JP3112047B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a high integration density and a reduced current consumption during standby.

[0002]

2. Description of the Related Art A CMOS circuit is well known as a semiconductor integrated circuit that consumes very little power during standby. When the input is at a high level, the p-channel MOS transistor is off and the n-channel MOS transistor is on. When discharging of the output capacitive load is completed, the n-channel MOS transistor is turned off. In this state, power consumption is ignored. it can. When the input is at a low level, the p-channel MOS transistor is on and the n-channel MOS transistor is off. When the charging of the output capacitive load is completed, the p-channel MOS transistor is turned off. On the other hand, while miniaturized MOS transistors are used in the internal circuits in the chip, the internal power supply voltage lower than the external power supply voltage must be reduced in the chip to cope with the breakdown voltage drop of the MOS transistors accompanying the miniaturization. A high-density semiconductor integrated circuit which is generated by a circuit (on-chip voltage limiter) and supplies this internal power supply voltage to the internal circuit has been disclosed in Japanese Patent Laid-Open No. 57-172.
761.

On the other hand, Japanese Patent Application Laid-Open No. 63-140486 discloses that while increasing the rising speed of a transient current in an internal circuit immediately after turning on a power supply, the peak value of the transient current is suppressed. Connect the current mirror circuit,
A method is disclosed in which a current supplied to an internal circuit is limited, and a rise in a voltage supplied to the internal circuit is clamped at a predetermined value by feedback.

[0004]

However, recent advances in fine processing technology used for semiconductor integrated circuits have been remarkable, and the processing size is approaching 0.1 μm. Compared with a MOS transistor having a channel length of 1 μm, a MOS transistor having a channel length of about 0.1 μm has a lower threshold voltage and a drain current of 0 even when the gate-source voltage is lower than the threshold voltage. No. The leakage current in a region where the gate-source voltage is equal to or lower than the threshold voltage is called a sub-threshold current, and is exponentially proportional to the gate-source voltage. On the other hand, the threshold voltage is defined in a region where the drain current is exponentially proportional to the gate-source voltage. For example, when the gate width is 10 μm, a drain current of 10 nA flows between the gate and the source. Voltage. There is a problem that the increase in the subthreshold current caused by miniaturization is contrary to the demand for lower power consumption of the integrated circuit. In particular, power consumption in a non-operating state of a semiconductor integrated circuit using miniaturized MOS transistors is determined by this sub-threshold current, and it is necessary to suppress this sub-threshold current to achieve low power consumption. .

By configuring a word driver for driving a word line of a semiconductor memory with a CMOS circuit, the power consumption of the semiconductor memory can be reduced. However, when the MOS transistors of the word driver CMOS circuit are miniaturized, the following problems occur. That is,
Since the parasitic capacitance of the word line is large, the gate width M
It is necessary to use an OS transistor as a driving transistor of a word driver. Therefore, the total gate width of the word driver reaches about half of the total gate width of the entire DRAM chip. However, since the subthreshold current increases in proportion to the gate width, the use of a MOS transistor having a large gate width as the drive transistor of the word driver causes a problem that the power consumption of the CMOS circuit of the word driver during standby increases.

That is, since a semiconductor memory generally uses a large number of word drivers, it is necessary to suppress the subthreshold current of a driving MOS transistor of a word driver constituted by a CMOS circuit. For example,
Taking a 4Mb DRAM as an example, a refresh period of 16 m
During 1sec, a period of about 15.9 msec (a period of 99% or more) is a period in which all the word lines are in a non-selected state. In this non-selected state, a subthreshold current of the driving MOS transistor of the word driver flows. Therefore, the power consumption in the non-selected state is determined by the subthreshold current of the driving MOS transistor miniaturized by the word driver. Such a problem is particularly serious in the case of a battery-operated semiconductor integrated circuit.

On the other hand, if the technique of the voltage dropping circuit disclosed in Japanese Patent Application Laid-Open No. 57-172761 is applied to a semiconductor memory such as the above-mentioned DRAM, the internal power supply voltage of an internal circuit including a MOS transistor having a large subthreshold current becomes Supplied from the output of the on-chip voltage limiter. However, in this case, since the on-chip voltage limiter does not have a current limiting function with respect to its output current, the above-mentioned problem of the subthreshold current cannot be reduced.

On the other hand, if the technique of the current mirror circuit disclosed in Japanese Patent Application Laid-Open No. 63-140486 is applied to a semiconductor memory such as the above-mentioned DRAM, the internal power supply voltage of an internal circuit including a MOS transistor having a large sub-threshold current is reduced. The internal power supply current is supplied from the output transistor of the current mirror circuit. However, in this case, although the current mirror circuit has a current limiting function of limiting the peak value of the transient current of the internal circuit to a predetermined value or less, the sub-threshold current corresponding to this predetermined value is smaller than the above-described sub-threshold current. This is a much larger value, and again cannot reduce the subthreshold current which has been considered above.

Accordingly, an object of the present invention is to provide a finely divided C
An object of the present invention is to provide a semiconductor integrated circuit in which power consumption during standby is not determined by a large subthreshold current accompanying miniaturization even when a MOS circuit is used.

[0010]

In order to achieve the above object, a switching MOS transistor is provided with a plurality of CMOS transistors.
The power supply is provided between a first power supply terminal common to the S circuit and an external power supply terminal or an internal power supply terminal which is an output of an on-chip voltage limiter, and has a gate of a switching MOS transistor.
A control signal having a voltage amplitude smaller than the absolute value of the threshold voltage is applied between the sources, and the first of the plurality of CMOS circuits is
A first sub-threshold flowing from the external power supply terminal or the internal power supply terminal which is the output of the on-chip voltage limiter through the source-drain path of the switching MOS transistor when the power supply terminal and the second power supply terminal are short-circuited. The current is supplied to a plurality of CMOS circuits of the same conductivity type as a switching MOS transistor whose source is electrically connected to the first power supply terminal and which is included in a plurality of CMOS circuits.
When a signal having a voltage amplitude smaller than the absolute value of the threshold voltage is applied between the gate and source of the S transistor and the source and drain of the switching MOS transistor are short-circuited, an external power supply terminal or an on-chip voltage Multiple CMOs from the internal power supply terminal that is the output of the limiter
The device parameters of the switching MOS transistor are set to be smaller than the second subthreshold current flowing through the source-drain path of the MOS transistor of the S circuit.

[0011]

In the standby state, the current of the plurality of off-state CMOS circuits is limited to the sub-threshold current of the off-state switching MOS transistor.

[0012]

EXAMPLES The present invention will be specifically described using examples. Unless otherwise specified, a symbol representing a terminal name also serves as a wiring name and a signal name, and in the case of a power supply, also serves as a voltage value.

FIG. 1 is a diagram showing a first embodiment of the present invention. Ci (i = 1 to n) is a logic circuit or a driver constituted by using CMOS transistors, and a simple CMOS inverter is taken as an example here, focusing on the driving of the output terminal Oi. Ii is its input terminal. VS and V
C is a power supply line from an external power supply or an internal power supply generated by an internal voltage conversion circuit such as an internal step-down circuit or an internal booster circuit. The external power supply voltage is, for example, about 1.5 to 3.6V. VC is set to, for example, 1.5 to 2.5V. V
S is usually 0V. The switch circuit S1 is inserted between Ci and VC. T1 is a control terminal of this switch circuit. For example, a MOS transistor or a bipolar transistor is used for the switch circuit S1. N1 is C
This is a first power supply terminal of the MOS inverter group. N2 is C
This is a second power supply terminal of the MOS inverter group.

The operation of this circuit will be described with reference to FIG.
Here, a case is considered where only one circuit (here, C1) operates during operation. In other words, the current supplied by the switch S1 during operation is only one circuit of Ci (current consumption in C1). In FIG. 2, T1
Is high level, S1 is turned on, and when T1 is low level, S1 is turned on.
1 is the case of turning off.

During the first standby, all inputs Ii of Ci are at high level VC and all outputs Oi are at low level VS. At this time, the p-channel MOS transistor is normally off, and the n-channel MOS transistor is normally on. However, a subthreshold current in an off state becomes a problem due to miniaturization. That is, the sub-threshold current which becomes a problem when the switch S1 is not provided is a current flowing from VC to VS through the off p-channel MOS transistor and the on n-channel MOS transistor when the output Oi is at a low level. . In the present embodiment, T1 is set to a low level during standby, and the switch S1 is turned off. However, even if the switch S1 is turned off, the leak current of the switch S1 cannot be ignored. However, the leak current of the switch S1 is set smaller than the above-described sub-threshold current. Therefore, at this time, the maximum current from VC to Ci is the leak current of the switch S1. Thus, even if a MOS transistor having a low threshold voltage is used for Ci for low-voltage operation, the current flowing through Ci is not determined by the subthreshold current but by the leak current of the small switch S1. You. Therefore, current consumption during standby is small.

Next, at the time of operation, T1 becomes high level, S1 is turned on, and S1 is in a state of supplying a current necessary for charging the output O1 of C1. Here, the input I1 changes to the low level VS, and the output O1 rises to the voltage VC by the current from the power supply VC. After that, the input I1 becomes the high level VC and the output O1 becomes the low level VS. When the above operation is completed, T1 goes low again in the standby state, and S1 turns off.

The switch S1 is a p-channel MOS
It can be formed by a transistor or a pnp bipolar transistor.

FIG. 3 is a diagram showing a second embodiment of the present invention. The difference from FIG. 1 is that a switch S is provided between VC and Ci.
1 instead of a switch S2 between VS and Ci.
And the first power supply terminal N1 and the second power supply terminal N
2 is the opposite. Others are the same as FIG.
The operation of this circuit is shown in FIG.

In the circuit of FIG. 3, the leak current of the switch S2 is set smaller than the subthreshold current of the n-channel MOS transistor of the circuit Ci in which a low potential is applied to the input Ii. Therefore, at this time, from Ci to V
The maximum current to S is the leakage current of switch S2. Thus, even if a MOS transistor having a low threshold voltage is used for Ci for low-voltage operation, the current flowing through Ci is not determined by the subthreshold current but by the leak current of the small switch S2. You. Therefore, current consumption during standby is small.

The switch S2 is an n-channel MOS
It can be formed by a transistor or an npn bipolar transistor.

FIG. 5 is a diagram showing a third embodiment of the present invention. In this embodiment, the switch S of the first embodiment shown in FIG.
1 is specifically configured by a p-channel MOS transistor. The current driving capability of the p-channel MOS transistor S1 is set in consideration of the number of circuits Ci that charge the output Oi in response to the low-potential input Ii. On the other hand, in order to reduce the current consumption during standby, it is necessary to reduce the leak current of the switch S1 as described above.
Therefore, it is necessary to set device parameters of the p-channel MOS transistor of the switch S1. For example, the gate width of the p-channel MOS transistor of the switch S1 is equal to the total p-channel MOS of the circuits C1, C2,.
The gate width is set smaller than the sum of the gate widths of the transistors and larger than the gate width of the p-channel MOS transistor of one circuit Ci. In order to reduce the leak current, it is possible to increase the threshold voltage of the p-channel MOS transistor of the switch S1, increase the gate length, or increase the gate insulating film thickness. As a result, current consumption during standby can be reduced.

The operation of this circuit will be described with reference to FIG.
In operation, only one circuit C1 outputs a high potential.

First, in the first standby mode, all inputs Ii of Ci are at high level VC, and all outputs Oi are at low potential VS, as in the previous embodiment. Also, C1, C2 ...
Since the sub-threshold current flowing through the switch element S1 is smaller than the sum of the sub-threshold currents of Cn,
The potential of the common power supply terminal N gradually decreases. Then, for example, considering the p-channel MOS transistor of the circuit C1, the gate voltage is VC and the source voltage is VC
Lower. That is, since the p-channel MOS transistor is turned off more strongly, the subthreshold current is greatly reduced. The dependency of the subthreshold current on the gate-source voltage is about DECADE / 100
It is about mV. Therefore, if the voltage drops by 0.2 V, the subthreshold current becomes 1/100.
Therefore, when the standby period is extended to some extent, the current consumption can be reduced to a negligible level due to the potential drop of the terminal N.

During operation, p-channel MOS transistor S
The difference from the previous embodiment is that T1 becomes the low level VS because 1 is turned on, and the rest is the same as the previous embodiment. It is to be noted that the switch S1 can be formed by a pnp bipolar transistor.

In the case of using a bipolar transistor, at least one power supply terminal of a plurality of CMOS circuits having first and second power supply terminals and an external power supply terminal or an internal power supply terminal which is an output of an on-chip voltage limiter are provided. An npn or pnp switching bipolar transistor is provided between them. The first of the plurality of CMOS circuits
And the leakage current when the switching bipolar transistor is off when the second power supply terminal is short-circuited, and the sub-threshold current when the plurality of CMOS circuits when the switching bipolar transistor is short-circuited (not short-circuited) when the switching bipolar transistor is short-circuited. The device parameters of the switching bipolar transistor are set so as to reduce The device parameter is, for example, an emitter width.

FIG. 7 shows a fourth embodiment of the present invention. In this embodiment, the potential of the first power supply terminal N1 is maintained at a predetermined potential between VC and VS between the power supplies VC and Ci in parallel with the switch S1 of the third embodiment shown in FIG. It is characterized by having a voltage clamp circuit L.

For example, the voltage clamp circuit L is constituted by a source follower-operating n-channel MOS transistor having a drain set to VC, a gate set to a predetermined potential, and a source connected to the terminal N1. You. In this embodiment, this voltage clamp circuit is realized by a diode-connected n-channel MOS transistor whose gate and drain are short-circuited.

The features and operation of this circuit will be described with reference to FIG. The initial state is the same as the case described with reference to FIGS. At this time, the potential of the common power supply terminal N1 of Ci is
As shown in the figure, when there is a voltage clamp circuit L (solid line)
When there is no (dashed line), it is different during standby. If the standby time is extremely long, the potential of the terminal N1 drops to VS in the worst case due to the subthreshold current flowing through Ci and other leak currents when the voltage clamp circuit L is not provided. For this reason, in order to shift from standby to operation, the common power supply terminal N1 must first be charged, so that the shift to the operation state is delayed until the charging is completed. On the other hand, when the threshold voltage of the n-channel MOS transistor constituting the voltage clamp circuit L is VT,
When there is a voltage clamp circuit L, the potential of the common power supply terminal N decreases only to VC-VT. Therefore, the transition to the operation state is completed in a short time. Note that N1 is set so that the sub-threshold current of Ci at the standby time when VC is applied to the input is negligibly small as in the previous embodiment.
Of the clamp potential VC-VT is set.
For example, when VT is set to 0.2 V, the dependence of the sub-threshold current on the gate-source voltage is DECADE / 100.
With mV, the subthreshold current can be reduced to 1/100 or less.

The present invention provides an operation mode in which a semiconductor integrated circuit including many CMOS circuits of the same type enters a standby state (a state in which output of valid data cannot be guaranteed from an output in a state in which power supply voltage is not substantially supplied). Is suitable for reducing the current consumption in the standby state.

A semiconductor memory, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), or an EEPRO
A non-volatile memory such as M has a word decoder, a word driver, a Y-system decoder, and a Y-system driver. Therefore, if the current consumption of such a decoder or driver is greatly reduced in a standby state of the semiconductor memory in which it is not possible to guarantee that valid data is output from the output, long-term battery operation can be guaranteed.

By applying the CMOS circuit of the present invention to such a decoder or driver, current consumption is greatly reduced, and long-term battery operation can be guaranteed.

FIG. 9 is a diagram showing an example in which the present invention is applied to a word driver / decoder of a dynamic random access memory. WD1 to WD8 are word drivers corresponding to Ci in FIG. 1, and a switch for supplying a current from the power supply VCH to this is S11. XD1 is a decoder, which also corresponds to Ci in FIG.
The switch that supplies current from L is S12. The power supply voltage VCH for the word drivers WD1 to WD8 is set to a high voltage necessary for sufficiently obtaining a storage voltage of a memory cell (not shown). For example, if the storage voltage of the memory cell is 1.5V, VCH is set to 2.5V. Since the power supply voltage VCL for the decoder XD1 does not need to directly drive the memory cells, the power supply voltage VCL is set to a voltage as low as possible so that current consumption is reduced and speed is not significantly degraded. For example, it is set to 1.5V. Therefore, VCH is set higher than VCL. VCH can also be obtained, for example, by boosting the external power supply voltage. A circuit block XB1 is composed of WD1 to WD8 and XD1, and there is shown a case where there are n such circuit blocks XB1 to XBn. W11
To Wn8 are word lines. In WD1, the pMOS MW1 and the nMOS MW2 are CMOS inverters that drive the word line W11. XDPH is a precharge signal. The basic operation of this WD1 is disclosed in
As shown in 2-178013, while the nMOS MS1 is off, the PMOSMP1 is turned on by the XDPH and the terminal N
3 is precharged to VCH and the output of the CMOS inverter, W11, is set to low level VS.
That is, SMS1 is selectively turned on to lower the potential of N3 to invert the CMOS inverter.
The pMOS MF1 applies weak feedback from the output of the CMOS inverter to the input to prevent malfunction. MS1
Is controlled by Xm and an output N2 of a decoder described later. Conventionally, in such a word driver, pMOS
MW1 was directly connected to the power supply VCH together with other word drivers. Since the MW1 generally has a large load on the word line, a MW1 having a large gate width is used. For this reason, the total gate width of a large number of word drivers occupies most of the total gate width of the logic circuits of the entire chip.
Conventionally, a MOS having such a large gate width has a power supply VC.
H was connected. For this reason, the power supply voltage is lowered in accordance with the reduction in the withstand voltage between the source and drain of the MOS due to the miniaturization of the processing technology, and if the threshold voltage is lowered to maintain the high-speed operation under this power supply voltage, the sub-threshold current is reduced. However, there is a problem in that the number increases. This results in an increase in standby current, and even if the battery can be driven by lowering the voltage, this is an obstacle in terms of current consumption. In the present invention, a switch S11 is provided between the word driver power supply VCH and a number of word drivers. Many word drivers are connected to the output VCHL of the switch S11. The switch S11 is formed of a pMOS, and the pM
The gate width of the OS need only be small as long as it can supply current to the word driver that operates at a time. This p
Since the MOS is connected to VCH, the sub-threshold current can be reduced. Thereby, the conventional problem is solved. For example, the gate width of MW1 is set to 20 μm.
m, and if one S11 is provided for every 512 word drivers, pM controlled by T11 in this S11
The gate width of the OS may be as large as 200 μm. The threshold voltage of the pMOS is set to be higher than MW1 by, for example, 0.1 V in absolute value. Thus, the subthreshold current can be reduced by three digits.

The same applies to the configuration of the decoder XD1. The only difference from the word driver is that two-stage series nMOSs MS21 and MS22 are arranged in place of the word driver MS1. MD1 and MD2 are CMOS inverters that drive the output terminal N2 of the decoder.
Is a PMOS for precharge, XDP is a precharge signal, and MF2 is a pMOS that applies weak feedback from the output of the CMOS inverter to the input. MS2
1 and MS22 are controlled by Xi, Xj and Xk. Conventionally, even in such a decoder, the MD1 is directly connected to the power supply VCL. For this reason, a large number of MOSs of decoders are connected to the VCL, and a fine sub-threshold current will flow if the threshold voltage is reduced in accordance with a reduction in the power supply voltage as the processing technology becomes finer. Using the present invention, a switch S12 is provided between a power supply and a number of decoders, and this output VCLL is connected to the decoder. In this case, the gate width of the pMOS constituting this switch can be small because it is sufficient to supply a current to a small number of operating decoders. Since this pMOS is connected to VCL, the subthreshold current can be reduced.

Next, the operation of this circuit will be described with reference to FIG. Although not shown in FIG. 9, / RAS is a signal which is applied to the chip and controls whether or not to operate the word driver / decoder group. A signal necessary for operating the circuit of FIG. 9 by a circuit in the chip not shown in FIG. 9 is generated from this signal and a so-called address signal for designating which word line to be applied from the outside of the chip. I do. Initially, / RAS is high and the chip is on standby. At this time, Xi is high level V
CL and Xj and Xk are low level VS, so that M
S21 and MS22 are turned off, and the decoder is in a non-selected state. Further, since XDP is a low level VS, pMO
SMP2 is turned on and the input N1 of the CMOS inverter of the decoder is precharged to VCL, so that the output N2 of the decoder is at the low level VS. On the other hand, in the word driver, Xm is high level VCL and N2
Is the low level VS as described above, so the nMOS MS1
Is off. Since XDPH is at the low level VS, the pMOS MP1 is turned on and N3 is precharged to the high level VCH, so that the word line W11 is at the low level. The same applies to other word driver / decoders, and all word lines are at low level VS. Next, in the operating state, / RAS goes low, and the precharge signal XDP becomes high level VCL, XDP
H goes to the high level VCH. T11 and T12 are also at the low level VS, and the switches S11 and S12 are turned on.
Further, Xi and Xm become low level VS and Xj and Xm
k becomes the high level VCL. Thereby, N1 is discharged toward Xi to the low level VS because M21 and M22 are turned on. Therefore, N1 is at the high level VCL, and Xm is at the low level VS, so that MS1 is turned on, and N3 is discharged toward Xi to the low level VS. As a result, W11 becomes high level, and the memory cell connected thereto is selected. Thereafter, when / RAS changes to a high level again, Xi, X
Since j, Xk, and Xm return to the standby state, and XDP and XDPH also return to the initial state, the word driver / decoder is deselected and precharged for the next operation. FIG. 9 shows the case of a word driver / decoder, but this can be applied to a Y driver / decoder. In this case, since it is not necessary to directly drive the memory cells, VCH in FIG.
The potential may be the same as L.

FIG. 11 shows the switches S11 and S1 of FIG.
2 shows an example of the control circuit. MA is an input signal of this control circuit. In FIG. 11, T11 is provided for S11 and T12 is provided for S12, but this control circuit controls S11 and S12 by one output signal T. The operation of this circuit will be described with reference to FIG. In a non-selection state where / RAS is at a high level, nMOS MG2 is off because MA is at a low level VS. Also, CM
M1 is at a high level VCL due to the OS inverter.
For this reason, in the level conversion circuit which constitutes a flip-flop and whose power supply is connected to VCH, M2 is low level VS
And the pMOS MG1 is on. Therefore, T is a high level VCH, and the switch S11
And S12 are off. Next, when / RAS goes high and becomes active, MA goes high VCL,
M1 becomes the low level VS. As a result, the NOR flip-flop is inverted, and M2 becomes the high level VCH. Here, since MA is input to the gate of nMOSMG2, when MA goes high, nMOSMG
2 turns on. The pMOS MG1 is also turned off with a delay because the above operation causes M2 to be at a high level. However, by setting the gate width of MG2 to be sufficiently larger than that of MG1, a change in MA to a high level VCL causes T to become low. VS. Since it is necessary for the high-speed operation that the switches S11 and S12 are turned on as soon as possible at the time of the operation, it is preferable to adopt such a circuit configuration. When / RAS goes high and returns to the unselected state, MA goes low first and MG goes low.
Turn 2 off. Next, the flip-flop operates and the MG
1 turns on and sets T to a high level. As a result, the switches S11 and S12 are turned off.

FIG. 13 is a diagram showing the configuration of a data processing system using the semiconductor memory of the present invention in a storage device M.
Arrows indicate signal flow. M is the DRA using the present invention
M, the CPU is a processing unit that controls the entire system, and R is
AG is a refresh address generator, TC is a control signal generator, SLCT is a selector for switching between an address signal sent from the CPU and a refresh address signal sent from the RAG, and PFY is another device in the system. (For example, an external storage device, a display device, a numerical operation device, etc.). The PFY may be connected to another information processing device through a communication line.

DATA is data communicated between the CPU and M, Aic is an address signal generated by the CPU,
Air is a refresh address signal generated by RAG, Ai is an address signal selected by SLCT and sent to M, ST is a status signal sent from CPU to RAG, BS is a busy signal from TC to CPU, and SE is A signal for starting SLCT sent from TC.
AS and / CAS are signals for starting the DRAM using the present invention. The SG collectively represents the exchange of signals between the CPU and other devices in the system. M
For example, an SRAM or an EEPROM may be used. At this time, of course, a start signal and a control signal corresponding thereto exist.

In the embodiment of FIG. 13, the / RAS signal and / C
AS signal is set to a high level, and the DRAM storage device M
Shifts to the standby state with very low current consumption as described in the previous embodiment. At this time, the CPU can also be put into the standby state with low power consumption by the sleep command, and the other peripheral devices can also be put into the standby state with low power consumption.

In a semiconductor integrated circuit using the present invention, the current consumption can be smaller than the sub-threshold current of a MOS transistor having a small threshold voltage under a low power supply voltage suitable for driving a battery. Therefore, it is possible to realize a semiconductor integrated circuit having a high speed, a low voltage, and a small standby current.

[0040]

According to the present invention, the leakage current of the switch transistor constituting the power switch which is turned off during standby is reduced to a plurality of CMs.
P-channel or n-channel M in the off state of the OS circuit
The device parameters of the switch transistor are set so as to be smaller than the sum of the sub-threshold currents of the OS. Therefore, the current flowing through the plurality of CMOS circuits during standby is set not by the subthreshold current of the plurality of CMOS circuits but by the small leak current of the switch transistor. Thus, the CMOS circuit is miniaturized,
Even when the sub-threshold current increases, the current consumption during standby can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment.

FIG. 2 is a diagram illustrating the operation of the first embodiment.

FIG. 3 is a diagram showing a second embodiment.

FIG. 4 is a diagram illustrating the operation of the second embodiment.

FIG. 5 is a diagram showing a third embodiment.

FIG. 6 is a diagram illustrating the operation of the third embodiment.

FIG. 7 is a diagram showing a fourth embodiment.

FIG. 8 is a diagram showing the operation of the fourth embodiment.

FIG. 9 is a diagram showing an application of the present invention to a word driver / decoder.

FIG. 10 is a diagram showing the operation of the circuit of FIG. 9;

FIG. 11 is a diagram illustrating an example of a control circuit.

FIG. 12 is a diagram illustrating the operation of the circuit of FIG. 11;

FIG. 13 is a diagram showing a system configuration using the present invention.

[Explanation of symbols]

S, S1, S2, S11, S12... Switch, T, T
1, T2, T11, T12 ... switch control terminal, Ci ...
Numerous circuits operating only a small number at a time, N1, N2 ... power supply terminals, VC ... high potential side power supply, VS ... low potential side power supply, I
.., Input, O, output, VCH, high-potential power supply for word driver, VCL, high-potential power supply for decoder, WD1 to WD
8 Word driver, XD1 Decoder, XB1 to XB
n: word driver / decoder, W11 to Wn8: word line, Xi, Xj, Xk, Xl: word driver / decoder selection signal, MA: control circuit input signal, M: memory,
DRAM, CPU: System control processing device, SLT: Address select device, RAG: Refresh address generator, TC: Control signal generator, PFY: Other devices in the system, DATA: Data signal, Aic, Air,
Ai: Address signal, ST: Status signal, BS: Busy signal, SE: Start signal, / RAS, / CAS: DR
AM start signal.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takesada Akiba 3681 Hayano, Mobara City, Chiba Prefecture Inside Hitachi Device Engineering Co., Ltd. (72) Inventor Masashi Horiguchi 1-280 Higashi Koikebo, Kokubunji City, Tokyo Hitachi, Ltd. Central Inside the research institute (72) Inventor Takao Watanabe 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. Inventor Yasushi Kawase 3681 Hayano Mobara-shi, Chiba Prefecture Hitachi Device Engineering Co., Ltd. (72) Inventor Toshikazu Tachibana 3681-Hayano Mobara-shi Chiba Prefecture Hitachi Device Engineering Co., Ltd. (72) Inventor Masakazu Aoki Tokyo 1 Higashi Koigakubo, Kokubunji City 280 Hitachi Research Institute, Ltd. (56) References JP-A-6-29834 (JP, A) JP-A-5-110392 (JP, A) JP-A-5-268065 (JP, A) Nikkei Microdevices (1993-3) P. 48-51 (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 11/4074

Claims (37)

(57) [Claims] And 1. A electronic circuit including a first 1MOS transistor having a source-drain path between the second potential point is lower potential than the first potential point and said first potential point, than the first potential point Having a source / drain path between a third potential point, which is also a high potential, and the first potential point.
An OS transistor; applying a control signal to the gate of the second MOS transistor to set the control signal to a first state,
Turning on the S transistor to allow a current to flow between the first potential point and the second potential point via the source / drain path of the on-state first MOS transistor; By setting the two states, the second MO
When the S transistor is turned off, a sub-threshold current flowing between the first potential point and the second potential point via the source / drain path of the first MOS transistor in the off state is set to the off state of the second MOS transistor. Limited by characteristics, the second M
A semiconductor integrated circuit, wherein the OS transistor is a p-channel MOS transistor. 2. The method according to claim 1, wherein the subthreshold current is equal to the first threshold voltage.
2. The semiconductor integrated circuit according to claim 1, wherein the current flows due to the processing dimension of the MOS transistor being in a 0.1 μm region. 3. The semiconductor integrated circuit according to claim 1, wherein an absolute value of a threshold voltage of said second MOS transistor is larger than an absolute value of a threshold voltage of said first MOS transistor. 4. An electronic circuit including a first MOS transistor having a source / drain path between a first potential point and a second potential point lower than the first potential point; Having a source / drain path between a third potential point, which is also a low potential, and the second potential point.
An OS transistor; applying a control signal to the gate of the second MOS transistor to set the control signal to a first state,
Turning on the S transistor to allow a current to flow between the first potential point and the second potential point via the source / drain path of the on-state first MOS transistor; By setting the two states, the second MO
When the S transistor is turned off, a sub-threshold current flowing between the first potential point and the second potential point via the source / drain path of the first MOS transistor in the off state is set to the off state of the second MOS transistor. Limited by characteristics, the second M
A semiconductor integrated circuit, wherein the OS transistor is an n-channel MOS transistor. 5. The method according to claim 1, wherein the sub-threshold current is the first
5. The semiconductor integrated circuit according to claim 4, wherein the current flows due to the processing dimension of the MOS transistor being in a 0.1 μm region. 6. The semiconductor integrated circuit according to claim 4, wherein an absolute value of a threshold voltage of said second MOS transistor is larger than an absolute value of a threshold voltage of said first MOS transistor. 7. The semiconductor integrated circuit according to any one of claims 1 to 6 in that the electronic circuit is a CMOS circuit. 8. A plurality of word lines, a plurality of data lines intersecting the plurality of word lines, and a memory cell arranged at an intersection of the plurality of word lines and the plurality of data lines. 8. The semiconductor integrated circuit according to claim 1, wherein said electronic circuit constitutes a word driver circuit for selecting said plurality of word lines. 9. A method according to claim 1 , wherein a source is connected between a first potential point and a second potential point.
A p-channel first MOS transistor having a drain path and a source connected to the first potential point; and a source / drain path between the first potential point and the second potential point; An n-channel type second MOS transistor connected in series with the first MOS transistor, a source / drain path between a third potential point and the first potential point, and a source connected to the third potential point Third
A MOS transistor, and applying a control signal to a gate of the third MOS transistor to set the control signal to a first state, thereby setting the third MOS transistor to a third state.
Turning on the S transistor to allow a current to flow between the first potential point and the second potential point via the source / drain path of the on-state first MOS transistor; By setting two states, the third MO
When the S transistor is turned off, a sub-threshold current flowing between the first potential point and the second potential point via the source / drain path of the first MOS transistor in the off state is set to the off state of the third MOS transistor. The first M
A semiconductor integrated circuit, wherein the conductivity type of an OS transistor is equal to the conductivity type of the third MOS transistor. 10. The semiconductor integrated circuit according to claim 9, wherein said subthreshold current flows due to a processing dimension of said first MOS transistor being in a 0.1 μm region. 11. The semiconductor device according to claim 9, wherein the absolute value of the threshold voltage of said third MOS transistor is larger than the absolute value of the threshold voltage of said first MOS transistor.
Or the semiconductor integrated circuit according to 10. 12. A p-channel type first MOS transistor having a source / drain path between a first potential point and a second potential point, and a source / drain between the first potential point and the second potential point. An n-channel second MOS transistor having a drain path, connected in series with the first MOS transistor, and having a source connected to the second potential point; a source connected between a third potential point and the second potential point; A third transistor having a drain path and a source connected to the third potential point;
A MOS transistor, and applying a control signal to a gate of the third MOS transistor to set the control signal to a first state, thereby setting the third MOS transistor to a third state.
Turning on the S transistor to allow a current to flow between the first potential point and the second potential point via the source / drain path of the on-state second MOS transistor; By setting two states, the third MO
When the S transistor is turned off, a sub-threshold current flowing between the first potential point and the second potential point via the source / drain path of the second MOS transistor in the off state is set to the off state of the third MOS transistor. Limited by characteristics, the second M
A semiconductor integrated circuit, wherein the conductivity type of an OS transistor is equal to the conductivity type of the third MOS transistor. 13. The semiconductor integrated circuit according to claim 12, wherein said subthreshold current flows due to a processing dimension of said first MOS transistor being in a 0.1 μm region. 14. The semiconductor device according to claim 1, wherein an absolute value of a threshold voltage of said third MOS transistor is larger than an absolute value of a threshold voltage of said first MOS transistor.
14. The semiconductor integrated circuit according to 2 or 13. 15. A first conductive type first transistor having a source / drain path between a first potential point and a second potential point .
MOS transistor and second MOS transistor of second conductivity type
A plurality of MOS circuit comprising a static source of the first 1MOS transistor being connected to said first potential point, the source-drain path of the source-drain path and a second 2MOS transistor of the first 1MOS transistor connected in series And a source / drain between the third potential point and the first potential point.
A third source having a path and having a source connected to the third potential point;
A MOS transistor is provided, and a control signal is applied to the gate of the third MOS transistor.
By setting the control signal to the first state, the third MO
The S transistor is turned on, and the first potential point and the
The first MOS transistor in an ON state between the first MOS transistor and the second potential point.
When current flows through the source / drain path of the
And the control signal is set to the second state, whereby the third MO
The S transistor is turned off, and the first potential point and the
The first MOS transistor in an off state between the second MOS transistor and the second potential point.
Sub-threshold flowing through the source / drain path of the
The threshold current to the off state of the third MOS transistor.
Is limited by the characteristics of the state .
A semiconductor integrated circuit, wherein a gate width of an OS transistor is smaller than a sum of gate widths of the first MOS transistors included in each of the MOS circuits. 16. The semiconductor integrated circuit according to claim 15 , wherein a gate width of said third MOS transistor is larger than one gate width of said first MOS transistor. 17. A plurality of first MOS transistors each having a source / drain path between a first potential point and a second potential point.
It has a transitional scan data, the source of the first 1MOS transistor are respectively connected to said first potential point, the source and drain between the third potential point and the first potential point
A second path having a path and a source connected to the third potential point;
A MOS transistor is provided, and a control signal is applied to a gate of the second MOS transistor.
By setting the control signal to the first state, the second MO
The S transistor is turned on, and the first potential point and the
The first MOS transistor in an ON state between the first MOS transistor and the second potential point.
When current flows through the source / drain path of the
By allowing the control signal to be in the second state,
The S transistor is turned off, and the first potential point and the
Serial the second 1MO S Trang off state between the second potential point
Sub-threshold flowing through the source / drain path of the
The threshold current to the off state of the second MOS transistor.
A limiting by properties of the state, the first 2M
A semiconductor integrated circuit, wherein the gate width of the OS transistor is smaller than the sum of the gate widths of the first MOS transistors. 18. A source between a first potential point and a second potential point.
・ Has a drain path, and the source is connected to the first potential point
And a source / drain between the first MOS transistor of the first conductivity type and the first potential point and the second potential point.
An in-path and connected in series with the first MOS transistor.
A second MOS transistor of the second conductivity type connected between the third potential point and the first potential point;
A third source having a path and having a source connected to the third potential point;
And a control signal applied to the gate of the third MOS transistor.
By setting the control signal to the first state, the third MO
The S transistor is turned on, and the first potential point and the
The first MOS transistor in an ON state between the first MOS transistor and the second potential point.
When current flows through the source / drain path of the
And the control signal is set to the second state, whereby the third MO
The S transistor is turned off, and the first potential point and the
The first MOS transistor in an off state between the second MOS transistor and the second potential point.
Sub-threshold flowing through the source / drain path of the
The threshold current to the off state of the third MOS transistor.
A semiconductor integrated circuit that is limited by the characteristics of the state and includes means for maintaining a predetermined potential between the third potential point and the first potential point . 19. An absolute value of a threshold voltage of the third MOS transistor is equal to the first or second MOS transistor of the same conductivity type.
19. The semiconductor integrated circuit according to claim 18 , wherein the absolute value of the threshold voltage of the transistor is larger than the absolute value of the transistor. 20. The semiconductor integrated circuit according to claim 18 , wherein a gate width of said third MOS transistor is smaller than a sum of gate widths of said first MOS transistor connected to a drain of said third MOS transistor. 21. A semiconductor integrated circuit according to any one of claims 18 to claim 20 said means characterized in that it is constituted by a diode. 22. The method according to claim 19, wherein the means includes a source / drain path.
And between the third potential point and the first potential point,
The MOS transistor different in conductivity type of 4MO
The fourth MOS transistor and the third MOS transistor.
22. The semiconductor integrated circuit according to claim 18 , wherein the sources of the MOS transistors have the same potential. 23. A source voltage between a first potential point and a second potential point.
A drain path having a source connected to the first potential point;
A connected first MOS transistor, and a source / drain between the first potential point and the third potential point.
A second path having a path and a source connected to the third potential point;
A MOS transistor, and a dam provided between the first potential point and the third potential point.
And a control signal is applied to the gate of the second MOS transistor.
By setting the control signal to the first state, the second MO
The S transistor is turned on, and the first potential point and the
The first MOS transistor in an ON state between the first MOS transistor and the second potential point.
When current flows through the source / drain path of the
By allowing the control signal to be in the second state,
The S transistor is turned off, and the first potential point and the
The first MOS transistor in an off state between the second MOS transistor and the second potential point.
Sub-threshold flowing through the source / drain path of the
The threshold current to the off state of the second MOS transistor.
A limiting by properties of the state, the first 2M
When OS transistor is off, the semiconductor integrated circuit characterized by having a state in which the voltage of the source and the gate of the first 1MOS transistor are different. 24. The first 1MOS transistor is constituted by a p-channel type, the claims said first 2MOS transistor is off state, the gate potential of the first 1MOS transistor, characterized in that the take higher than the source potential 24. The semiconductor integrated circuit according to 23 . 25. The diode is constituted by the 3MOS transistor different in conductivity type of the first 2MOS transistor, said first 3MOS transistor has a source-drain path
Between the first potential point and the third potential point.
The semiconductor integrated circuit according to any one of claims 23 to claim 24 bets are characterized by being connected to the third potential point. 26. A semiconductor device comprising: a first MOS transistor of a first conductivity type; and one or more MOS circuits having a common first power supply terminal and a common second power supply terminal; The gate of the transistor is controlled by a control signal, the source of the first MOS transistor of the first conductivity type is electrically connected to a first operating potential, and the drain of the first MOS transistor of the first conductivity type is the first MOS transistor of the first conductivity type. The second power supply terminal is electrically connected to a second operating potential, and the source included in all the MOS circuits is electrically connected to the second power supply terminal.
All the first conductivity types connected to the first power supply terminal.
Between the gate and source of the second MOS transistor.
A signal with a voltage smaller than the absolute value of the threshold voltage is applied.
In this case, all the MOS transistors are deviated from the first operating potential.
Source of the second MOS transistor of the first conductivity type of the circuit
Flows to the second operating potential through the drain channel
Sub-threshold current is
Current value, wherein the predetermined sub-threshold current is the first conductivity type.
Between the gate and source of the first MOS transistor
Breaking of the threshold voltage of the first conductivity type first MOS transistor
When the above control signal of a voltage smaller than the pair value is applied
In addition, a first MO of the first conductivity type is obtained from the first operating potential.
Through the source-drain path of the S transistor
Sub-threshold current flowing through the power supply terminal
And a semiconductor integrated circuit. 27. The control signal having a voltage smaller than an absolute value of a threshold voltage of the first MOS transistor of the first conductivity type is applied between a gate and a source of the first MOS transistor of the first conductivity type, and When the first power supply terminal and the second power supply terminal of all of the MOS circuits are short-circuited, the first operation potential is passed through the source-drain path of the first MOS transistor of the first conductivity type. A sub-threshold current flowing at the second operating potential is defined as a first sub-threshold current, and all the first conductivity types whose sources included in all the MOS circuits are electrically connected to the first power supply terminal are used. A signal having a voltage smaller than the absolute value of the threshold voltage is applied between the gate and the source of the second MOS transistor, and the first MOS transistor of the first conductivity type is applied. When the source-drain of the transistor is short-circuited, the first operating potential is changed to the second operating potential through the source-drain paths of the second MOS transistors of the first conductivity type of all the MOS circuits. The flowing sub-threshold current is defined as a second sub-threshold current, and the device parameters of the first MOS transistor of the first conductivity type are set such that the first sub-threshold current is smaller than the second sub-threshold current. 27. The semiconductor integrated circuit according to claim 26, wherein: 28. The semiconductor integrated circuit according to claim 26, wherein said MOS circuit is a CMOS circuit.
circuit. 29. A second MO of the first conductivity type of the MOS circuit.
27. The semiconductor integrated circuit according to claim 26 , wherein the S transistor forms a CMOS inverter circuit with a second conductivity type MOS transistor included in the MOS circuit. 30. An absolute value of a threshold voltage of the first MOS transistor of the first conductivity type is larger than an absolute value of a threshold voltage of the second MOS transistor of the first conductivity type included in the MOS circuit. Claim 26
30. A semiconductor integrated circuit according to claim 29 . 31. A semiconductor device according to claim 26, wherein a gate width of said first conductivity type first MOS transistor is smaller than a sum of gate widths of all said first conductivity type MOS transistors included in said MOS circuit. Any of claim 30
13. A semiconductor integrated circuit according to 32. The MOS transistor according to claim 26, wherein a gate length of said first conductivity type first MOS transistor is longer than a gate length of said first conductivity type MOS transistor included in said MOS circuit. A semiconductor integrated circuit according to any one of the above. 33. A claim, wherein the gate insulating film thickness of the 1MOS transistor of the first conductivity type is greater than the thickness of the gate insulating film of the MOS transistor of the first conductivity type included in the MOS circuit 26 To claim 32
A semiconductor integrated circuit according to any of the preceding claims. 34. A plurality of word lines, a plurality of data lines intersecting the plurality of word lines, and a memory cell arranged at an intersection of the plurality of word lines and the plurality of data lines. 34. The semiconductor integrated circuit according to claim 26 , wherein said plurality of CMOS circuits constitute a word driver circuit for selecting said plurality of word lines. 35. A bipolar transistor and a plurality of capacitors having a common first power supply terminal and a second power supply terminal.
A MOS circuit, wherein the emitter of the bipolar transistor is electrically connected to a first operating potential, the base of the bipolar transistor is controlled by a control signal, and the collector of the bipolar transistor is connected to the first power supply terminal. The second power supply terminal is electrically connected to a second operating potential, the control signal having a voltage smaller than a base-emitter forward voltage is applied between a base and an emitter of the bipolar transistor, and When the first power supply terminal and the second power supply terminal of the plurality of CMOS circuits are short-circuited, a leak current flowing through the emitter-collector path of the bipolar transistor is included in the plurality of CMOS circuits. A plurality of first conductivity type second MOS transistors whose sources are electrically connected to the first power supply terminal. When a signal smaller than the absolute value of the threshold voltage is applied between the gate and the source of the transistor and the source and the drain of the bipolar transistor are short-circuited, the plurality of the plurality of transistors are deviated from the first operating potential. The plurality of first conductivity type second M of the CMOS circuit
A semiconductor integrated circuit, wherein device parameters of said bipolar transistor are set so as to be smaller than a subthreshold current flowing to said second operating potential through a source-drain path of an OS transistor. 36. When the bipolar transistor is a pnp type, the first conductivity type is p-channel and the second conductivity type is n-type.
The semiconductor integrated circuit according to claim 35 , wherein the semiconductor integrated circuit is a channel. 37. When the bipolar transistor is of npn type, the first conductivity type is n-channel and the second conductivity type is p-channel.
The semiconductor integrated circuit according to claim 35, wherein the semiconductor integrated circuit is a channel.