JP4600835B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to an improvement in a circuit configuration for reducing leakage current due to sub-threshold characteristics of a MOS transistor, and relates to a semiconductor integrated circuit in which an element is miniaturized and an operation voltage is made constant. For example, a storage capacity is 256 M to 1 G. The present invention relates to a technology that is effective when applied to a large-capacity DRAM (Dynamic Random Access Memory) of bit or more.

  A semiconductor integrated circuit, for example, a DRAM that has been highly integrated, has a low operating voltage of 2 to 2.5 V due to miniaturization of elements, and the threshold voltage of a MOS transistor is required for high speed operation. The voltage is lowered to 0.15 to 0.2 V (conventionally about 0.4 V). Then, a leakage current (subthreshold current) due to the subthreshold characteristic of the MOS transistor becomes a problem. The subthreshold current is a leak current that tends to flow when the gate voltage is equal to or lower than the threshold voltage and the surface is in a weakly inverted state.

  The present inventor examined the application of a circuit for reducing the subthreshold current (Subthreshold Current Reduction Circuit, hereinafter abbreviated as SCRC) to a DRAM.

  In FIG. 16 showing an example of the SCRC examined previously by the present inventor, logic circuits L1 to L4 typified by a CMOS inverter are targeted for reducing the subthreshold current. The period in which the subthreshold current needs to be reduced is, for example, a standby state, and the input signal IN to the logic circuit L1 is set to a low level (“L”) in the standby state. Accordingly, in order to suppress the generation of subthreshold currents in the MOS transistors Qn1, Qp2, Qn3, Qp4 to be controlled to be turned off in the standby state, the main power supply wiring ML1 supplied with the power supply voltage VDD and the ground voltage VSS are suppressed. Are supplied to the main power supply line ML2 to which the main power supply line ML2 is supplied, a switch SD is provided between the main power supply line ML1 and the sub-source line SL1, and the main power supply line ML2 and the sub power supply line SL2 are connected to each other. A switch SS is provided between them. The switches SD and SS are controlled to be turned off in the standby state. When the switches SD and SS are turned off, the potential of the sub power supply line SL1 falls below the power supply voltage VDD of the main power supply line ML1, and the potential of the sub power supply line SL2 rises above the ground voltage VSS of the main power supply line ML2. Thereby, a reverse bias voltage is applied between the gates and sources of the off-state MOS transistors Qn1, Qp2, Qn3, and Qp4 in each of the logic circuits L1 to L4, and the subthreshold current is reduced.

Examples of documents describing SCRC include, for example, Japanese Patent Application Laid-Open Nos. 5-210976 and 5-347550.
Japanese Patent Application Laid-Open No. 5-210976 JP-A-5-347550

  The inventor examined the SCRC and found the following problems. The first problem of SCRC is a voltage drop due to the wiring resistance of the power supply wiring, particularly the sub power supply wiring. In SCRC, since the number of power supply wirings is doubled to 4, the wiring width per wiring must be narrowed in terms of layout, and the wiring resistance increases. When the potential of the sub power supply line SL1 on the power supply voltage VDD side decreases due to the wiring resistance and the potential of the sub power supply line SL2 on the ground voltage VSS side increases, the operation speed of the logic circuit decreases in the operable state.

  The second problem is the area occupied by the switches SS and SD. In the MOS semiconductor integrated circuit, the switches SS and SD are actually realized by MOS transistors. In order to prevent a decrease in the operating speed of the logic gate, it is necessary to make the resistance as small as possible when the switch MOS transistor is in the ON state. For this purpose, the channel width of the MOS transistor must be increased, which increases the layout area.

  An object of the present invention is to provide a semiconductor integrated circuit capable of reducing a voltage drop on a sub power supply wiring for reducing a subthreshold current, thereby preventing a decrease in operating speed of a logic circuit.

  Another object of the present invention is to provide a semiconductor integrated circuit capable of low power consumption during standby and high speed during operation.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  In other words, a plurality of switch MOS transistors for selectively connecting the main power supply wiring and the sub power supply wiring are distributed to one main power supply wiring. The layout of the main power supply wiring, the sub power supply wiring, and the switch can be as follows.

  First, a main power supply wiring is arranged along one side of a rectangular area including a MOS logic circuit whose subthreshold current is to be reduced, and a plurality of sub power supply wirings are arranged on the area in a direction perpendicular to the main power supply wiring. Deploy. A plurality of switch MOS transistors for selectively connecting the sub power supply lines to the main power supply lines are arranged in a distributed manner with respect to the main power supply lines.

  Secondly, the sub power supply wirings are arranged so as to intersect in the X direction and the Y direction on the region, and are joined at the intersections to form a so-called mesh shape. At this time, the main power supply wiring is arranged along one side of the region. Alternatively, they are arranged along two adjacent sides of the region.

  Third, a switch MOS transistor for connecting the main power supply wiring and the sub power supply wiring is arranged in a region immediately below the main power supply wiring.

  As described above, when the switch MOS transistors are distributedly arranged with respect to the main power supply wiring, the equivalent wiring resistance of the sub power supply wiring can be reduced as compared with the case where the switch MOS transistors are arranged at one place. This is because the distance from the MOS logic circuit targeted for reduction of the subthreshold current to the nearest switch MOS transistor is shortened. When MOS logic circuits targeted for reduction of the subthreshold current are dispersed in a rectangle, if the sub power supply wiring is laid in the short side direction of the rectangular area, the length of one sub power supply wiring is at most a rectangular area. The resistance component of the sub power supply wiring is further reduced. Further, if the sub power supply wiring is configured in a mesh shape so that power is supplied from two directions of the main power supply wiring along two adjacent sides of the rectangular area, the equivalent wiring resistance of the sub power supply wiring is further reduced.

  If the equivalent resistance of the sub power supply wiring is reduced, the voltage drop on the sub power supply wiring is reduced in the operable state of the MOS logic circuit. Therefore, even if the subthreshold current is reduced, a reduction in the operating speed of the MOS logic circuit can be suppressed. In addition, low power consumption of the semiconductor integrated circuit during standby can be promoted.

  In the above, the main power supply wiring is supplied with the first main power supply wiring to which the first power supply voltage having a relatively high level is supplied and the second main power supply to which the second power supply voltage having a relatively low level is supplied. And the sub power supply line coupled to the source of the p-channel MOS transistor that is controlled to be turned off in the MOS logic circuit in the operation stop state, is connected to the first main power supply line via the switch MOS transistor. Connected. Further, the sub power supply line coupled to the source of the n-channel MOS transistor that is controlled to be turned off inside the MOS logic circuit in the operation stop state is connected to the second main power supply line via the switch MOS transistor. The carrier conductivity of the p-channel MOS transistor is about 1/3 that of the n-channel MOS transistor. Therefore, in a CMOS circuit or the like, the channel width of the p-channel MOS transistor is three times that of the n-channel MOS transistor. As a result, the occurrence rate of the subthreshold current is higher in the p-channel MOS transistor than in the n-channel MOS transistor. Therefore, when measures for reducing the subthreshold current cannot be applied to both n-channel and p-channel MOS transistors, it is advantageous to take measures against the p-channel MOS transistors.

  In a memory such as a DRAM, generally, a voltage obtained by boosting a power supply voltage is often used as a word line selection level. The MOS transistors constituting the MOS logic circuit using the boosted voltage as the operation power supply have a higher operation power supply voltage than the MOS transistors of other circuit portions, but the threshold voltage is the same as the MOS transistors included in the other circuits. Often done. This is to simplify the manufacturing process. Then, it is equivalent that the threshold voltage of the MOS transistor using the boosted voltage as the operation power supply becomes relatively small with respect to the operation power supply. This means an increasing tendency of the subthreshold current. In consideration of this point, the semiconductor integrated circuit according to the present invention includes a plurality of memory mats arranged in an array including a plurality of memory cells having word lines coupled to selection terminals, and a memory mat arranged in an array. A plurality of MOS logics regularly arranged between the word drivers for selectively driving the word lines and the word drivers arranged between the memory mats arranged in an array to supply the word line drive voltage An X-direction sub-power supply wiring and a Y-direction sub-power-supply wiring connected to power supply terminals of a circuit and a plurality of MOS logic circuits and arranged in the X and Y directions and having a coupling point at an intersection position; All or some of the main power supply wires arranged in the laying direction of at least one sub power supply wire of the Y direction sub power supply wires and all or a part of the selected power source wires are selected from the X direction sub power supply wires and the Y direction sub power supply wires. A plurality of switch MOS transistors individually connecting the sub power supply wiring to the main power supply wiring, the switch MOS transistor being turned off in the standby state of the MOS logic circuit, and the switch MOS transistor being operable in the MOS logic circuit operable state The transistor is turned on. A boosted voltage is supplied to the main power supply wiring. The operation stop state is instructed in response to, for example, a chip non-selection state.

  When the boosted voltage is supplied to the main power supply wiring, the source is coupled to the sub power supply wiring, and the boosted voltage can be supplied to the well region of the p-channel MOS transistor in the MOS logic circuit. This tends to increase the threshold voltage of the p-channel MOS transistor, and also in this respect, the subthreshold current is reduced.

  The word driver receives a selection signal from a common main word line in a plurality of word driver units, and the MOS logic circuit sends a sub-power supply line to the word driver according to a decode signal for selecting one of the plurality of word drivers. Supply word line drive level. Since the main word line is arranged for each of the plurality of word drivers, the interval between the main word lines is relatively wide, and the sub power supply wiring is arranged therebetween. That is, the sub power supply wiring is formed in the same wiring layer as the main word line. As a result, the chip area does not increase even if the sub power supply wiring increases.

  The effects obtained by typical ones of the present invention will be briefly described as follows.

  In other words, a plurality of switch MOS transistors for selectively connecting the main power supply wiring and the sub power supply wiring are distributed to one main power supply wiring. As described above, when the switch MOS transistors are arranged in a distributed manner with respect to the main power supply wiring, the equivalent wiring resistance of the sub power supply wiring can be reduced as compared with the case where the switch MOS transistors are arranged at one place. Further, if the sub power supply wiring is configured in a mesh shape so that power is supplied from two directions of the main power supply wiring along two adjacent sides of the rectangular area, the equivalent wiring resistance of the sub power supply wiring is further reduced. If the equivalent resistance of the sub power supply wiring is reduced, the voltage drop on the sub power supply wiring is reduced in the operable state of the MOS logic circuit. Therefore, even if the subthreshold current is reduced, a reduction in the operating speed of the MOS logic circuit can be suppressed. In addition, low power consumption of the semiconductor integrated circuit during standby can be promoted.

  FIG. 1 shows an example of SCRC for reducing a subthreshold current in a semiconductor integrated circuit. The circuit shown in the figure is an operating voltage of a circuit from the point of withstand voltage of an element miniaturized for high integration and high-speed operation, such as a DRAM of 256 M to 1 Gbit or more. Is a part of a semiconductor integrated circuit whose voltage is lowered to about 1.5V to 2V. A rectangular area indicated by 1 in FIG. 1 is an area in which the MOS logic circuit 2 focused as a target for reducing the subthreshold current is arranged. In the rectangular area 1, other circuit elements are actually arranged, but they are not shown.

  Here, the MOS logic circuit 2 is not particularly limited, but is a CMOS inverter composed of a p-channel MOS transistor Mp1 and an n-channel MOS transistor Mn2. Hereinafter, the MOS logic circuit 2 is also referred to as a CMOS inverter 2. In the CMOS inverter 2, the input signal IN is fixed at a high level in the standby state or standby state of the semiconductor integrated circuit, thereby fixing the state of the circuit that receives the output of the CMOS inverter 2. The CMOS inverter 2 is arranged in a matrix in the rectangular area 1.

  X-direction main power supply wires 3 and 4 are arranged along the long side of the rectangular region 1. The X-direction main power supply wiring (first X-direction main power supply wiring) 3 is supplied with a relatively high level power supply voltage VDD such as 2V, and the X-direction main power supply wiring (second X-direction main power supply wiring). 4 is supplied with a relatively low level ground voltage VSS such as 0V. On the rectangular region 1, a plurality of sub power supply wires 5 and 6 are arranged in a direction intersecting with the main power supply wires 3 and 4. One sub-power supply line (first Y-direction sub-power supply line) 5 is coupled to the main power supply line 3 via the p-channel type switch MOS transistor 7 and the other sub-power supply line (second Y-direction sub-power supply line). ) 6 is directly coupled to the main power supply wiring 4. The switch MOS transistor 7 is turned on / off by a control signal φD.

  The CMOS inverter 2 obtains operating power from the sub power wirings 5 and 6. In order to distinguish the voltage supplied to the sub power supply wiring 5 from the power supply voltage VDD, it is referred to as a voltage VDT. In the operating state of the semiconductor integrated circuit, the switch MOS transistor 7 is turned on. Thereby, the voltage VDT of the sub power supply wiring 5 is made substantially equal to the power supply voltage VDD. As a result, the CMOS inverter 2 is operated using the power supply voltage VDD and the ground voltage VSS as operation power supplies.

  In the standby state of the semiconductor integrated circuit, the input IN of the CMOS inverter 2 is fixed to a high level substantially equal to the power supply wiring voltage VDD. At this time, the signal φD is also set to the high level, and the switch MOS transistor 7 is turned off. Then, the voltage VDT of the sub power supply wiring 5 is made lower than the power supply voltage VDD of the main power supply wiring 3. As a result, the source voltage of the p-channel MOS transistor Mp1 constituting the CMOS inverter 2 is set to a reverse bias voltage state that is lower than the gate voltage, and the generation of the subthreshold current is suppressed or the generation of the subthreshold current is reduced. it can. When the semiconductor integrated circuit is changed from the standby state to the operable state, the control signal φD is set to the low level in synchronization therewith.

  In the SCRC configuration, the switch MOS transistors 7 are dispersedly arranged with respect to the main power supply wires 3 and 4. As shown in FIG. 16, the equivalent wiring resistance of the sub power supply wirings 5 and 6 can be reduced as compared with the case where the switch MOS transistors are concentratedly arranged at one place. This is because the distance from the CMOS inverter 2 to the nearest switch MOS transistor 7 is shortened. As shown in FIG. 1, since the sub power supply wires 5 and 6 are laid in the short side direction of the rectangular region 1, the length of one sub power supply wire 5 and 6 is at most the length of the short side of the rectangular region 1. Thus, the resistance values of the individual sub power supply wires 5 and 6 are further reduced. Similarly, the parasitic capacitance components of the sub power supply wires 5 and 6 can be reduced.

  As described above, if the equivalent resistance of the sub power supply lines 5 and 6 is reduced, the voltage VDT undesirably drops from the power supply voltage VDD on the sub power supply line 5 in the operable state of the CMOS inverter 2. A situation in which the voltage of the wiring 6 undesirably rises from the ground voltage VSS can be reduced. Therefore, even if the subthreshold current is reduced, it is possible to suppress a decrease in the operating speed of the CMOS inverter 2 in the operating state of the semiconductor integrated circuit. Further, since the parasitic capacitance component (wiring capacitance component) of the sub power supply wirings 5 and 6 is reduced, when the switch MOS transistor 7 is turned on, the voltage VDT of the sub power supply wiring 5 is restored to the power supply voltage VDD. You can save time. Therefore, this contributes to shortening the transition time from the standby state to the operable state of the semiconductor integrated circuit. Since generation of the subthreshold current in the CMOS inverter 2 can be prevented or reduced, wasteful power consumption during standby of the semiconductor integrated circuit can be suppressed.

  In the configuration of FIG. 1, since the leakage current of the MOS transistor 7 is supplied from the main power supply wiring 3 to the sub power supply wiring 5 in the OFF state of the switch MOS transistor 7, the level of the sub power supply wiring 5 is not abnormally lowered. Absent. If the level of the sub power supply line becomes too low, it takes a long time to recover the voltage VDT of the sub power supply line 5 to the power supply voltage VDD. In order to relatively reduce the level drop of the sub power supply wiring 5 during standby of the semiconductor integrated circuit, the high resistance element 8 can be arranged in parallel with the switch MOS transistor 7 as illustrated in FIG.

  FIG. 3 shows an example in which an n-channel switch MOS transistor 9 is arranged between the sub power supply line 6 and the main power supply line 4 on the ground voltage VSS side. In this example, it is assumed that the input IN of the CMOS inverter 2 is fixed at a low level in the standby state of the semiconductor integrated circuit. As a result, the switch MOS transistor 9 is turned off in the standby state, and the voltage VST of the sub power supply line 6 is set higher than the ground voltage VSS. As a result, the source voltage of the n-channel MOS transistor Mn2 constituting the CMOS inverter 2 is set to a reverse bias voltage state in which the gate voltage is set higher than the gate voltage, and generation of the subthreshold current in the MOS transistor Mn2 is suppressed or the subthreshold current is reduced. Generation can be reduced. The effects obtained with respect to the layout of the main power supply wirings 3 and 4 and the sub power supply wirings 5 and 6 are the same as those in FIG.

  FIG. 4 shows an example in which the MOS logic circuit targeted for reduction of the subthreshold current in the standby state is a series circuit of two CMOS inverters 2a and 2b. The configuration of FIG. 4 is a circuit configuration combining FIG. 1 and FIG. That is, the sub power supply lines 5 a and 5 b are arranged orthogonal to the main power supply line 3, and the sub power supply lines 6 a and 6 b are arranged orthogonal to the main power supply line 4. One sub power supply line 5 a on the power supply voltage VDD side is connected to the main power supply line 3 via the switch MOS transistor 7, and the other sub power supply line 5 b is directly connected to the main power supply line 3. One sub power supply line 6 a on the ground voltage VSS side is directly connected to the main power supply line 4, and the other sub power supply line 6 b is connected to the main power supply line 4 via the switch MOS transistor 9. The CMOS inverter 2a at the previous stage is operated using the voltages VDT and VSS of the sub power supply lines 5a and 6a as the operation power supply. The subsequent stage CMOS inverter 2b is operated using the voltages VDD and VST of the sub power supply lines 5b and 6b as operation power supplies. Therefore, in the standby state of the semiconductor integrated circuit, generation of subthreshold currents of the p-channel MOS transistor Mp1 of the CMOS inverter 2a and the n-channel MOS transistor Mn2 of the CMOS inverter 2b is suppressed.

  FIG. 5 shows an example in which the sub power supply wirings on the ground voltage VSS side in FIG. 4 are integrated into one line 6a and 6b. That is, the sub power supply line 6b and the switch MOS transistor 9 in FIG. 4 are eliminated, and the n-channel MOS transistor Mn2 of the CMOS inverter 2b in the subsequent stage is coupled to the sub power supply line 6b. In this configuration, the subthreshold current is not reduced for the n-channel MOS transistor Mn2 of the post-stage CMOS inverter 2b. Here, the carrier conductivity of the p-channel MOS transistor is about 1/3 that of the n-channel MOS transistor. Therefore, in a CMOS circuit or the like, the channel width of the p-channel MOS transistor is three times that of the n-channel MOS transistor. As a result, the occurrence rate of the subthreshold current is higher in the p-channel MOS transistor than in the n-channel MOS transistor. Therefore, as shown in FIG. 5, if measures are taken to reduce the subthreshold current only for the p-channel type MOS transistor Mp1 of the front-stage CMOS inverter 2a, the purpose of low power consumption during standby can be achieved to some extent. it can. The configuration of FIG. 5 is inferior in power consumption during standby compared to the configuration of FIG. 4, but the circuit configuration or chip occupation area is reduced as compared to FIG.

  FIG. 6 shows an example in which the main power supply wiring is arranged along the short side of the rectangular area. In this case, the sub power supply wires 5 and 6 are arranged in the long side direction of the rectangular region 1. Compared to the configuration of FIG. 1, the sub power supply wires 5 and 6 are longer, but the main power supply wires 3 and 4 are shorter. Since the main power supply wirings 3 and 4 are shortened, the area occupied by the wirings 3 and 4 in the wiring area can be saved as compared with FIG. However, an undesired voltage drop in the sub power supply wires 5 and 6 in the operable state is larger in FIG. 4 than in FIG.

  FIG. 7 shows an example in which the sub power supply wiring is arranged in a mesh shape. In the CMOS inverter 2 shown in FIG. 7, as in FIG. 1, the input IN is fixed at a high level in the standby state of the semiconductor integrated circuit.

  X direction main power supply lines 3x and 4x and Y direction main power supply lines 3y and 4y are arranged along two mutually adjacent sides of the rectangular area 1. The main power supply lines 3x and 3y are mutually coupled and supplied with the power supply voltage VDD. The main power supply lines 4x and 4y are mutually coupled and supplied with the ground voltage VSS.

  In the rectangular area 1, a plurality of X-direction sub power supply wires 5x and 6x are alternately arranged in the X direction at regular intervals, and a plurality of Y-direction sub power supply wires 5y and 6y are alternately arranged in the Y direction at regular intervals. Has been. The X direction sub power supply wiring 5x and the Y direction sub power supply wiring 5y are coupled at the intersection position. Similarly, the X direction sub power supply wiring 6x and the Y direction sub power supply wiring 6y are coupled at the intersection position. The p-channel type MOS transistor Mp1 and the n-channel type MOS transistor Mn2 of the CMOS inverter 2 as the MOS logic circuit are directly coupled to the X-direction sub power supply lines 5x and 6x.

  The X direction sub power supply line 5x is coupled to the Y direction main power supply line 3y via the p channel type switch MOS transistor 7y arranged in the Y direction, and the Y direction sub power supply line 5y is the p channel type arranged in the X direction. The switch MOS transistor 7x is coupled to the X-direction main power supply wiring 3x. The main power supply lines 4x and 4y on the ground voltage VSS side are directly connected to the sub power supply lines 6y and 6x.

  The switch MOS transistors 7x and 7y are switch-controlled by a control signal φD, turned off in the standby state of the semiconductor integrated circuit, and turned on in the operable state of the semiconductor integrated circuit.

  In the above configuration, there are two layout forms of the sub power supply lines 5x, 5y, 6x, 6y. First, one wiring layer (for example, a third metal wiring layer) is used for the sub-power supply lines 5x and 5y on the power supply voltage side, and another wiring layer (for the sub-power supply lines 6x and 6y on the ground voltage side). For example, a second metal wiring layer) is used. Second, one wiring layer (for example, a third metal wiring layer) is used for the sub-power supply lines 5y and 6y in the Y direction (vertical direction), and the sub-power supply lines 5x and 6x in the X direction (lateral direction) are used. This is a method using another wiring layer (for example, a second metal wiring layer). In the latter case, through wires are provided at the intersections of the sub power supply wires 5x and 5y and the intersections of 6x and 6y, and the wires are connected to each other.

  In the above example, the sub power supply lines 5x and 5y coupled to each other at the crossing positions are supplied with power from two directions via the switch MOS transistors 7x and 7y, so that the sub power supply lines 5x are compared with the configuration of FIG. , 5y equivalent resistance components and capacitance components can be reduced. Therefore, the high-speed operation of the CMOS inverter 2 in the operable state and the time reduction from the standby state to the operable state can be further improved. Since other operations and effects are the same as those in FIG. 1, detailed description thereof is omitted.

  FIG. 8 shows a simplified configuration of FIG. 7 due to layout constraints. As shown in FIG. 7, it is ideal to provide the switch MOS transistors 7x and 7y for each of the sub power supply lines 5x and 5y. However, when this is not possible due to layout restrictions, a part of the configuration of FIG. Can be omitted. For example, as shown in FIG. 8, the main power supply wirings 3x and 4x are provided only in one direction, and the switch MOS transistors 7x are provided every other sub power supply wiring 5y. At this time, the sub power supply wiring is configured in a mesh shape with 5x, 6x, 5y, and 6y, as in FIG. Since the sub power supply wirings 5x, 6x, 5y, 6y are configured in a mesh shape, a large number of current supply paths to the CMOS inverter 2 are secured even if the number of the switch MOS transistors 7x is small. Compared to the configuration, the equivalent resistance component and capacitance component of the sub power supply wiring do not increase as much as the left.

  FIG. 9 shows an example of the layout of the switch MOS transistor 7. The switch MOS transistor 7 is formed in a region immediately below the main power supply wiring 3. In the switch MOS transistor 7, S is a source, D is a drain, and G is a gate.

  Thus, by forming the switch MOS transistor 7 immediately below the main power supply wiring 3, the chip area can be saved. In other words, the switch MOS transistor 7 having a relatively large size can be arranged without increasing the chip area. The arrangement of the switch MOS transistor 7x with respect to the main power supply wiring 3x and the arrangement of the switch MOS transistor 7y with respect to the main power supply wiring 3y can be similarly configured.

  FIG. 10 is an overall block diagram of a DRAM to which the present invention is applied. The DRAM shown in the figure is formed on one semiconductor substrate 10 such as single crystal silicon. The arrangement of the circuit blocks shown in FIG. 10 is in accordance with a DRAM layout example. A peripheral circuit 14 is disposed at the center of the semiconductor substrate 10, and a plurality of memory array units 11, column decoder units 13, row decoder units 12, peripheral circuit units 15, and peripheral circuit units 16 are disposed above and below the peripheral circuit 14. .

  A large number of dynamic memory cells are arranged in a matrix in the memory array section 11. The row decoder unit decodes the row address signal and generates a selection signal for selecting a word line coupled to the selection terminal of the memory cell. The column decoder unit 13 decodes the column address signal and selects a bit line to which the data input / output terminals of the memory cells are coupled. The peripheral circuit sections 14, 15, and 16 include an address input buffer, a data input / output buffer, a timing controller, and the like, and perform overall control of the DRAM.

  In this DRAM, a circuit to which SCRC for reducing the subthreshold current is applied is arranged in the memory array section 11. In this example, the high potential side power supply of the circuit to which SCRC is applied is the boosted voltage VPP for driving the word line. The boosted voltage VPP is formed by boosting an external power supply corresponding to the power supply voltage VDD by the booster circuit 20. The booster circuit 20 is disposed in the peripheral circuit section 14. The main power supply line to which the boosted voltage VPP is supplied and the switch MOS transistor for SCRC are formed in the hatched regions 21 and 22 shown in the row decoder circuit portion 12 and the peripheral circuit portion 14 of FIG. Yes. In the upper layer of the memory array unit 11, sub power supply wiring is wired in a mesh shape. These configurations will be described in detail later.

  The arrangement of the main power supply wiring and the switch MOS transistor is not limited to the above. If the main power supply wiring and the switch MOS transistor are arranged in the peripheral circuits 15 and 16, the column decoder section 13, and the periphery of the semiconductor substrate 10, the mesh-like sub power supply wiring can be obtained. Power can be supplied from four directions, and the equivalent wiring resistance and equivalent capacitance component of the sub power supply wiring can be further reduced.

  FIG. 11 shows an example of the memory array unit 11. In the memory array unit 11, a memory mat 30, a sense amplifier unit (SA) 32, a sub word driver unit (SWD) 31, and a MOS logic circuit 33 are regularly arranged in an array. The MOS logic circuit 33 supplies the sub-word driver unit 31 with the boosted voltage VPP as a drive voltage.

  A large number of dynamic memory cells are arranged in a matrix on the memory mat 30. The sense amplifier unit 32 includes a number of sense amplifiers coupled in a folded bit line format to a pair of complementary bit lines to which data input / output terminals of memory cells are coupled. The sub-word driver unit 31 includes a number of sub-word drivers that selectively drive a sub-word line to which a memory cell selection terminal is coupled to a selection level.

  Although the configurations of the sub word driver unit 31 and the MOS logic circuit 33 will be described in detail later, the selection level output from the sub word driver unit 31 to the sub word line is supplied via the MOS logic circuit 33, and the selection level is a boosted voltage. VPP. The threshold voltage of the MOS transistors constituting the MOS logic circuit 33 is the same as that of the other MOS transistors in the memory array section 11. Therefore, the level of the high-potential side operation power supply (boosted voltage VPP) of the MOS logic circuit 33 is raised with respect to the other MOS transistors of the memory array section 11. In other words, the threshold voltage with respect to the power supply voltage of the MOS transistors constituting the MOS logic circuit 33 is made relatively smaller than other MOS transistors in the memory array unit 11. The number of MOS logic circuits 33 occupies most of the circuits including MOS transistors coupled to the power supply in the memory array unit 11.

  Considering the above situation, in this example, the CMOS inverter included in the MOS logic circuit 33 is the target of SCRC. In the standby state of the DRAM of FIG. 11, for example, the chip non-selected state, the input of the CMOS inverter included in the MOS logic circuit 33 is fixed at a high level (the p-channel MOS transistor of the CMOS inverter is turned off). . That is, the SCRC configuration for the CMOS inverter included in the MOS logic circuit 33 is applied to the high potential side power supply. The configuration of FIG. 7 is applied to supply operation power to the CMOS inverter included in the MOS logic circuit 33 of FIG. FIG. 11 representatively shows only the supply path of the high-potential side power supply to the CMOS inverter included in the MOS logic circuit 33.

  In FIG. 11, the memory array unit 11 is a rectangular area, 43x is an X-direction main power supply wiring arranged in the X direction of the memory array unit 11, and 43y is a Y-direction main power supply wiring arranged in the Y direction. The boosted voltage VPP output from the booster circuit 20 is supplied. 45y is a Y-direction sub-power supply line arranged in the Y direction on the memory array unit 11, and 45x is an X-direction sub-power supply line arranged in the X direction on the memory array unit 11. The X direction sub power supply wiring 45x and the Y direction sub power supply wiring 45y are coupled to each other at the crossing position. The X direction sub power supply line 45x is coupled to the main power supply line 43y via the switch MOS transistor 47y, and the Y direction sub power supply line 45y is coupled to the main power supply line 43x via the switch MOS transistor 47x. The switch MOS transistors 47x and 47y are turned off in the l standby state of the DRAM. VPT means the voltage of the sub power supply wirings 45x and 45y. Therefore, voltage VPT is set lower than boosted voltage VPP in the standby state of the DRAM. In the operable state of the DRAM, the voltage VPT is set to the boosted voltage VPP. The basic operation and effect of the SCRC configuration using this mesh-like sub power supply wiring network is the same as that described with reference to FIG.

  FIG. 12 shows a circuit format of the main / sub word line structure of the DRAM. MWB is a main word line, and SW is a sub word line. The main word line MWB is shared by a plurality of memory mats 30 arranged in the horizontal direction. A large number of sub word lines SW are arranged for each memory mat 30. A signal used for selecting the sub word line SW is a selection signal transmitted to the main word line MWB and predecode signals FXB0 to FXB7. In one memory mat 30, predecode signals are divided into a set of FXB0, FXB2, FXB4, and FXB6 and a set of FXB1, FXB3, FXB5, and FXB7. Individually supplied to the sub word driver 51. The main word line MWB is commonly connected to the sub word driver 51 having four units as a unit in the memory mat 30 here. Main word line MWB driven to the selected level selects one set of eight sub word lines SW on the left and right in each memory mat, and predecode signals FXB0 to FXB7 are set of eight sub word lines SW. It can be regarded as a signal for selecting one sub word line SW from the inside. The predecode signals FXB0 to FXB7 are output from a predecoder (not shown) included in the peripheral circuit 14. The predecoder decodes part of the address signal to generate predecode signals FXB0 to FXB7. Details of the main / sub word line structure, that is, the hierarchical word line system, are described in, for example, ESSCIRC Dig. Tech. Papers, Sep. 1992, pp. 131-134.

  FIG. 13 shows a detailed example of the row decoder unit 12. The row decoder unit 12 is commonly used for the left and right memory array units 11. The mat selection circuit 50 selects a pair of left and right memory mats 30 using a part of the address signal. The row decoder unit 51 decodes a part of the address signal to generate a selection signal for the main word line MWB. The main word driver section 52 has a main word driver 520 for each main word line MWB, and a main word line selection signal is supplied to each main word driver 520 in a one-to-one correspondence.

  11 uses a third-layer metal wiring layer (wiring layer in the same layer as the output line of the column decoder section 13), and the X-direction sub-power wiring 45x is a second-layer metal wiring. A wiring layer (a wiring layer in the same layer as the main word line MWB) is used. Generally, the wiring pitch of the output lines and main word lines of the column decoder section 13 has a margin compared to the minimum processing dimension of the wiring. This is because according to FIG. 12, the main word line MWB is arranged for every eight sub-word lines SW, and the sub-word lines SW are composed of, for example, a polysilicon wiring layer. This is because the output line of the column decoder is arranged for each single or a plurality of complementary bit lines. Therefore, the sub power supply wirings 45x and 45y can be wired without adding a new wiring layer or providing a special area dedicated to the sub power supply wiring. The sub power supply wires 45x and 45y are connected by a through hole. Therefore, the sub power supply wirings 45x and 45y can be wired in the memory array section 11 in a mesh shape without increasing the number of manufacturing steps and the chip size. As a result, the voltage drop of the sub power supply wiring can be reduced and the circuit operation speed can be increased as described above. Although not shown in FIG. 11, the same applies to the sub power supply wiring on the ground voltage VSS side.

  FIG. 14 shows a circuit configuration around the sub word driver unit 31 and the MOS logic circuit 33. The MOS logic circuit 33 includes a CMOS inverter 50 that supplies operation power to the sub word driver 51. The CMOS inverter 50 inverts the subdecode signals FX0B, FX2B,... To generate signals FX0, FX2,. The high level of the signals FX0B, FX2B,..., FX0, FX2,... Is the boosted voltage VPP, and the low level is the ground voltage VSS. The CMOS inverter 50 includes a p-channel MOS transistor Mp3 and an n-channel MOS transistor Mn4.

  The sub word driver 51 is configured as a NOR gate by a p-channel MOS transistor Mp5 and n-channel MOS transistors Mn6 and Mn7. The corresponding predecode signals FX0B, FX2B,... Are supplied to the gate of the MOS transistor Mn7, and the corresponding main word line MWB is coupled to the gates of the MOS transistors Mp5, Mn6. The sub word driver 51 is configured so that the sub word driver 51 only has a sub word when the corresponding main word line MWB is at a low level and the corresponding signals FX0B, FX2B,... Are at a low level (FX0, FX2,... Are at a high level). The line SW is driven to a voltage VPT equal to the boost voltage VPP. The voltage VPT is supplied to the sub word driver 51 as high level outputs FX0, FX2,.

  In the standby state of the DRAM, the signals FX0B, FX2B,... Are set to a high level (= VPP), and FX0, FX2,. Therefore, a subthreshold current tends to flow through the p-channel MOS transistor Mp3 constituting the CMOS inverter 50. At this time, the source of the MOS transistor Mp3 is connected to the sub power supply line 45x, and the sub power supply line 45x is connected to the main power supply line 43y via the switch MOS transistor 47y. Even in the standby state, the boosted voltage VPP is supplied to the main power supply wiring 43y. During standby, the switch MOS transistors 47y and 47x are controlled to be turned off. Therefore, voltage VPT falls below boosted voltage VPP during standby, so that the gate potential of MOS transistor Mp3 becomes higher than the source potential, and the subthreshold current is suppressed. In FIG. 14, the reference numerals 46x and 46y denote sub power supply wirings on the ground voltage VSS side which are not shown in FIG.

  In the configuration of FIG. 14, not the voltage VPT but the boosted voltage VPP is supplied to the back gate of the p-channel MOS transistor Mp3, that is, the n-type well region. This is because when the potential of the voltage VPT is lowered in the standby state, the MOS transistor Mp3 is subjected to a back gate bias, the threshold voltage of the MOS transistor Mp3 is lowered (the threshold voltage is increased in absolute value), and the subthreshold current is increased. This is because it acts in the direction of decreasing the. The power supply wirings 48x and 48y supplying the boosted voltage VPP as a back gate bias voltage are dedicated thereto. Therefore, since it is not necessary to supply a large current, there is no problem even if the wiring resistance is somewhat large. Therefore, the power supply wirings 48x and 48y can be made narrower than the sub power supply wirings 45x and 45y supplying the voltage VPT, thereby saving the chip occupation area.

  In FIG. 14, reference numeral 52 denotes a dynamic memory cell, the selection terminal of which is coupled to the sub word line SW, and the data input / output terminal of which is coupled to the complementary bit lines BL and BLB.

  What is indicated by 53 is a sense amplifier included in the sense amplifier section 32. The sense amplifier 53 is provided for each of the complementary bit lines BL and BLB, and amplifies a minute potential difference between the complementary bit lines BL and BLB. The complementary bit lines BL and BLB are connected to the common data lines IO and IOB via the column selection gate 54. The column selection gate 54 is switch-controlled by a column selection signal YS output from the column decoder unit 13.

  In FIG. 13, a mat selection circuit 50, a row decoder unit 51, and a main word driver unit 52 are arranged on the left and right with the region 22 where the SCRC switch MOS transistor 47y is arranged as a center. The sub power supply wiring 45x is formed of the same wiring layer as the main word line MWB, and is wired in a surplus area between the main word lines MWB. The switch MOS transistor 47y is shared by the left and right memory array units 11. Since the left and right memory array units 11 are not selected at the same time, the channel width of the switch MOS transistor 47y may be set so that power can be supplied to one memory array unit 11. Therefore, even if the switch MOS transistor 47y is shared by the left and right memory array units 11, it is not necessary to double the channel width of the MOS transistor 47y.

  FIG. 15 shows a partial cross-sectional view of the memory mat 30. In FIG. 15, 60 is a p-type substrate, 61 is an element isolation oxide film, 62 is an n-type diffusion layer, and 63 is a first metal wiring layer used as bit lines BL and BLB. Note that the sub word line SW passes before or behind the page, and does not appear in this figure.

  Here, a multilayer capacitor type is used as the memory cell. A capacitor is formed by the storage electrode 64, the counter electrode 65, and an insulating film (not shown) therebetween. Reference numeral 66 denotes an interlayer insulating film. Reference numeral 67 denotes a second-layer metal wiring layer, which is used as a wiring for the sub power supply wiring 45x. Although not shown, the main word line MWB is also formed of the second metal wiring layer, and is wired in parallel with the sub power supply wiring 45x. Reference numeral 70 denotes a third metal wiring layer, which is used as a wiring for the column selection signal YS output from the sub power supply wiring 45y and the column decoder. Reference numeral 69 denotes a through hole formed in the interlayer insulating film 68, which connects the sub power supply wirings. The same applies to the sub power supply wirings 46x and 46y on the ground voltage VSS side. Reference numeral 71 denotes a surface protective film.

  The signal wiring for the column selection signal YS is often provided at a ratio of one to two pairs or four pairs of complementary bit lines. That is, the column selection signal wiring is formed at a rate of one in four or eight of the first metal wiring layers. Accordingly, even if the third metal wiring layer has a larger minimum processing dimension than the first metal wiring layer, it is normal that the wiring pitch still has a margin, and the column selection signal It is possible to pass other wiring such as a sub power supply wiring between the wirings of the line YS.

  As described above, the sub power supply wirings 45x, 45y, 46x, and 46y are formed of the same wiring layer as the main word MWB line and the column selection signal YS, so that a mesh shape can be obtained without adding a new wiring layer. Wiring is possible.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. For example, the MOS logic circuit targeted by SCRC is not limited to a CMOS inverter and can be changed to an appropriate circuit. The MOS logic circuit is not limited to a CMOS circuit, and may be a push-pull circuit using an n-channel MOS transistor. When the present invention is applied to a DRAM, the target of SCRC is not limited to the CMOS inverter 50, but can also be applied to a power supply circuit portion of a main word driver, a power supply circuit portion of a column decoder, and the like.

  The present invention can be applied to other memories such as SRAM (Static Random Access Memory) and ROM (Read Only Memory), and various semiconductor integrated circuits such as a logic LSI. The present invention can be widely applied to semiconductor integrated circuits intended to reduce the subthreshold current and increase the operation speed.

It is a circuit diagram which shows an example of SCRC for the subthreshold current reduction in a semiconductor integrated circuit. FIG. 2 is a circuit diagram in which a configuration for relatively reducing the level drop of the sub power supply wiring in a standby state is added to the configuration of FIG. 1. FIG. 5 is a circuit diagram showing an example of an SCRC configured by arranging an n-channel type switch MOS transistor between a sub power supply wiring on the ground voltage side and a main power supply wiring. It is a circuit diagram which shows an example of SCRC when the MOS logic circuit made into the reduction object of the subthreshold current in a standby state is used as the series circuit of two CMOS inverters. FIG. 5 is an example circuit diagram of SCRC in which the number of sub power supply wirings on the ground voltage side in FIG. 4 is reduced. It is an example circuit diagram of SCRC which has arrange | positioned the main power supply wiring along the short side of a rectangular area. It is an example circuit diagram of SCRC which has arranged sub power supply wiring in the shape of a mesh. FIG. 8 is a circuit diagram showing a configuration in which the configuration of FIG. 7 is simplified due to layout restrictions. It is a top view which shows an example of the layout of a switch MOS transistor. 1 is an overall block diagram of a DRAM to which an SCRC configuration according to the present invention is applied. FIG. 11 is a block diagram illustrating an example of a memory array unit included in the DRAM of FIG. 10. FIG. 11 is a logic circuit diagram showing an example of a main / sub word line structure in the DRAM of FIG. 10. FIG. 11 is a block diagram illustrating an example of a row decoder included in the DRAM of FIG. 10. FIG. 11 is an example circuit diagram in the vicinity of a sub word driver unit and a MOS logic circuit included in the DRAM of FIG. 10. FIG. 11 is a partial cross-sectional view of a memory mat included in the DRAM of FIG. 10. It is an example circuit diagram of SCRC which this inventor examined previously.

Explanation of symbols

1 Rectangular area 2, 2a, 2b CMOS inverter (MOS logic circuit)
3, 4 Main power supply wiring 5,6 Sub power supply wiring 3x, 4x X direction main power supply wiring 3y, 4y Y direction main power supply wiring 5x, 6x X direction sub power supply wiring 5y, 6y Y direction sub power supply wiring 7 p-channel type switch MOS transistor 7x X-direction switch MOS transistor 7y Y-direction switch MOS transistor Mp1 p-channel MOS transistor Mn2 n-channel MOS transistor VDD power supply voltage VSS ground voltage VDT voltage of sub power supply wiring 5 8 resistance element 9 n-channel switch MOS transistor DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 11 Memory part 12 Row decoder part 14 Peripheral circuit part 30 Memory mat 31 Subword driver part 32 Sense amplifier part 33 MOS logic circuit 43x X direction main power supply wiring 43y Y direction main power supply wiring 45x X direction sub power supply Line 45y Y direction sub power supply wiring 47x X direction switch MOS transistor 47y Y direction switch MOS transistor VPP Boost voltage VPT Voltage on sub power supply wiring 45x, 45y SW Sub word line MWB Main word line FXB0 to FXB7 Predecode signal FX0 to FX7 Predecode Inverted signal of signals FXB0 to FXB7 50 CMOS inverter 51 Sub word driver 63 First layer metal wiring layer 67 Second layer metal wiring layer 70 Third layer metal wiring layer

Claims (3)

A plurality of load circuits each formed of a logic circuit formed in a rectangular region on a semiconductor substrate;
A main power supply line disposed along one side of the periphery of the rectangular area;
A plurality of sub power supply wirings arranged in a direction orthogonal to the main power supply wiring in the rectangular region and respectively connected to power supply terminals of the load circuit;
Arranged along the direction in which the main power supply wiring extends, the same control signal corresponding to the operating state of the plurality of load circuits is input, and the main power supply wiring and the plurality of sub power supply wirings are respectively connected. A plurality of switch transistors,
The switch transistor has a leakage current smaller than a leakage current value that can flow between the source and drain of the transistor when the transistor included in the load circuit is not operating when the switch transistor is non-conductive. to flow in between,
The plurality of switch transistors are disposed in a region of the main power supply wiring.
A semiconductor integrated circuit. The plurality of switch transistors include a first terminal connected to the main power supply wiring, a second terminal connected to the sub power supply wiring, and a first terminal connected to the control signal according to a voltage value of the control signal. A third terminal for passing a current between the first terminal and the second terminal,
The long side of each layout pattern constituting the transistors connected to the first, second, and third terminals is configured along the direction in which the main power supply wiring extends. Item 14. A semiconductor integrated circuit according to Item 1 . The plurality of switch transistors include a first terminal connected to the main power supply wiring, a second terminal connected to the sub power supply wiring, and a first terminal connected to the control signal according to a voltage value of the control signal. A third terminal for passing a current between the second terminal and the second terminal,
The direction of the current flowing between the first terminal and the second terminal due to the voltage of the electrode constituting the transistor connected to the third terminal is a direction orthogonal to the main power supply wiring. The semiconductor integrated circuit according to claim 1 .

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