JPH07212218A - Logic circuit - Google Patents

Abstract

PURPOSE:To realize acceleration and area reduction at the same time. CONSTITUTION:Pseudo power supply lines VA1-VA3 of middle logic circuits M1-M3 are mutually connected through a common pseudo circuits circuits M1-M3 are mutually connected through a common pseudo power supply line VB. The gates of MOSFET QA1-QA3 for power control of the middle logic circuits M1-M3 are mutually connected through a common control line CSB. The gates of MOSFET QB1-QB3 for power control of the middle logic circuits M1-M3 are mutually connected through a common control line CS.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit capable of operating at a low voltage, and in particular, a high speed operation is realized by a small logic circuit composed of a field effect transistor having a low threshold when operating.
The present invention relates to an improvement of a logic circuit that realizes low leakage characteristics by turning off a high-threshold power control field effect transistor when it is not operating.

[0002]

2. Description of the Related Art In recent years, low voltage operation of integrated circuits has been promoted in order to meet the demand for portable electronic devices.
As an example of this kind of circuit, I E E "" 1V Hig
h-Speed Digital Circuit Technology With 0.5μm Mu
lti-Threshold CMOS “Proceedings of IEEE A
SIC CONFERENCE PP.186-189, SEPT.199
MT-CMOS (Multi-Threshold
A CMOS circuit is shown in FIG. In the figure, G is a logic gate, which is a low threshold P-channel MOSFET
Q3, Q4 and N-channel MOSFET Q5, Q6
It is composed by. A high potential pseudo power supply line VA1 is connected to one of the power supply terminals of the logic gate G, and a low potential pseudo power supply line VB1 is connected to the other. A high threshold P-channel MOSFET (power control MOS) is provided between the pseudo power supply line VA1 and the real power supply line (high potential) VDD.
FET) QA1 is connected, and a high threshold N-channel MOSFET (power control MOSFET) is connected between the pseudo power supply line VB1 and the real power supply line GND (low potential: ground potential).
QB1 is connected. In the figure, CSB
1 and CS1 are control lines, which are connected to the gates of QA1 and QB1. In this MT-CMOS circuit, CSB1 is set to low potential and CS1 is set to high potential during normal operation. This causes QA1 and QB2 to conduct,
VA1 and VB1 are connected to VDD and GND. In this case, the logic gate G is a low threshold MOSFE.
Since it is composed of TQ3 to Q6, it is possible to operate at high speed even with a very low power supply voltage of 1V.
Here, when a low threshold MOSFET is used, there is a problem that the leak current during non-operation becomes extremely large. Therefore, in this MT-CMOS circuit, the above-mentioned problems are avoided by the following method. That is,
When not operating, CSB1 is set to a high potential, CS1 is set to a low potential, and QA1 and QB1 are cut off. QA1 and Q
Since the threshold voltage of B1 is large, the MO of the logic gate G is
It is possible to suppress an increase in leak current generated in the SFETs Q3 to Q6.

By the way, in this MT-CMOS circuit,
Pseudo power supply lines VA1, VB1, Pseudo power supply lines VA1, VB1
For power control between the power supply line and the actual power line VDD, GND
SFET QA1 and QB1 and their control lines CSB
1 and CS1 are required and cannot be handled as they are by general CAD. Therefore, an MT-CMOS compatible standard cell as shown in FIG. 4 has been proposed. This drawing shows an example in which n + 1 standard cells are arranged in the X direction (horizontal direction in the drawing) to form a middle logic circuit, and the middle logic circuits are arranged in three stages in the Y direction (longitudinal direction in the drawing). . In the figure, SL1 to SLn + 1 are standard cells constituting the uppermost middle logic circuit M1.
This standard cell has power supply lines VDD and GND inside the cell.
In addition to the pseudo power supply lines VA1 and VB1 and the control lines CSB1 and C
It has S1 and can be automatically connected by simply arranging the cells. It should be noted that the power supply cells that supply a voltage to each cell include a high-threshold power control MOSFET QA1 controlled by control lines CSB1 and CS1.
QB1 is arranged. By using this standard cell, the MT-CMOS circuit can be automatically configured by laying out the layout similar to that of a normal CMOS logic cell.

The standard cells SL1 to SLn are logic gates (small logic circuits) G1 to G each having a logic function.
n is built in. The logic gates G1 to Gn are composed of low threshold MOSFETs. Logic gates G1 to G
A high potential pseudo power source line VA1 is connected to one of the n power source terminals, and a low potential pseudo power source line VB1 is connected to the other. The pseudo power supply lines VA1 and VB1 are the real power supply lines VD.
Current is supplied from D and GND via QA1 and QB1. The power line is capable of always supplying a sufficient amount of current.

[0005]

Generally, when an LSI is designed by a standard cell automatic layout method using CAD, it is not possible to specify in detail what cells are arranged adjacent to each other. In many cases, cells that perform switching operation at the same time are arranged close to each other. In particular, in a logic circuit in which the middle logic circuits are arranged in a plurality of stages, when the logic gates that simultaneously switch to a particular middle logic circuit are arranged in a concentrated manner, there is a great problem. For example, consider a case where all the logic gates G1 to Gn in the standard cell arranged in the middle logic circuit M1 at the top of FIG. In FIG. 4, during normal operation, the control lines CSB1 to CSB3 are set to a low potential and the control line CS1
~ CS3 is set to high potential, so power control M
The OSFETs QA1 to QA3 and QB1 to QB3 are all conductive. Here, if all the logic gates G1 to Gn are switched at the same time, a large current flows from the real power supply line VDD to the pseudo power supply line VA1, but at that time, since only QA1 serves as a path for the current, the resistance is increased. big,
The potential of the pseudo power supply line VA1 is lower than that of the real power supply line VDD. In addition, a large current flows from the pseudo power supply line VB1 to the real power supply line GND, and at that time, the current path is Q.
Since it is only B1, the resistance is large and the pseudo power supply line VB1
Potential rises as compared with the actual power supply line GND. As a result,
The potential difference (VA1-VB1) applied between the power supply terminals of the logic gates G1 to Gn becomes considerably smaller than the power supply voltage (VDD-GND), which causes a problem that sufficient speed performance cannot be obtained. In addition, the control line CSB
Regarding 1 to CSB3 and CS1 to CS3, assuming that the number of arranged middle logic circuits is m, control lines must be connected to 2m control signal terminals (not shown),
There is a problem that the number of externally connected control signal lines increases in proportion to the number of stages, which hinders the reduction of the area.

The present invention has been made in order to solve such a problem, and an object thereof is to eliminate speed deterioration of a logic circuit in which a middle logic circuit is arranged over a plurality of stages and speed up without trouble. It is an object of the present invention to provide a logic circuit capable of realizing the above-mentioned, and reducing the number of control signal lines connected from the outside to realize a small area.

[0007]

In order to achieve such an object, the present invention relates to first to nth small logic circuits composed of low threshold field effect transistors, and the first to nth.
A first pseudo power supply line connected to one of the power supply terminals of the small logic circuit, and a second pseudo power supply line connected to the other of the power supply terminals of the first to nth small logic circuits; Between the high threshold first power control field effect transistor connected between the pseudo power supply line and the first real power supply line, and between the second pseudo power supply line and the second real power supply line In a logic circuit having m stages of medium logic circuits each including a connected high threshold second power control field effect transistor, the first pseudo power supply lines of each medium logic circuit are mutually connected. First power control of each middle logic circuit is achieved by connecting via a first common pseudo power supply line, and connecting second pseudo power supply lines of each middle logic circuit to each other via a second common pseudo power supply line. The gates of the field effect transistors are connected to each other via the first common control line, and the second power control circuit of each middle logic circuit is connected. Gate effect transistor to each other which are connected via a second common control line.

[0008]

Therefore, according to the present invention, for example, when all the small logic circuits arranged in the upper middle logic circuit are simultaneously switched, only the first power controlling field effect transistor of the upper middle logic circuit is switched. Not only from the first power control field effect transistor of the other middle logic circuit,
Via the common pseudo power supply line of the first middle logic circuit
Current flows into the dummy power supply line of the second power control field effect transistor of the middle logic circuit in the uppermost stage and the second power control field effect transistor of the other middle logic circuit. A current flows out from the second pseudo power supply line of the middle logic circuit in the uppermost stage through the common pseudo power supply line.
Further, if the first and second common control lines are connected to the first and second control signal terminals and the control signal is given to the first and second control signal terminals, all middle logic circuits The control signal reaches the gates of the first and second power control field effect transistors.

[0009]

【Example】

Example 1 The present invention will be described in detail below based on examples. FIG. 1 is a diagram showing an embodiment of the present invention. In this figure, n + 1 standard cells are arranged in the X direction (horizontal direction in the drawing) to form a middle logic circuit.
An example in which three stages are arranged in the direction (vertical direction in the drawing) is shown. In the figure, SL1 to SLn + 1 are standard cells constituting the uppermost middle logic circuit M1. This standard cell has pseudo power supply lines VA1 and VB1 and control lines CSB1 and CS1 in addition to the power supply lines VDD and GND in the cell, and can be automatically connected by simply arranging the cells. There is. In addition, high threshold power control MOSFETs QA1 and QB1 controlled by control lines CSB1 and CS1 are arranged in the power supply cells that supply a voltage to each cell.

The standard cells SL1 to SLn are logic gates (small logic circuits) G1 to G having logic functions, respectively.
n is built in. The logic gates G1 to Gn are composed of low threshold MOSFETs. Logic gates G1 to G
A high potential pseudo power source line VA1 is connected to one of the n power source terminals, and a low potential pseudo power source line VB1 is connected to the other. The pseudo power supply lines VA1 and VB1 are the real power supply lines VD.
Current is supplied from D and GND via QA1 and QB1. The power line is capable of always supplying a sufficient amount of current.

Here, the circuit of this embodiment differs from the conventional circuit shown in FIG. The pseudo power supply lines VA1 to VA3 of the middle logic circuits M1 to M3 are connected to each other via a common pseudo power supply line VA. The pseudo power supply lines VB1 to VB3 of the middle logic circuits M1 to M3 are connected to each other via a common pseudo power supply line VB. Power control MOSFET Q for middle logic circuits M1 to M3
The gates of A1 to QA3 are connected to each other via a common control line CSB. Power control MOSFET Q for middle logic circuits M1 to M3
The gates of B1 to QB3 are connected to each other through a common control line CS.

In this circuit, consider a case where all the logic gates G1 to Gn in the standard cell arranged in the middle logic circuit M1 are simultaneously switched. In FIG. 1, during normal operation, the control lines CSB1 to CSB3 are set to a low potential and the control lines CS1 to CS3 are set to a high potential, so that the power control MOSFETs QA1 to QA1.
3 and QB1 to QB3 are all conductive. here,
When all the logic gates G1 to Gn are switched at the same time, a large current flows from the real power supply line VDD to the pseudo power supply line VA1.

At this time, the power control MO of the middle logic circuit M1
Power control MOSFETs QA2 and QA3 for other middle logic circuits M2 and M3 as well as SFET QA1
Also, a current flows into the pseudo power supply line VA1 of the middle logic circuit M1 via the common pseudo power supply line VA. For this reason, that is, since QA1 to QA3 are connected in parallel, the actual power line VD
The conduction resistance between D and the pseudo power supply line VA1 becomes very small, and the decrease in the potential of the pseudo power supply line VA1 is suppressed. Also, the power control MOSFET QB1 of the middle logic circuit M1.
Not only the power control MOSFETs QB2 and QB3 of the other middle logic circuits M2 and M3 but also the pseudo power supply line VB1 of the middle logic circuit M1 via the common pseudo power supply line VB.
Current flows out from. Therefore, that is, QB1 to Q
Since B3 is connected in parallel, the conduction resistance between the real power supply line GND and the pseudo power supply line VB1 becomes extremely small, and the rise in the potential of the pseudo power supply line VB1 is suppressed. As a result, the potential difference (V
A1-VB1) becomes approximately equal to the power supply voltage (VDD-GND), and sufficient speed performance can be obtained.

Next, the common control lines CSB and CS will be described. In this embodiment, the power control MOSFETs QA1 to QA of the middle logic circuits M1 to M3 are connected by the common control line CSB.
The gates of A3 are connected to each other, and the power control MOSFET / QB of the middle logic circuits M1 to M3 are connected by the common control line CS.
Gates 1 to QB3 are connected to each other. As a result, the common control lines CSB and CS are connected to the control signal terminals N1 and N2 (not shown), and the control signal terminal N1 is connected.
And N2, the power control MOSFETs QA1 to QA of the middle logic circuits M1 to M3 are provided.
3 and the control signals reach the gates of QB1 to QB3, and the number of external control signal lines connected is changed to CS, CSB.
There may be one for each.

[Embodiment 2] FIG. 2 shows another embodiment of the present invention. In the present embodiment, the common pseudo power supply line V is provided on one side (right side in the drawing) sandwiching the middle logic circuits M1 to M3 (middle logic circuit group).
A, VB and common control lines CSB, CS are provided, and common pseudo power supply lines VA ', VB' and common control lines CSB ', CS' are provided on the other side (left side in the drawing). The common pseudo power supply lines VA 'and VB' and the common control lines CSB 'and CS' are connected to the common pseudo power supply lines VA and VB and the common control line CS.
Similarly to B and CS, the lines in the middle logic circuits M1 to M3 are connected. With this configuration, current is supplied through the common pseudo power supply lines VA and VA ′,
Further, the current flows out through the common pseudo power supply lines VB and VB ', and the conduction resistance becomes smaller, and the power supply potential fluctuation is further suppressed.
In this embodiment, the common control lines CSB 'and CS' are provided on the other side sandwiching the middle logic circuit group.
B ', CS' are not provided, that is, the common control line CS
The configuration may be such that only B and CS are provided. CSB ', C
When S'is provided, it can be used as a spare.

Further, in each of the above-mentioned embodiments, the middle logic circuit has three stages, but it goes without saying that it is not limited to three stages. Various logic gates (for example, AND gate, OR gate, NAND gate, NOR gate, etc.) can be considered as the logic gates G1 to Gn, and a plurality of various logic gates may be connected. Further, in the above-described embodiment, the transistors forming QA1 to QA3, QB1 to QB3 and logic gates G1 to Gn are MOSF.
Although ET is used, that is, an insulated gate field effect transistor is used, a junction type field effect transistor may be used. Further, the common pseudo power supply lines VA and VB and the common control lines CSB and CS may be placed in the power supply cell SLn + 1. Further, the power supply cell SLn + 1 in the middle logic circuit M1 does not necessarily have to be provided at the end, and may be arranged at any position.

[0017]

As is apparent from the above description, according to the present invention, the first pseudo power supply lines of each middle logic circuit are connected to each other through the first common pseudo power supply line, and each middle logic circuit is connected. The second pseudo power supply lines of the circuit are mutually connected through the second common pseudo power supply line, and the gates of the first power control field effect transistors of the respective middle logic circuits are mutually connected to the first common control line. Since the gates of the second power control field-effect transistors of each middle logic circuit are connected to each other through the second common control line, for example, the small logic circuits arranged in the top middle logic circuit are connected. When all the logic circuits are switched at the same time, not only the first power control field-effect transistor of the middle logic circuit in the uppermost stage but also the first power control field-effect transistor of the other middle logic circuit becomes the first power control field effect transistor. Through the common pseudo power supply line A current flows into the first pseudo power supply line of the circuit, and not only the second power control field effect transistor of the uppermost middle logic circuit but also the second power control field effect transistor of the other middle logic circuit. Also flows out from the second pseudo power supply line of the uppermost middle logic circuit via the second common pseudo power supply line, and the potential difference applied between the power supply terminals of the small logic circuit is almost equal to the power supply voltage. It becomes equal, sufficient speed performance can be obtained, and high speed can be realized without any trouble. Further, if the first and second common control lines are connected to the first and second control signal terminals and the control signal is given to the first and second control signal terminals, all middle logic circuits The control signal reaches the gates of the first and second electric power control field effect transistors, and the number of external control signal lines is reduced,
It is possible to reduce the area.

[Brief description of drawings]

FIG. 1 is a diagram showing an example (Example 1) of the present invention.

FIG. 2 is a diagram showing another embodiment (Example 2) of the present invention.

FIG. 3 is a diagram illustrating a conventional MT-CMOS circuit.

FIG. 4 is a diagram showing a conventional circuit example using a standard cell compatible with MT-CMOS.

[Explanation of symbols]

 SL1 to SLn + 1 standard cells G1 to Gn logic gates QA1 to QA3 power control MOSFETs QB1 to QB3 power control MOSFETs VDD actual power supply line (high potential) GND actual power supply line (low potential) VA common pseudo power supply line (high potential) VB Common pseudo power line (low potential) VA1 to VA3 Pseudo power line (high potential) VB1 to VB3 Pseudo power line (low potential) CS, CSB Common control line CS1 to CS3, CSB1 to CSB3 Control line

Front page continuation (72) Inventor Junzo Yamada 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation

Claims (3)

[Claims] 1. A first to nth small logic circuit composed of a low threshold field effect transistor, and a first pseudo power supply connected to one of power supply terminals of the first to nth small logic circuits. Line, a second pseudo power source line connected to the other of the power source terminals of the first to nth small logic circuits, and a line connected between the first pseudo power source line and the first real power source line. And a high threshold first power control field effect transistor, and a high threshold second power control electric field connected between the second pseudo power line and the second real power line. In a logic circuit having m stages of middle logic circuits each including an effect transistor, the first pseudo power supply lines of each of the middle logic circuits are connected to each other through a first common pseudo power supply line, The second pseudo power supply lines of each middle logic circuit are connected to each other through the second common pseudo power supply line, The gates of the first power control field effect transistors of the circuit are mutually connected via the first common control line, and the gates of the second power control field effect transistors of the middle logic circuits are second to each other. A logic circuit characterized in that they are connected via a common control line. 2. A first to nth small logic circuit composed of a low threshold field effect transistor, and a first pseudo power supply connected to one of power supply terminals of the first to nth small logic circuits. Line, a second pseudo power source line connected to the other of the power source terminals of the first to nth small logic circuits, and a line connected between the first pseudo power source line and the first real power source line. And a high threshold first power control field effect transistor, and a high threshold second power control electric field connected between the second pseudo power line and the second real power line. In a logic circuit having m stages of middle logic circuits each including an effect transistor, the first pseudo power supply lines of each of the middle logic circuits are mutually connected through first and third common pseudo power supply lines. The second pseudo power supply lines of each of the middle logic circuits are mutually connected via the second and fourth common pseudo power supply lines. Connected, the gates of the first power control field effect transistors of the middle logic circuits are connected to each other via a first common control line, and the second power control field effect transistors of the middle logic circuits are connected to each other. Are connected to each other via a second common control line, and the first and second common pseudo power supply lines and the first and second common control lines are provided on one side sandwiching the middle logic circuit group. A logic circuit provided, wherein the third and fourth common pseudo power supply lines are provided on the other side sandwiching the middle logic circuit group. 3. The logic circuit according to claim 1, wherein the low-threshold field effect transistor and the high-threshold first and second field effect transistors are MOSFETs.