JP3901610B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit using a gate array and an embedded array.
[0002]
[Prior art]
In recent years, large-scale integrated circuits (LSIs) using “gate arrays” have been actively designed. As shown in FIG. 9B, in the gate array, a master chip 14 in which the basic cells 10 shown in FIG. P shown in FIG. ⁺ A p-channel MOS transistor (pMOS transistor) can be configured by the type semiconductor region 12 and the gate electrode 11. n ⁺ An n-channel MOS transistor (nMOS transistor) can be configured by the type semiconductor region 13 and the gate electrode 11. An I / O cell 15 is arranged on the outer periphery of the master chip 14 shown in FIG. A desired LSI can be configured only by performing wiring connection on each basic cell 10 of the master chip 14 surrounded by the I / O cells 15. That is, an LSI can be developed in a short time by using a gate array. In addition, LSI design using an “embedded array” in which a highly integrated memory or the like is embedded in the master chip 14 has been actively performed.
[0003]
In digital circuits used in computer systems and the like, each digital circuit is often connected to another digital circuit via a buffer circuit. The buffer circuit includes the following circuits. The buffer circuit shown in FIG. 10A (hereinafter referred to as “first prior art”) outputs a high level signal to the output terminal 2 when a high level signal is input to the input terminal 1. When a low level signal is input to the input terminal 1, a high impedance output is obtained. From the output terminal 2, the pMOS transistor Tr ₃ Drain current is output. The buffer circuit shown in FIG. 10B (hereinafter referred to as “second prior art”) outputs a high impedance when a high level signal is input to the input terminal 1. When a low level signal is input to the input terminal 1, the low level signal is output to the output terminal 2. From the output terminal 2, the nMOS transistor Tr ₃ Drain current is output. The buffer circuit shown in FIG. 11 (hereinafter referred to as “third prior art”) outputs a high level signal to the output terminal 2 when a high level signal is input to the input terminal 1, and outputs a low level to the input terminal 1. When a signal is input, a low level signal is output to the output terminal 2. From the output terminal 2, the pMOS transistor Tr ₃ NMOS transistor Tr ₄ One of the drain currents is output. Note that the drain current of the MOS transistor can be reduced by increasing the gate length L and decreasing the gate width W shown in FIG.
[0004]
[Problems to be solved by the invention]
In the first prior art, in order to reduce the amount of current output from the output terminal 2, the pMOS transistor Tr ₃ The gate length L must be increased. In the second prior art, the nMOS transistor Tr ₃ The gate length L must be increased. In the third prior art, the pMOS transistor Tr ₃ NMOS transistor Tr ₄ Each of the gate lengths L had to be increased. However, miniaturization and high integration of LSIs have progressed, and it has become difficult to keep the gate length L of MOS transistors long. As the gate length L becomes shorter, the output current capability of the MOS transistor increases. In particular, the gate array has a structure in which basic cells 10 having a constant gate length L of MOS transistors are periodically arranged as shown in FIG. 9A. For this reason, it is impossible to change the gate length L of the basic cell 10 after forming the master chip shown in FIG. In order to change the structure of the basic cell 10, the modification from the previous process (diffusion process) is required, and the advantage of the gate array is lost. Furthermore, there is a problem that the development period of LSI becomes long.
[0005]
Further, it is possible to reduce the output current capability of the buffer circuit by configuring a complicated circuit. However, there is a problem that miniaturization of the LSI is hindered due to an increase in the transistor area in the LSI. Further, when the transistor area increases, the number of necessary basic cells 10 increases in proportion, and the area utilization efficiency decreases.
[0006]
In view of the above problems, an object of the present invention is to provide a semiconductor integrated circuit with a small amount of output current that can use an existing gate array and embedded array without increasing the area occupied by a transistor.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, a feature of the present invention is a semiconductor integrated circuit having first and second reference potential terminals, an input terminal, and an output terminal, comprising: (a) a first reference potential terminal and a second reference potential terminal; An inverter circuit that is connected between the first reference potential terminal and inverts an input signal input to the input terminal; (b) a first that has a source connected to the first reference potential terminal and a gate connected to the input terminal; (C) a second field effect transistor having a source connected to the drain of the first field effect transistor and a gate and a drain connected to the output node of the inverter circuit; (d) a first reference potential terminal; A third field effect transistor in which a source is connected to the gate, a gate is connected to a connection point between the drain of the first field effect transistor and the source of the second field effect transistor, and the drain is connected to the output terminal. And summarized in that a semiconductor integrated circuit comprising a register.
[0008]
According to the semiconductor integrated circuit of the present invention, the gate bias voltage of the third field effect transistor can be controlled by the first and second field effect transistors. The drain current of the third field effect transistor becomes the output current of the semiconductor integrated circuit according to the feature of the present invention. Therefore, by reducing the gate bias voltage of the third field effect transistor to about the threshold voltage, a semiconductor integrated circuit with a very small output current can be provided. The amount of output current can be reduced without correcting the gate length of the field effect transistor as in the prior art.
[0009]
Furthermore, a source is connected to the second reference potential terminal and a gate is connected to the input terminal, a source is connected to the drain of the fourth field effect transistor, and a gate is connected to the gate of the second field effect transistor. , A fifth field effect transistor having a drain connected to the drain of the second field effect transistor, a source connected to the second reference potential terminal, a drain of the fourth field effect transistor, and a fifth field effect transistor You may further provide the 6th field effect transistor which connected the gate to the connection point with a source, and connected the drain to the output terminal, respectively. In this case, the gate bias voltage of the sixth field effect transistor can be controlled by the fourth and fifth field effect transistors.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Next, first to third embodiments of the present invention will be described with reference to the drawings. In the descriptions of the drawings in the first to third embodiments, the same or similar parts are denoted by the same or similar reference numerals.
[0011]
(First embodiment)
As shown in FIG. 1, the semiconductor integrated circuit 5a according to the first embodiment of the present invention includes a semiconductor integrated circuit 5a having first and second reference potential terminals 6, 7, an input terminal 1, and an output terminal 2. The inverter circuit 3 is connected between the first reference potential terminal 6 and the second reference potential terminal 7 and inverts the input signal input to the input terminal 1, and is connected to the first reference potential terminal 6. A first field effect transistor Tr having a source connected and a gate connected to the input terminal 1 ₁ , First field effect transistor Tr ₁ A second field effect transistor Tr having a source connected to the drain and a gate and a drain connected to the output node of the inverter circuit 3 ₂ The source is connected to the first reference potential terminal 6, and the first field effect transistor Tr ₁ Drain and second field effect transistor Tr ₂ Connection point P with the source of ₂ A third field effect transistor Tr having a gate connected to the output terminal and a drain connected to the output terminal 2 ₃ With. The first reference potential terminal 6 has a high power supply V _DD Is connected. The second reference potential terminal 7 has a low power supply V _SS Is connected.
[0012]
The inverter circuit 3 includes a fourth field effect transistor Tr having a source connected to the first reference potential terminal 6, a gate connected to the input terminal 1, and a drain connected to the output node of the inverter circuit 3. ₄ , The source to the second reference potential terminal 7, the fourth field effect transistor Tr ₄ The fourth field effect transistor Tr ₄ Field effect transistor Tr having a drain connected to the drain of the first field effect transistor Tr ₅ It consists of. Fourth field effect transistor Tr ₄ Drain and fifth field effect transistor Tr ₅ Is the connection point P ₁ Are connected to each other. This connection point P ₁ Becomes an output node of the inverter circuit 3. Connection point P ₁ Includes a second field effect transistor Tr. ₂ Are connected to the drain and gate. The inverter circuit 3 inverts the digital signal input to the input terminal 1 and outputs the inverted signal from the output node.
[0013]
First field effect transistor Tr ₁ , Second field effect transistor Tr ₂ , Third field effect transistor Tr ₃ , Fourth field effect transistor Tr ₄ A pMOS transistor can be used. Fifth field effect transistor Tr ₅ NMOS transistors can be used. The third field effect transistor Tr ₃ Is used as an output current of the semiconductor integrated circuit 5a. The semiconductor integrated circuit 5 a shown in FIG. 1 outputs a high level signal to the output terminal 2 when a high level signal is input to the input terminal 1. When a low level signal is input to the input terminal 1, the output terminal 2 becomes a high impedance output.
[0014]
First to fifth field effect transistors Tr ₁ , Tr ₂ , Tr ₃ , Tr ₄ , Tr ₅ Is actually mounted on a master chip in which basic cells are periodically arranged. That is, the semiconductor integrated circuit 5a can be configured by using an existing gate array or embedded array basic cell. Therefore, the first to fourth field effect transistors (pMOS transistors) Tr ₁ , Tr ₂ , Tr ₃ , Tr ₄ All have the same structure, and each threshold voltage is V _thp Are equal. First to fifth field effect transistors Tr ₁ , Tr ₂ , Tr ₃ , Tr ₄ , Tr ₅ The wiring for connecting is formed on the master chip by multilayer wiring or the like.
[0015]
Connection point P ₁ The potential of V _P1 , Connection point P ₂ The potential of V _P2 Second field effect transistor (pMOS transistor) Tr ₂ Threshold voltage and gate-source potential of V _thp And V _gs2 Then, the second field effect transistor Tr ₂ To turn off:
V _P2 ≦ V _P1 ... (1)
｜ V _P1 -V _P2 |-| V _thp | = 0 (2)
It is necessary to satisfy one of the following. The second field effect transistor Tr ₂ To turn on:
V _P1 > V _P2 ... (3)
｜ V _P1 -V _P2 |-| V _thp | <0 (4)
It is necessary to satisfy the respective expressions. That is, | V _gs2 |-| V _thp Second field effect transistor (pMOS transistor) Tr when | <0 holds ₂ Turns on.
[0016]
Next, the operation of the semiconductor integrated circuit 5a according to the first embodiment of the present invention will be described with reference to FIG.
[0017]
(A) When a high level signal is input to the input terminal 1:
(A) When a high level signal is input to the input terminal 1, a high level signal is input to the inverter circuit 3. When a high level signal is input to the inverter circuit 3, the fourth field effect transistor (pMOS transistor) Tr ₄ And a fifth field effect transistor (nMOS transistor) Tr ₅ A high level signal is input to each of the gates. Fourth field effect transistor Tr ₄ Turn off. Fifth field effect transistor Tr ₅ Turns on and conducts. As a result, the fourth field effect transistor Tr ₄ Drain and fifth field effect transistor Tr ₅ Connection point P with the drain of ₁ From low power supply V _SS , That is, a low level signal is output.
[0018]
(B) At the same time when the high level signal is input to the inverter circuit 3, the first field effect transistor (pMOS transistor) Tr ₁ A high level signal is also input to the gates. First field effect transistor Tr ₁ Gate potential | V _gs1 | Is the threshold voltage | V _thp |, The first field effect transistor Tr ₁ Turns off.
[0019]
(C) The low level signal output from the inverter circuit 3 is the second field effect transistor (pMOS transistor) Tr ₂ Are input to the drain and gate. First field effect transistor Tr ₁ Turns off and connection point P ₂ The potential of V is V _DD Degree. Therefore, the second field effect transistor Tr that satisfies the conditions shown in the equations (3) and (4) is satisfied. ₂ Turns on.
[0020]
(D) Connection point P ₂ Potential V _P2 Gradually decreases. Connection point P ₂ Potential V _P2 Reaches the potential given by the following equation, the second field effect transistor Tr ₂ Turns off:
｜ V _P1 -V _P2 | = | V _thp | (5)
Second field effect transistor Tr ₂ Is turned off and the connection point P ₂ Potential V _P2 Maintains its potential. Where connection point P ₁ Potential V _P1 ≒ 0 [V] V _P2 = | V _thp | Therefore, the third field effect transistor Tr ₃ Turns on. Third field effect transistor Tr ₃ Is turned on, the output terminal 2 provides a high-level power supply V. _DD , That is, a high level signal is output.
[0021]
(B) When a low level signal is input to the input terminal 1:
(A) When a low-level signal is input to the input terminal 1, the fourth field effect transistor Tr constituting the inverter circuit 3 ₄ And the fifth field effect transistor Tr ₅ A low level signal is input to each of the gates. Fourth field effect transistor Tr ₄ Turns on. Fifth field effect transistor Tr ₅ Turn off. As a result, the fourth field effect transistor Tr ₄ Drain and fifth field effect transistor Tr ₅ Connection point P with the drain of ₁ From high power supply V _DD , That is, a high level signal is output.
[0022]
(B) At the same time, the first field effect transistor Tr ₁ A low level signal is input to the gate of the first. First field effect transistor Tr ₁ Gate potential V _gs1 Is the first field effect transistor Tr ₁ Threshold voltage V _thp Smaller than. As a result, the first field effect transistor Tr ₁ Turns on. Therefore, connection point P ₂ Potential V _P2 Becomes a high level potential.
[0023]
(C) Connection point P ₁ Potential V _P1 And connection point P ₂ Potential V _P2 Respectively have a high level potential. Second field effect transistor Tr ₂ A high level signal is input to the drain and the gate. Therefore, the second field effect transistor Tr that satisfies the expression (1) is satisfied. ₂ Turn off.
[0024]
(D) Connection point P ₂ Potential V _P2 Becomes a high level potential, the third field effect transistor Tr ₃ Gate potential V _gs3 Becomes a high level potential. Third field effect transistor Tr ₃ Gate potential V _gs3 Becomes a high level potential, the third field effect transistor Tr ₃ Turn off. Therefore, no current is output from the output terminal 2 and a high impedance (Hi-Z) state is established.
[0025]
Thus, according to the first embodiment, the third field effect transistor Tr ₃ The gate bias voltage can be reduced. Therefore, the amount of current output from the output terminal 2 is smaller than in the conventional case. In addition, the semiconductor integrated circuit 5a uses a small number of transistors and does not increase the area occupied by the transistors. Further, since it is not necessary to change the gate length L of the MOS transistor, it is not necessary to change the structure of the basic cell of the master chip. Therefore, the semiconductor integrated circuit 5a can be configured using an existing gate array and embedded array.
[0026]
As shown in FIG. 2, the semiconductor integrated circuit 5b according to the modification of the first embodiment includes a second field effect transistor (pMOS transistor) Tr. ₂ A drain and a gate are connected to the source of the third field effect transistor (pMOS transistor) Tr ₃ Sixth field effect transistor Tr having a source connected to the gate of the transistor ₆ 1 is different from FIG. Sixth field effect transistor Tr ₆ Is composed of pMOS transistors. Second field effect transistor Tr ₂ Source and sixth field effect transistor Tr ₆ The connection point with the drain of P _A , Connection point P _A The potential of V _PA In particular, the second field effect transistor Tr ₂ The conditions for turning on are:
｜ V _PA -V _P1 |-| V _thp |> 0 (V _PA > V _P1 (6)
It becomes. Where V _P1 When ≈0 [V], the second field effect transistor Tr ₂ The condition for turning on is V _PA > | V _thp | The sixth field effect transistor Tr ₆ The conditions for turning on are:
｜ V _P2 -V _PA |-| V _thp |> 0 (V _P2 > V _PA ) ... (7)
It becomes. Substituting the condition of equation (6) into equation (7) and rearranging:
V _P2 > 2 × | V _thp | (8)
Holds. Thus, the sixth field effect transistor (pMOS transistor) Tr ₆ To connect the second field effect transistor Tr ₂ | V _thp The effect of doubling | can be obtained. Therefore, when a low level signal is output from the inverter circuit 3, the third field effect transistor Tr ₃ The gate bias voltage is further reduced. Third field effect transistor Tr ₃ Therefore, the amount of current output from the output terminal 2 is further reduced as compared with the amount of output current of the semiconductor integrated circuit 5a according to the first embodiment. Thus, the second field effect transistor Tr ₂ A second field effect transistor Tr by connecting a multi-stage field effect transistor (pMOS transistor) in series with the second field effect transistor Tr ₂ | V _thp An effect equivalent to double | Therefore, the third field effect transistor Tr ₃ Can be sufficiently reduced.
[0027]
(Second Embodiment)
As shown in FIG. 3, the semiconductor integrated circuit 5c according to the second embodiment of the present invention includes a fourth field effect transistor (pMOS transistor) Tr. ₄ Source and fifth field effect transistor (nMOS transistor) Tr ₅ 1 is different from FIG. 1 in that the source is connected to the second reference potential terminal 7 and the first reference potential terminal 6. Further, the first reference potential terminal 6 is connected to the low power supply V. _SS And the second reference potential terminal 7 is connected to the high-level power supply V _DD 1 is different from FIG. First field effect transistor Tr ₁ , Second field effect transistor Tr ₂ , Third field effect transistor Tr ₃ 1 is different from FIG. 1 in that nMOS transistors are used. First to fifth field effect transistors Tr ₁ , Tr ₂ , Tr ₃ , Tr ₄ , Tr ₅ Is mounted on a gate array or an embedded array as in the first embodiment. Other structures are the same as those of the semiconductor integrated circuit 5a shown in FIG. In the semiconductor integrated circuit 5c shown in FIG. 3, when a high level signal is inputted to the input terminal 1, the output terminal 2 becomes a high impedance output. When a low level signal is input to the input terminal 1, the low level signal is output to the output terminal 2.
[0028]
Connection point P ₁ The potential of V _P1 , Connection point P ₂ The potential of V _P2 , Second field effect transistor (nMOS transistor) Tr ₂ Threshold voltage of V _thn Then, the second field effect transistor Tr ₂ The conditions to turn off are:
｜ V _P1 -V _P2 |-| V _thn | ≦ 0 (9)
It becomes. That is, | V _gs2 |-| V _thn When | ≦ 0 is satisfied, the second field effect transistor Tr ₂ Turns off.
[0029]
Next, the operation of the semiconductor integrated circuit 5c according to the second embodiment of the present invention will be described with reference to FIG. However, the description of the same operation as that of the semiconductor integrated circuit 5a according to the first embodiment is partially omitted.
[0030]
(A) When a high level signal is input to the input terminal 1:
(A) When a high level signal is input to the input terminal 1, the inverter circuit 3 outputs a low level signal. At the same time as the high level signal is input to the input terminal 1, the first field effect transistor (nMOS transistor) Tr ₁ A high level signal is input to the gate. As a result, the first field effect transistor Tr ₁ Turns on.
[0031]
(B) First field effect transistor Tr ₁ Turns on, connection point P ₂ Potential V _P2 Becomes a low level potential. Second field effect transistor (nMOS transistor) Tr ₂ Gate-source potential V _gs2 Becomes 0 [V]. Therefore, from the equation (9), the second field effect transistor Tr ₂ Turn off.
[0032]
(C) Connection point P ₂ Potential V _P2 Becomes a low level potential, the third field effect transistor (nMOS transistor) Tr ₃ The gate potential is also a low level potential. Third field effect transistor Tr ₃ When the gate potential of the third transistor becomes low level, the third field effect transistor Tr ₃ Turn off. Therefore, the output terminal 2 becomes a high impedance (Hi-Z) output.
[0033]
(B) When a low level signal is input to the input terminal 1:
(A) When a low level signal is input to the input terminal 1, the inverter circuit 3 outputs a high level signal. At the same time as the low level signal is input to the input terminal 1, the first field effect transistor Tr ₁ A low level signal is input to the gate of the first. First field effect transistor Tr ₁ When a low level signal is input to the gate of the first field effect transistor Tr ₁ Turns off.
[0034]
(B) Connection point P ₁ Potential V _P1 Is a high level potential, the second field effect transistor Tr ₂ Turns on. Second field effect transistor Tr ₂ When turned on, V _P2 = V _DD − | V _thn |
[0035]
(C) Second field effect transistor Tr ₂ Is turned on, the third field effect transistor Tr ₃ Also turn on. As a result, a low level signal is output from the output terminal 2. Third field effect transistor Tr ₃ The gate bias voltage is reduced as compared with the prior art.
[0036]
According to the second embodiment, it is possible to provide the semiconductor integrated circuit 5c with a small output current amount that outputs a low level signal to the output terminal 2 only when a low level signal is input to the input terminal 1. The first to third field effect transistors Tr ₁ , Tr ₂ , Tr ₃ Can be operated at high speed. The semiconductor integrated circuit 5c shown in FIG. 3 can be configured using an existing gate array and embedded array without modifying the basic cell structure of the master chip, as in the semiconductor integrated circuit 5a shown in FIG.
[0037]
As shown in FIG. 4, a semiconductor integrated circuit 5d according to a modification of the second embodiment includes a second field effect transistor (nMOS transistor) Tr. ₂ A drain and a gate are connected to the source of the third field effect transistor (nMOS transistor) Tr ₃ Sixth field effect transistor Tr having a source connected to the gate of the transistor ₆ 3 is different from FIG. Sixth field effect transistor Tr ₆ Is composed of nMOS transistors. Second field effect transistor Tr ₂ Source and sixth field effect transistor Tr ₆ The connection point with the drain of P _A , Connection point P _A The potential of V _PA In particular, the second field effect transistor Tr ₂ The conditions for turning on are:
(V _P1 -V _PA -V _thn > 0 (10)
It becomes. Where V _P1 ≒ V _DD Assuming [V], the second field effect transistor Tr ₂ The condition for turning on is V _PA <V _DD -V _thn It becomes. The sixth field effect transistor Tr ₆ The conditions for turning on are:
(V _PA -V _P2 -V _thn > 0 (11)
It becomes. Substituting the condition of equation (10) into equation (11) and rearranging:
V _P2 <V _DD -2 x V _thn (12)
Holds. That is, the sixth field effect transistor (nMOS transistor) Tr ₆ Is connected to the second field effect transistor Tr. ₂ V _thn The effect of doubling can be obtained. Therefore, when a high level signal is output from the inverter circuit 3, the third field effect transistor Tr ₃ The gate bias voltage is further reduced. Further, as in the modification of the first embodiment, the second field effect transistor Tr ₂ A plurality of stage field effect transistors (nMOS transistors) may be connected in series.
[0038]
(Third embodiment)
As shown in FIG. 5, the semiconductor integrated circuit 5e according to the third embodiment of the present invention has a fourth field effect in which a source is connected to the second reference potential terminal 7 and a gate is connected to the input terminal 1. Transistor Tr ₄ , Fourth field effect transistor Tr ₄ The source is connected to the drain of the second field effect transistor Tr. ₂ Of the second field effect transistor Tr ₂ Field effect transistor Tr having a drain connected to the drain of the first field effect transistor Tr ₅ , The source to the second reference potential terminal 7, the fourth field effect transistor Tr ₄ Drain and fifth field effect transistor Tr ₅ Connection point P with the source of ₃ And a sixth field effect transistor Tr having a drain connected to the output terminal 2 and a drain connected to the output terminal 2, respectively. ₆ 1 is different from FIG. Fourth field effect transistor Tr ₄ , Fifth field effect transistor Tr ₅ , Sixth field effect transistor Tr ₆ NMOS transistors can be used.
[0039]
The inverter circuit 3 includes a seventh field effect transistor Tr having a source connected to the first reference potential terminal 6, a gate connected to the input terminal 1, and a drain connected to the output node of the inverter circuit 3. ₇ , The source to the second reference potential terminal 7, the seventh field effect transistor Tr ₇ The eighth field effect transistor Tr has a gate connected to the gate of the transistor and a drain connected to the output node of the inverter circuit 3. ₈ It consists of. Other structures are the same as those of the semiconductor integrated circuit 5a shown in FIG. The semiconductor integrated circuit 5 e shown in FIG. 5 outputs a high level signal to the output terminal 2 when a high level signal is input to the input terminal 1. On the other hand, when a low level signal is input to the input terminal 1, the low level signal is output to the output terminal 2.
[0040]
Connection point P ₁ The potential of V _P1 , Connection point P ₃ The potential of V _P3 , Fifth field effect transistor (nMOS transistor) Tr ₅ Threshold voltage of V _thn Then, the fifth field effect transistor Tr ₅ The conditions to turn off are:
｜ V _P1 -V _P3 |-| V _thn | ≦ 0 (13)
It becomes. That is, | V _gs5 |-| V _thn If | ≦ 0 is satisfied, the fifth field effect transistor Tr ₅ Turn off.
[0041]
Next, the operation of the semiconductor integrated circuit 5e according to the third embodiment of the present invention will be described with reference to FIG. However, the description of the same operations as those of the semiconductor integrated circuits 5a and 5c according to the first and second embodiments is partially omitted.
[0042]
(A) When a high level signal is input to the input terminal 1:
(A) When a high level signal is input to the input terminal 1, the inverter circuit outputs a low level signal. At the same time as the high level signal is input to the input terminal 1, the first field effect transistor (pMOS transistor) Tr ₁ And a fourth field effect transistor (nMOS transistor) Tr ₄ A high level signal is input to each of the gates. First field effect transistor Tr ₁ When a high level signal is input to the gate of the first field effect transistor (pMOS transistor) Tr ₁ Turns off. Fourth field effect transistor (nMOS transistor) Tr ₄ When a high level signal is input to the gate of the fourth field effect transistor Tr ₄ Turns on.
[0043]
(B) The low level signal output from the inverter circuit 3 is the second field effect transistor (pMOS transistor) Tr ₂ And a fifth field effect transistor (nMOS transistor) Tr ₅ Are input to each drain and gate. First field effect transistor Tr ₁ Turns off and connection point P ₂ The potential of V is V _DD Degree. Therefore, the second field effect transistor Tr is satisfied by satisfying the conditions shown in the expressions (1) and (2). ₂ Turns on. On the other hand, the fifth field effect transistor Tr ₅ Turn off. Fourth field effect transistor Tr ₄ Is on, the fifth field effect transistor Tr ₅ Will turn off so connection point P ₃ Becomes a low level potential. Connection point P ₃ Becomes the low level, the sixth field effect transistor (nMOS transistor) Tr ₆ Turn off.
[0044]
(C) Connection point P ₂ Potential V _P2 Gradually decreases. Connection point P ₂ Potential V _P2 Reaches the potential given by equation (5), the second field effect transistor Tr ₂ Is turned off and the connection point P ₂ Potential V _P2 Maintains its potential. Where connection point P ₁ Potential V _P1 ≒ 0 [V] V _P2 = | V _thp | As a result, a high level signal is output from the output terminal 2.
[0045]
(B) When a low level signal is input to the input terminal 1:
(A) When a low level signal is input to the input terminal 1, the inverter circuit 3 outputs a high level signal. At the same time as the low level signal is input to the input terminal 1, the first field effect transistor Tr ₁ And the fourth field effect transistor Tr ₄ A low level signal is input to each of the gates. First field effect transistor Tr ₁ When a low level signal is input to the gate of the first field effect transistor Tr ₁ Turns on. Fourth field effect transistor Tr ₄ When a low level signal is input to the gate of the fourth field effect transistor Tr ₄ Turns off.
[0046]
(B) When the fourth field effect transistor is turned off, the connection point P ₃ Is approximately 0 [V]. Connection point P ₁ Potential V _P1 Is a high level potential. Therefore, from the equation (13), the fifth field effect transistor Tr ₅ Turns on. On the other hand, the second field effect transistor Tr ₂ Turn off. First field effect transistor Tr ₁ Is on, the second field effect transistor Tr ₂ Will turn off so connection point P ₁ Becomes a high level potential. Connection point P ₁ Becomes a high level potential, the third field effect transistor Tr ₃ Turn off.
[0047]
(C) Connection point P ₃ Potential V _P3 Reaches the potential given by the following equation, the fifth field effect transistor Tr ₅ Turns off:
｜ V _P1 -V _P3 | = | V _thn | (14)
When the expression (14) is satisfied, the fifth field effect transistor Tr ₅ Is turned off and the connection point P ₃ Potential V _P3 Maintains its potential. Where connection point P ₁ Potential V _P1 ≒ V _DD [V] means V _P3 = V _DD -V _thn It becomes.
[0048]
According to the third embodiment, the third field effect transistor Tr ₃ And the sixth field effect transistor Tr ₆ The gate bias voltage can be reduced. Therefore, it is possible to provide the semiconductor integrated circuit 5e with a small output current amount that outputs the logic level input to the input terminal 1 to the output terminal 2 as it is. The amount of output current of the semiconductor integrated circuit 5e is reduced compared to the conventional case when the output is either a high level signal or a low level signal. Similarly to the semiconductor integrated circuit 5a shown in FIG. 1, the semiconductor integrated circuit 5c can be configured using a gate array and an embedded array.
[0049]
As shown in FIG. 6, the semiconductor integrated circuit 5f according to the first modification of the third embodiment includes a second field effect transistor (pMOS transistor) Tr. ₂ A drain and a gate are connected to the source of the third field effect transistor (pMOS transistor) Tr ₃ Field effect transistor Tr having a source connected to the gate of the transistor ₉ 5 is different from FIG. Ninth field effect transistor Tr ₉ Is composed of pMOS transistors. Second field effect transistor Tr ₂ Source and the ninth field effect transistor Tr ₉ The connection point with the drain of P _A , Connection point P _A The potential of V _PA In particular, the second field effect transistor Tr ₂ The conditions for turning on are:
｜ V _PA -V _P1 |-| V _thp |> 0 (V _PA > V _P1 ... (15)
It becomes. Where V _P1 When ≈0 [V], the second field effect transistor Tr ₂ The condition for turning on is V _PA > | V _thp | The ninth field effect transistor Tr ₉ The conditions for turning on are:
｜ V _P2 -V _PA |-| V _thp |> 0 (V _P2 > V _PA ... (16)
It becomes. Substituting the condition of equation (15) into equation (16) and rearranging:
V _P2 > 2 × | V _thp | (17)
Holds. That is, the ninth field effect transistor (pMOS transistor) Tr ₉ To connect the second field effect transistor Tr ₂ | V _thp An effect equivalent to doubling | can be obtained. That is, the connection point P ₂ Can be further reduced. Therefore, the third field effect transistor Tr ₃ It is possible to further reduce the gate bias voltage. Furthermore, the second field effect transistor Tr ₂ And a multi-stage field effect transistor (pMOS transistor) may be connected in series.
[0050]
As shown in FIG. 7, the semiconductor integrated circuit 5g according to the second modification of the third embodiment includes a fifth field effect transistor (nMOS transistor) Tr. ₅ A drain and a gate are connected to the source of a sixth field effect transistor (nMOS transistor) Tr ₆ Field effect transistor Tr having a source connected to the gate of the transistor ₉ 5 is different from FIG. Ninth field effect transistor Tr ₉ Is composed of nMOS transistors. Second field effect transistor Tr ₂ Source and the ninth field effect transistor Tr ₉ The connection point with the drain of P _A , Connection point P _A The potential of V _PA In particular, the second field effect transistor Tr ₂ The conditions for turning on are:
(V _P1 -V _PA -V _thn > 0 (18)
It becomes. Where V _P1 ≒ V _DD Assuming [V], the second field effect transistor Tr ₂ The condition for turning on is V _PA <V _DD -V _thn It becomes. The ninth field effect transistor Tr ₉ The conditions for turning on are:
(V _PA -V _P2 -V _thn > 0 (19)
It becomes. Substituting the condition of equation (18) into equation (19) and rearranging:
V _P2 <V _DD -2 x V _thn ... (20)
Holds. That is, the ninth field effect transistor (nMOS transistor) Tr ₉ To connect the fifth field effect transistor Tr ₅ V _thn An effect equivalent to doubling the value can be obtained. Therefore, when a high level signal is output from the inverter circuit 3, the sixth field effect transistor Tr ₆ The gate bias voltage is further reduced. Further, a fifth field effect transistor Tr ₅ A plurality of stage field effect transistors (nMOS transistors) may be connected in series.
[0051]
As shown in FIG. 8, the semiconductor integrated circuit 5h according to the third modification of the third embodiment includes a second field effect transistor (pMOS transistor) Tr. ₂ A drain and a gate are connected to the source of the third field effect transistor (pMOS transistor) Tr ₃ Field effect transistor Tr having a source connected to the gate of the transistor ₉ , Fifth field effect transistor (nMOS transistor) Tr ₅ A drain and a gate are connected to the source of a sixth field effect transistor (nMOS transistor) Tr ₆ Tenth field effect transistor Tr having a source connected to its gate ₁₀ 5 is different from FIG. Ninth field effect transistor Tr ₉ Is composed of pMOS transistors. Tenth field effect transistor Tr ₁₀ Is composed of nMOS transistors. Therefore, the third field effect transistor Tr ₃ And the sixth field effect transistor Tr ₆ It becomes possible to further reduce the respective gate bias voltages. Furthermore, the second field effect transistor Tr ₂ And a multi-stage field effect transistor (pMOS transistor) may be connected in series. The fifth field effect transistor Tr ₅ A plurality of stage field effect transistors (nMOS transistors) may be connected in series.
[0052]
(Other embodiments)
As described above, the present invention has been described according to the first to third embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.
[0053]
In the first to third embodiments, it has been described that the semiconductor integrated circuits 5a, 5b,..., 5h are configured using a gate array and an embedded array. However, a monolithic integrated circuit may be configured by monolithically integrating on the same semiconductor substrate without using the gate array and the embedded array. Alternatively, individual semiconductor elements may be mounted on a printed circuit board or the like and configured as a hybrid integrated circuit. Furthermore, although MOS transistors are used as field effect transistors, various field effect transistors such as junction field effect transistors (JFETs), MESFETs, and high electron mobility transistors (HEMTs) can be used. It is.
[0054]
In the first to third embodiments, a CMOS type inverter circuit 3 is used as the inverter circuit. For example, the inverter circuit may have a structure in which a resistor and an nMOS transistor are connected in series. In this case, a signal is input to the gate of the nMOS transistor, and a connection point between the resistor and the nMOS transistor becomes an output node. Further, an nMOS transistor and an nMOS transistor may be connected in series. In this case, a signal is input to the gate of one of the nMOS transistors, and a connection point between the nMOS transistor and the nMOS transistor becomes an output node.
[0055]
Thus, it should be understood that the present invention includes various embodiments and the like not described herein. Therefore, the present invention is limited only by the invention specifying matters in the scope of claims reasonable from this disclosure.
[0056]
【The invention's effect】
According to the present invention, it is possible to provide a semiconductor integrated circuit with a small output current amount that can use an existing gate array and embedded array without increasing the transistor occupation area.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram of a semiconductor integrated circuit according to a modification of the first embodiment of the present invention.
FIG. 3 is a circuit diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.
FIG. 4 is a circuit diagram of a semiconductor integrated circuit according to a modification of the second embodiment of the present invention.
FIG. 5 is a circuit diagram of a semiconductor integrated circuit according to a third embodiment of the present invention.
FIG. 6 is a circuit diagram of a semiconductor integrated circuit according to a first modification of the third embodiment of the present invention.
FIG. 7 is a circuit diagram of a semiconductor integrated circuit according to a second modification of the third embodiment of the present invention.
FIG. 8 is a circuit diagram of a semiconductor integrated circuit according to a third modification of the third embodiment of the present invention.
FIG. 9A is a schematic top view showing a conventional basic cell, and FIG. 9B is a schematic top view showing a conventional master chip.
FIG. 10A and FIG. 10B are circuit diagrams of conventional buffer circuits.
FIG. 11 is a circuit diagram of a conventional buffer circuit.
[Explanation of symbols]
1 Input terminal
2 Output terminal
3 Inverter circuit
5a, 5b, 5c ... Semiconductor integrated circuit
6 First reference potential terminal
7 Second reference potential terminal
10 basic cells
11 Gate electrode
12 p ⁺ Type semiconductor region
13 n ⁺ Type semiconductor region
14 Master chip
15 I / O cell
Tr ₁ First field effect transistor
Tr ₂ Second field effect transistor
Tr ₃ Third field effect transistor
Tr ₄ Fourth field effect transistor
Tr ₅ Fifth field effect transistor
Tr ₆ Sixth field effect transistor
Tr ₇ Seventh field effect transistor
Tr ₈ Eighth field effect transistor
Tr ₉ Ninth field effect transistor
Tr ₁₀ Tenth field effect transistor

Claims (10)

A semiconductor integrated circuit having first and second reference potential terminals, an input terminal, and an output terminal,
An inverter circuit connected between the first reference potential terminal and the second reference potential terminal and inverting an input signal input to the input terminal;
A first field effect transistor having a source connected to the first reference potential terminal and a gate connected to the input terminal;
A source connected to a drain of the first field effect transistor, a second field effect transistor having a gate and a drain connected to an output node of the inverter circuit; a source connected to the first reference potential terminal; And a third field effect transistor having a gate connected to a connection point between a drain of the first field effect transistor and a source of the second field effect transistor and a drain connected to the output terminal. Semiconductor integrated circuit. The inverter circuit is
A fourth field effect transistor having a source connected to the first reference potential terminal, a gate connected to the input terminal, and a drain connected to the output node;
2. The semiconductor integrated circuit according to claim 1, further comprising: a fifth field effect transistor having a source connected to the second reference potential terminal, a gate connected to the input terminal, and a drain connected to the output node. 3. The semiconductor integrated circuit according to claim 1, wherein the first reference potential terminal is set to a higher potential than the second reference potential terminal. 3. The semiconductor integrated circuit according to claim 1, wherein the second reference potential terminal is set to a higher potential than the first reference potential terminal. 5. A sixth field effect transistor, further comprising a sixth field effect transistor having a drain and a gate connected to a source of the second field effect transistor and a source connected to a gate of the third field effect transistor. The semiconductor integrated circuit according to any one of the above. A fourth field effect transistor having a source connected to the second reference potential terminal and a gate connected to the input terminal;
A fifth field effect transistor having a source connected to the drain of the fourth field effect transistor, a gate connected to the gate of the second field effect transistor, and a drain connected to the drain of the second field effect transistor;
A source connected to the second reference potential terminal, a gate connected to a connection point between the drain of the fourth field effect transistor and the source of the fifth field effect transistor, and a drain connected to the output terminal; The semiconductor integrated circuit according to claim 1, further comprising a field effect transistor. 7. The ninth field effect transistor according to claim 6, further comprising a ninth field effect transistor having a drain and a gate connected to a source of the second field effect transistor and a source connected to a gate of the third field effect transistor. Semiconductor integrated circuit. 7. The ninth field effect transistor according to claim 6, further comprising a ninth field effect transistor having a drain and a gate connected to a source of the fifth field effect transistor and a source connected to a gate of the sixth field effect transistor. Semiconductor integrated circuit. 8. The tenth field effect transistor according to claim 7, further comprising a tenth field effect transistor having a drain and a gate connected to a source of the fifth field effect transistor and a source connected to a gate of the sixth field effect transistor. Semiconductor integrated circuit. The inverter circuit, the first field effect transistor, the second field effect transistor, and the third field effect transistor are mounted on a master chip in which basic cells are periodically arranged. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is characterized in that:

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