JPH0818021A - Gate array type integrated circuit - Google Patents

Abstract

PURPOSE:To realize an MT-CMOS circuit without reducing the availability of a cell in a gate cell array by arranging a cell array having field effect transistors with high threshold voltage adjacent to a cell array having field effect transistors with low threshold voltage. CONSTITUTION:First and second logical circuits 7 and 7' of a first basic cell are comprised of transistors with low threshold value and are connected between a high-potential psuedo power supply line VDDV and low-potential actual power supply line VSS. A power supply control circuit 8 of a second basic cell is comprised of transistors with high threshold value and is connected between a high-potential actual power supply line VDD and high-potential psuedo power supply line VDDV. In the circuit 8, transistors QH1 and QH2 are connected in parallel, forming a transfer gate, and it becomes conductive when a sleep signal is at a low potential and supplies a power, while it stops power supplying when the signal is at a high potential. Thus, an MT-CMOS circuit can be realized on one LSI chip without reducing the availability of a cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate array type semiconductor integrated circuit, and more particularly to a low-voltage high-speed operation CMOS composed of a low threshold voltage transistor and a high threshold voltage transistor. The present invention relates to a gate array type integrated circuit corresponding to a circuit.

[0002]

2. Description of the Related Art A gate array type semiconductor integrated circuit is
By arranging in advance a basic cell composed of a plurality of transistor elements in a matrix on a semiconductor wafer and connecting the basic cells with wirings, a desired circuit function is realized, and an integrated circuit can be obtained in a short period of time. There is an advantage.

FIG. 10 shows a schematic view of an LSI chip 11 of a conventional gate array (reference document "ULSI design technology", supervised by Takuo Sugano, Institute of Electronics, Information and Communication Engineers). This LSI
In the central portion of the chip 11, basic cells 12 are arranged in a matrix to form a cell array 12A, and in the peripheral portion, an input / output buffer cell row 13 for interfacing with the outside is arranged.

FIG. 11 shows a conventionally used CMOS.
It is a figure which shows one basic cell 12 of a gate array type. Q11 and Q12 are P-channel type MOS field effect transistors (hereinafter referred to as MOS transistors),
Q13 and Q14 are N-channel type MOS transistors, and both are used as transistors forming a logic gate.

Since an example of forming a transistor in a P-type substrate is described here, P-channel MOS transistors Q11 and Q12 are formed in the n-well 121. 122 is ap ⁺ region that functions as a source or drain of a P-channel MOS transistor, 123 is an n ⁺ region that functions as a source or drain of an N-channel MOS transistor, and 124 is a gate electrode.

The transistors Q11 and Q12 may have different sizes, but the threshold voltages that have a significant effect on the device characteristics are set to the same value. The same applies to the transistors Q13 and Q14.

FIG. 12 shows an example of connection for realizing a 2-input NAND gate, and FIG. 13 shows an equivalent circuit thereof. 12
The black circles in indicate the contact position to the source, drain, or gate electrode of the MOS transistor. Also,
A1 and A2 are input terminals, Y is an output terminal, VDD is a high potential real power supply line, and VSS is a low potential real power supply line.

By the way, in recent years, in order to meet the demand for portability of various electronic devices, low voltage operation of semiconductor integrated circuits has been promoted. As a technology for that purpose, the 5th volume of the 1994 Spring Conference of the Institute of Electronics, Information and Communication Engineers 5-195
MT-CMOS (Multi-Threshold CM
The OS circuit is shown in FIG. 14 as an example.

In FIG. 14, a logic circuit (2-input NAN
Transistors Q21 to Q24 forming the D gate 14
Is a low threshold voltage transistor. Logic circuit 14
The power supply terminal on the high potential side is connected to the high potential pseudo power supply line VDDV, and the power supply terminal on the low potential side is the low potential real power supply terminal VSS.
Connected to. Between the high potential pseudo power source line VDDV and the high potential actual power source line VDD, M for controlling the power source of the high threshold voltage is provided.
The OS transistor QH11 is connected. Then, the sleep signal SL for power supply control is input to the gate of the MOS transistor QH11.

During operation, the sleep signal SL is set to a low potential. As a result, the PMOS transistor QH1
1 is conductive, and the high potential pseudo power supply line VDDV can be regarded as the high potential real power supply line VDD. At this time, since the logic circuit 14 connected to the high potential pseudo power supply line VDDV is composed of the MOS transistors Q21 to Q24 having a low threshold voltage, it operates at a high speed even with an extremely low voltage of 1 V or less.

In general, the MOS transistor has a problem that when the absolute value of the threshold voltage is lowered, the leak current blocking capability is lowered and the current at the time of standby (at the time of interruption) is increased. In MT-CMOS circuit technology, a power control function called sleep control is introduced to avoid this problem. That is, the circuit is put in a sleep state at the time of styling where the circuit is not operated. Specifically, the sleep signal S
L is set to high potential and P channel MOS transistor QH
11 is cut off. As a result, the high potential real power line VD
Since the interrupted high threshold voltage P-channel MOS transistor QH11 is sandwiched between D and the low potential real power supply line VSS, the low threshold voltage MOS transistor Q
It is possible to cut the standby leak current that would occur in 21 to Q24, and it is possible to realize ultra-low power characteristics.

As described above, the MT-CMOS circuit technology is promising as a low-voltage high-speed circuit technology, but in order to realize this circuit in an actual LSI, a high threshold voltage is required on one LSI chip. Must be mixed with low threshold voltage transistors.

[0013]

However, in the conventional gate array widely used as a simple LSI realization method, both the P-channel type MOS transistor and the N-channel type MOS transistor have a single threshold voltage. The basic cells composed of MOS transistors are simply arranged and arranged in an array.

An object of the present invention is to provide a gate array integrated circuit capable of realizing an MT-CMOS circuit technology using a plurality of types of field effect transistors having different threshold voltages without reducing the utilization rate of the gate array. Is to provide.

[0015]

To achieve this object, a gate array type integrated circuit of the present invention comprises a first basic cell composed of a field effect transistor and a field effect transistor constituting the first basic cell. Also comprises a second basic cell composed of a field effect transistor having a large absolute value of threshold voltage, at least one cell array is formed by the first basic cell, and at least one by the second basic cell. Another cell array is formed, and one of the left, right, top, and bottom ends of the cell array including the first basic cell, both left and right ends, both upper and lower ends, all left and right top and bottom ends, or internally, from the second basic cell. The cell array is formed adjacent to each other.

In the present invention, it is preferable that the first basic cell forms a logic circuit group and the second basic cell forms a power supply control circuit that controls power supply to the logic circuit group.

Further, according to the present invention, a logic circuit group formed of the transistors forming the first basic cell and having first and second power supply terminals and a transistor forming the second basic cell are formed. First and / or second power supply control circuits for controlling power supply to the logic circuit group; first and second real power supply lines serving as power supply sources for the logic circuit group;
And / or a second pseudo power supply line, and connects the first pseudo power supply line to the first power supply terminal of the logic circuit group, and connects the first pseudo power supply line and the first real power supply line. The first power supply control circuit is connected in between, the second power supply line is directly connected to the second power supply terminal of the logic circuit group, or the second pseudo power supply line is connected and the second power supply line is connected. It is preferable to connect the second power supply control circuit between the pseudo power supply line and the second real power supply line.

[0018]

In the present invention, the second basic element having the high threshold voltage field effect transistor is provided for the cell array including the first basic cell having the low threshold voltage field effect transistor.
By arranging the cell arrays of basic cells adjacent to each other, it is possible to realize an MT-CMOS circuit using a high threshold voltage transistor and a low threshold voltage transistor without lowering the cell utilization rate in the gate cell array. .

[0019]

Embodiments of the present invention will be described below. FIG. 1 is a schematic diagram of an LSI chip 1 of the gate array integrated circuit of the first embodiment. Reference numeral 2 is a first basic cell, which is composed of a low threshold voltage MOS transistor. Reference numeral 3 is a second basic cell, which is composed of a high threshold MOS transistor. The first basic cells 2 are arranged in a matrix to form cell arrays 2A, 2B, 2C. Cell arrays (cell arrays) 3A, 3B, 3C and 3D each including a second basic cell 3 are arranged adjacent to each of the cell arrays 2A, 2B and 2C. An input / output buffer cell row 4 for interfacing with the outside is arranged in the peripheral portion of the LSI chip 1.

FIG. 2 is a diagram showing the first basic cell 2. Q
1, Q2 is a P-channel type MOS transistor, Q
Reference numerals 3 and Q4 are N-channel type MOS transistors, and all the threshold voltages are low level. For example,
The PMOS transistors Q1 and Q2 have about -0.2V, N
The MOS transistors Q3 and Q4 may be set to about 0.2V.

Also in this case, since the example in which the transistor is formed in the P-type substrate has been described, the P-channel MOS transistors Q1 and Q2 are formed in the n-well 201.
Reference numeral 202 is ap ⁺ region that functions as a source or drain of a P-channel MOS transistor, 203 is an n ⁺ region that functions as a source or drain of an N-channel MOS transistor, and 204 is a gate electrode.

FIG. 3 is a diagram showing the second basic cell 3. QH
1, QH2 are P-channel type MOS transistors, and the threshold voltage is high level, for example, −0.
It may be set to about 7V.

Also in this case, since the example in which the transistor is formed in the P-type substrate has been described, the P-channel MOS transistors QH1 and QH2 are formed in the n-well 301. 302 is a p ⁺ region that functions as the source or drain of the P-channel MOS transistor, and 303 is a gate electrode.

As described above, one LSI chip 1 is prepared in advance.
A low threshold voltage transistor portion and a high threshold voltage transistor portion are fixedly formed in the inside to form a high threshold voltage transistor and a low threshold voltage transistor. A gate array type integrated circuit corresponding to the MT-CMOS circuit technology can be realized.

FIG. 4 is a diagram showing an example of connection of a portion A surrounded by a circle in FIG. Here, the first basic cell 2 is the NAND
Consider forming a gate to form an MT-CMOS circuit. In FIG. 4, A1 'and A2' are first logic circuits (N
AND gate), Y'is an output terminal, A1 and A2 are input terminals of the second logic circuit (NAND gate), and Y is an output terminal. Q1 ', Q2', Q1, Q
2 is a P-channel MOS transistor in the first basic cell 2 and Q3 ', Q4', Q3 and Q4 are N-channel MOS transistors in the first basic cell 2, respectively. It is a thing. QH
1 and QH2 are both P channels M in the second basic cell 3.
OS transistors, which are of high threshold voltage. Black circles indicate source, drain,
Alternatively, it indicates the contact position to the gate electrode. The thick solid line indicates the first layer wiring. Reference numeral 5 is a second-layer wiring (shown by a dotted line) of the high-potential actual power supply line VDD, and 6 is the second-layer wirings 5 and 1.
It is a through hole between the layer wiring.

FIG. 5 is a circuit diagram showing an equivalent circuit of the configuration of FIG. The first and second logic circuits 7 and 7'composed of the first basic cell 2 are connected between the high potential pseudo power supply line VDDV and the low potential real power supply line VSS, and the high potential pseudo power supply line V
The power supply control circuit 8 including the second basic cell 3 is connected between the DDV and the high-potential actual power supply line VDD. Here, the power supply control circuit 8 is composed of a transfer gate formed by connecting P-channel MOS transistors QH1 and QH2 in parallel, and conduction / cutoff thereof is controlled by a sleep signal SL. When the sleep signal SL has a low potential, it conducts to supply power, and when the sleep signal SL has a high potential, cuts off to stop power supply. In this way, the first basic cell 2 constitutes the first and second logic circuits 7 and 7 ′, and the second basic cell 3 constitutes the power supply control circuit 8.

FIG. 6 is a diagram showing an outline of the LSI chip 1 of the second embodiment. In this arrangement, one cell array 2D composed of the first basic cells 2 is arranged at the center, and second cell arrays 2D are arranged at the left and right ends thereof.
It is an example in which cell columns (cell arrays) 3A and 3D each including a basic cell 3 are provided. Others are the same as those of the first embodiment shown in FIG.

FIG. 7 is a diagram showing the outline of the LSI chip 1 of the third embodiment. Similar to that shown in FIG. 6, one cell array 2E made up of the first basic cells 2 is arranged at the center, but two cell rows (cell array) 3E made up of the second basic cells 3 are arranged at the left and right ends of the cell array 2E. It is an example in which 3F is provided. Others are the same as those of the first embodiment shown in FIG.
The cell rows 3E and 3F may be three or more cell rows.

In this case, more high threshold voltage transistors can be used. Specifically, in the circuit of FIG. 5, a high threshold voltage P-channel transistor QH
Since three or more of 1 and QH2 can be connected in parallel, the size of the transistor can be effectively increased. in this way,
If the size of the high threshold voltage transistors QH1 and QH2 is increased, the capability of supplying current to the high potential pseudo power supply line VDDV is improved, so that the MT-CMOS circuit can operate at higher speed.

FIG. 8 is a schematic diagram of the LSI chip 1 of the fourth embodiment. Here, the cell columns (cell arrays) 3G and 3H formed by the second basic cells 3 formed of high threshold voltage transistors are arranged in the cell array 2 formed by the first basic cells 2.
It is arranged adjacent to the upper and lower ends of F.

FIG. 9 is an equivalent circuit diagram of a portion B surrounded by a circle in FIG. As shown in FIG. 9, the MT-CMOS circuit can be configured even if the cell column 3G formed by the second basic cells 3 is arranged adjacent to the upper portion of the cell array 2F formed by the first basic cells 2. The same can be said if it is arranged adjacent to the lower part.
Although not shown, the second basic cell 3 can be arranged adjacent to not only the end portion but also the central portion.

In each of the above embodiments, only the second basic cell 3 is constituted by the P-channel MOS transistor. However, conversely, the N-channel MO of high threshold voltage is used.
It is also possible to use only the S transistor. At this time, a low potential pseudo power supply is provided in place of the high potential pseudo power supply line VDDV, and the power supply terminal on the high potential side of the logic circuit group including the transistors of the first basic cell 2 is connected to the high potential real power supply line VD.
Connected to D, the power supply terminal on the low potential side is connected to the low potential pseudo power supply line, and the low potential pseudo power supply line and the low potential real power supply line VSS
A power supply control circuit composed of a high threshold voltage N-channel MOS transistor of the second basic cell is connected between and.
Then, the inverted signal of the sleep signal SL is applied to the gate of the N-channel MOS transistor of the power supply control circuit.

The second basic cell 3 has a structure in which a P-channel MOS transistor having a high threshold voltage and an N-channel MOS transistor having a high threshold voltage are mixed (the same structure as the first basic cell 2). It can also be taken.
At this time, the high-potential pseudo power supply line VDDV and the low-potential pseudo power supply are provided, and the power supply terminal on the high potential side of the logic circuit group including the transistors of the first basic cell 2 is connected to the high-potential pseudo power supply line VD.
The low-potential-side power supply terminal is connected to the DV and the low-potential pseudo-power supply line is connected, and the high threshold voltage P of the second basic cell is set between the high-potential real power supply line VDD and the high-potential pseudo power supply line VDDV. A power supply control circuit including a channel MOS transistor is connected, and a power supply control circuit including an N-channel MOS transistor having a high threshold voltage of the second basic cell is connected between the low potential real power supply line VSS and the low potential pseudo power supply line. Connecting. Then, the sleep signal SL is supplied to the gate of the P-channel MOS transistor of the power supply control circuit including the P-channel MOS transistor, and the N-channel M of the power supply control circuit including the N-channel MOS transistor is included.
An inverted signal of the sleep signal SL is applied to the gate of the OS transistor.

As for the circuit form of the power supply control circuit, the transfer gate form is shown in the present embodiment, but it is not limited to this form. That is, this power supply control circuit is based on the existing circuit design method.
It can take any conceivable circuit form.

[0035]

As described above, according to the present invention, the second basic cell having the field effect transistor having the high threshold voltage is different from the cell array including the first basic cell having the field effect transistor having the low threshold voltage. Since the cell arrays composed of 2 are arranged adjacent to each other, an MT-CMOS circuit using a high threshold voltage transistor and a low threshold voltage transistor can be realized without lowering the cell utilization rate on one LSI chip. .

This MT-CMOS circuit can be realized by using the first basic cell as a logic circuit group and the second basic cell as a power supply control circuit.

[Brief description of drawings]

FIG. 1 is a gate array LSI according to a first embodiment of the present invention.
It is a schematic diagram of a chip.

FIG. 2 is an explanatory diagram of a first basic cell according to the first embodiment.

FIG. 3 is an explanatory diagram of a second basic cell of the first embodiment.

FIG. 4 is an explanatory diagram of a cell showing a connection example of a portion A of FIG.

5 is a circuit diagram of an equivalent circuit of the cell shown in FIG.

FIG. 6 is a schematic view of an LSI chip of a gate array of the second embodiment.

FIG. 7 is a schematic view of an LSI chip of a gate array of the third embodiment.

FIG. 8 is a schematic diagram of an LSI chip of a gate array of a fourth embodiment.

9 is a circuit diagram of an equivalent circuit of a portion B in FIG.

FIG. 10 is a schematic diagram of a conventional gate array LSI chip.

11 is an explanatory diagram of a basic cell of FIG.

FIG. 12 is a 2-input NAN using the basic cell of FIG.
It is explanatory drawing which shows the connection example of D gate.

13 is a circuit diagram of the equivalent circuit of FIG.

FIG. 14 is a circuit diagram of MT-CMOS circuit technology.

[Explanation of symbols]

1: LSI chip 2: First basic cell, 2A, 2B, 2C, 2D, 2E, 2
F: cell array, 201: n-well, 202: p ⁺ region, 203: n ⁺ region, 204: gate electrode 3: second basic cell 3A, 3B, 3C, 3D, 3E, 3
F: 3G, 3H: Cell column (cell array), 301: n-well, 302: p ⁺ region, 303: gate electrode 4: input / output buffer cell column 5: second layer wiring 6: through hole 7, 7 ': logic Circuit 8: Power supply control circuit 11: LSI chip 12: Basic cell, 121: n well, 122: p ⁺ region, 123: n ⁺ region, 124: gate electrode, 12A:
Cell array 13: input / output buffer cell column 14: logic circuits Q1 to Q4, Q1 'to Q4', Q11 to Q14, Q21
-Q24: MOS transistors of low threshold voltage QH1, QH2, QH11: P-channel MOS transistors of high threshold VDD: High potential real power line VDDV: High potential pseudo power line VSS: Low potential real power line

Claims (3)

[Claims] 1. A second basic cell composed of a first basic cell composed of a field effect transistor and a field effect transistor having a threshold voltage absolute value higher than that of the field effect transistor composing the first basic cell. The first basic cell forms at least one cell array, and the second basic cell forms at least one other cell array. A gate array type integrated circuit characterized in that a cell array composed of the second basic cell is adjacently arranged at one end, both left and right ends, both upper and lower ends, left and right upper and lower ends, or inside. 2. A logic circuit group is formed by the first basic cell,
2. The gate array type integrated circuit according to claim 1, wherein a power supply control circuit for controlling power supply to the logic circuit group is formed by the second basic cell. 3. A logic circuit group formed of transistors forming the first basic cell and having first and second power supply terminals, and a transistor forming the second basic cell,
First and / or second power supply control circuits for controlling power supply to the logic circuit group, first and second actual power supply lines serving as power supply sources to the logic circuit group, and first and / or Two pseudo power supply lines, the first pseudo power supply line is connected to the first power supply terminal of the logic circuit group, and the first pseudo power supply line and the first pseudo power supply line are connected to each other.
The first power supply control circuit is connected to an actual power supply line, the second power supply line is directly connected to the second power supply terminal of the logic circuit group, or the second pseudo power supply line is connected. The gate array integrated circuit according to claim 1, wherein the second power supply control circuit is connected between the second pseudo power supply line and the second real power supply line.