JP3863267B2 - Semiconductor integrated circuit, macro cell, basic cell and transistor array - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit capable of high-speed operation at a low voltage, a master slice type macro cell for forming the semiconductor integrated circuit, a basic cell for forming the macro cell, and the basic cells arranged in a matrix. The present invention relates to a transistor array having a configuration.
[0002]
[Prior art]
In recent years, high-speed operation of semiconductor integrated circuits at low voltage has been promoted. As a semiconductor integrated circuit capable of high-speed operation at a low voltage, there is an MT-CMOS (Multi-Threshold CMOS) circuit.
[0003]
The MT-CMOS circuit includes a low-threshold MOS transistor capable of high-speed operation with a large leakage current during non-operation and a high-threshold MOS transistor with a low operation speed but low leakage current during non-operation. It is a circuit formed by using.
[0004]
For example, as an MT-CMOS circuit, a CMOS logic circuit is formed using a low-threshold MOS transistor, and a power supply control circuit is formed using a high-threshold MOS transistor in a path for supplying current to the CMOS logic circuit. There is something that provided.
[0005]
More specifically, as an MT-CMOS circuit, a CMOS logic circuit formed by using a low threshold PMOS transistor and a low threshold NMOS transistor between a high potential power line and a low potential power line. And connect a power control circuit on the high potential side formed using a high-threshold PMOS transistor between the high potential power supply line and the high potential power supply, and connect between the low potential power supply line and the low potential power supply. There is a configuration in which a low-potential side power supply control circuit formed by using a high-threshold NMOS transistor is connected.
[0006]
In such an MT-CMOS circuit, the CMOS logic circuit is formed using a low-threshold MOS transistor, so that high-speed operation can be realized at a low voltage. In addition, since the power supply control circuit formed using the high threshold MOS transistor is provided in the path for supplying current to the CMOS logic circuit, the leakage current from the CMOS logic circuit can be reduced during non-operation. .
[0007]
In FIG. 7, for example, a CMOS logic circuit is composed of a two-input NAND circuit and an inverter circuit, a high-potential-side power supply control circuit is composed of one high-threshold PMOS transistor, and a low-potential-side power supply control circuit is high. It is a circuit diagram of an MT-CMOS circuit composed of one NMOS transistor having a threshold value. In FIG. 7, 101 is a high potential power line, 102 is a low potential power line, 103 is a two-input NAND circuit connected between the high potential power line 101 and the low potential power line 102, and 104 is a high potential power line 101. , An inverter circuit connected between the low-potential power supply line 102, 105 is a high-potential power supply (VDD), 106 is a low-potential power supply (GND), and 107 is between the high-potential power supply line 101 and the high-potential power supply 105. A power control PMOS transistor connected to a high threshold (for example, the absolute value of the threshold is about 0.7 V; the same applies hereinafter) 108 is connected between the low potential power line 102 and the low potential power source 106. This is a high-threshold power supply control NMOS transistor. A power control active signal is input to the gate of the power control PMOS transistor 107, and a complementary signal (hereinafter referred to as an active bar signal) is input to the gate of the power control NMOS transistor.
[0008]
In the two-input NAND circuit 103, the first and second PMOS transistors 109 and 110 have low threshold values (for example, the absolute value of the threshold value is about 0.2 V; the same applies hereinafter), and the first and second PMOS transistors 111 and 112 have low values. The first and second NMOS transistors have threshold values.
[0009]
In the inverter circuit 104, reference numeral 113 denotes a low-threshold third PMOS transistor, and reference numeral 114 denotes a low-threshold third NMOS transistor.
[0010]
FIG. 8 is a block diagram of a conventional semiconductor integrated circuit comprising an MT-CMOS circuit. In FIG. 8, 121 is a semiconductor substrate, 122 is an internal region in which an MT-CMOS circuit is formed, 123 is a peripheral region in which an input / output buffer cell is formed, and 124 is a low threshold value in the internal region 122. The low threshold MOS transistor region in which the MOS transistor is formed, 125 is the high threshold MOS transistor region in which the high threshold MOS transistor is formed in the internal region 122, and 126 is the low threshold In the MOS transistor region 124, a macro cell formed using a low threshold MOS transistor, and in the high threshold MOS transistor region 125, a macro cell formed using a high threshold MOS transistor. MOS transistor circuit 128 is an inter-cell wiring connecting the macro cells 126, 12 Is a region between lines connecting the macrocell 126 and the high-threshold MOS transistor circuit 127.
[0011]
In this case, a CMOS logic circuit is formed by connecting the macro cells 126 with inter-cell wiring 128, and a high potential side MOS transistor circuit 127 is used to form a high potential side and a low potential side power supply control circuit. 126 and a high threshold MOS transistor circuit 127 are connected by an inter-region wiring 129 to form an MT-CMOS circuit. However, a CMOS logic circuit may be formed using one macro cell.
[0012]
FIG. 9 is a configuration diagram of a conventional semiconductor integrated circuit comprising an MT-CMOS circuit disclosed in Japanese Patent Laid-Open No. 8-18021. In FIG. 9, 131 is a semiconductor substrate, 132 is an internal region where an MT-CMOS circuit is formed, 133 is a peripheral region where an input / output buffer cell 133a is formed, and 134 is a low threshold of the internal region 132. Low threshold MOS transistor region in which basic cells 134a formed using value MOS transistors are arranged in a matrix, 135 is formed using a high threshold MOS transistor in internal region 132 This is a high threshold MOS transistor region in which basic cells 135a are arranged in a line or matrix.
[0013]
In this case as well, a CMOS logic circuit is formed by connecting the macrocells formed by using the low threshold MOS transistors in the low threshold MOS transistor region 134 by inter-cell wiring, as in the above case. In the high threshold MOS transistor region 135, a high threshold MOS transistor circuit formed by using a high threshold MOS transistor is used to form a power control circuit on the high potential side and the low potential side. An MT-CMOS circuit is formed by connecting the high threshold MOS transistor circuit with inter-region wiring. However, a CMOS logic circuit may be formed using one macro cell.
[0014]
Hereinafter, as a conventional semiconductor integrated circuit composed of an MT-CMOS circuit, a CMOS logic circuit is formed using one macro cell, and a power control circuit on the high potential side and the low potential side uses a high threshold MOS transistor circuit. The CMOS logic circuit is composed of a two-input NAND circuit, the high-potential-side power supply control circuit is composed of a high-threshold PMOS transistor, and the low-potential-side power supply control circuit is composed of a high-threshold NMOS transistor. A case where a circuit (a circuit corresponding to an X portion surrounded by a square in FIG. 7) is formed will be described.
[0015]
FIG. 10 is a configuration diagram of a conventional macro cell. In FIG. 10, 141 and 142 are low threshold first and second PMOS transistors, 143 and 144 are low threshold first and second NMOS transistors, and 145 and 146 are first and second PMOS transistors. Gate electrodes of the PMOS transistors 141 and 142, 147 and 148 are gate electrodes of the first and second NMOS transistors 143 and 144, and 149 is a diffusion region functioning as a source or drain of the first and second PMOS transistors 141 and 142. , 150 is a diffusion region functioning as the source or drain of the first and second NMOS transistors 143 and 144, 151 is a high potential power line, 152 is a low potential power line, and 153 to 158 are first to sixth conductivity. A wiring 159 is a via hole. One input signal to the two-input NAND circuit is input to the first conductive wiring 153, and the other input signal to the two-input NAND circuit is input to the second conductive wiring 154. The output signal from the 2-input NAND circuit is output to the conductive wiring 155. A, B, and Y in FIG. 10 correspond to A, B, and Y in FIG. In FIG. 10, wirings formed in the upper layers of the first to sixth conductive wirings 153 to 158 are not shown in order to simplify the drawing.
[0016]
FIG. 11 is a block diagram of a conventional high threshold MOS transistor circuit. In FIG. 11, 161 is a high threshold power control PMOS transistor, 162 is a high threshold non-use PMOS transistor, 163 is a high threshold power control NMOS transistor, and 164 is a high threshold non-use transistor. The NMOS transistor used, 165 is the gate electrode of the PMOS transistor 161 for power control, 166 is the gate electrode of the non-use PMOS transistor 162, 167 is the gate electrode of the NMOS transistor 163 for power control, 168 is the gate electrode of the non-use PMOS transistor 164, 169 is a diffusion region functioning as a source or drain of the power control PMOS transistor 161, 170 is a diffusion region functioning as a source or drain of the power control NMOS transistor 163, 171 is a power supply line connected to a high potential power source, 172 Is low Position supply line connected to the power supply, 173-178 the seventh to twelfth conductive wire, 179 is a via hole. The seventh conductive wiring 173 receives a power control Active signal to the gate electrode 165 of the power control PMOS transistor 161, and the eighth conductive wiring 174 receives the gate electrode 167 of the power control NMOS transistor 163. The active bar signal is input. The ninth conductive wiring 175 is connected to the high potential power supply line 151 in FIG. 10, and the tenth conductive wiring 176 is connected to the low potential power supply line 152 in FIG. The ninth and tenth conductive wirings 175 and 176 correspond to the inter-region wiring 129 in FIG. Note that FIG. 11 does not show the wirings formed in the upper layers of the seventh to twelfth conductive wirings 173 to 178 for the sake of simplicity.
[0017]
Next, the operation of the MT-CMOS circuit will be described with reference to FIG.
The MT-CMOS circuit has two operation modes, normal operation and non-operation.
[0018]
During normal operation, the Active signal is set to “H” and the Active bar signal is set to “L”. As a result, the power control PMOS transistor 107 and the power control NMOS transistor 108 become conductive, the high potential power line 101 is biased to the same potential as the high potential power source 105, and the low potential power line 102 is equipotential to the low potential power source 106. The power is supplied to the 2-input NAND circuit 103 and the inverter circuit 104. At this time, the 2-input NAND circuit 103 and the inverter circuit 104 operate in the same manner as a normal CMOS circuit.
[0019]
During non-operation, the Active signal is set to “L” and the Active bar signal is set to “H”. As a result, the power supply control PMOS transistor 107 and the power supply control NMOS transistor 108 become non-conductive, the high potential power supply line 101 and the low potential power supply line 102 are in a floating state, and the power supply to the 2-input NAND circuit 103 and the inverter circuit 104 is not supplied. Supply is stopped. At this time, the leakage current from the 2-input NAND circuit 103 and the inverter circuit 104 is cut.
[0020]
[Problems to be solved by the invention]
Since the conventional semiconductor integrated circuit is configured as described above, a CMOS logic circuit formed using a low threshold MOS transistor and a power supply control circuit formed using a high threshold MOS transistor The wiring connecting the two becomes longer. That is, the resistance of the wiring connecting the CMOS logic circuit and the power supply control circuit is increased. Therefore, there is a problem that the potential of the power supplied to the CMOS logic circuit via the power control circuit is lowered, causing the semiconductor integrated circuit to malfunction.
[0021]
The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor integrated circuit which does not cause a malfunction due to the wiring length and can operate at a high speed with a low voltage.
[0022]
Another object of the present invention is to obtain a master slice type macro cell for forming the semiconductor integrated circuit.
[0023]
A further object of the present invention is to obtain a basic cell for forming this macro cell.
[0024]
A further object of the present invention is to obtain a transistor array having a configuration in which the basic cells are arranged in a matrix.
[0030]
[Means for Solving the Problems]
  The transistor array according to the present invention includes one or more high-threshold PMOS transistors having a threshold value higher than that of the low-threshold MOS transistors, which are sequentially arranged with the gate electrodes aligned in the row direction. A basic cell having a configuration in which a plurality of transistor groups including a plurality of low-threshold MOS transistors and one or a plurality of high-threshold NMOS transistors having a threshold value higher than that of the low-threshold MOS transistors are arranged in the column direction. The high threshold PMOS transistor of one basic cell of the two basic cells adjacent in the row direction and the high threshold PMOS transistor of the other basic cell face each other or are adjacent in the row direction High threshold NMOS transistor of one basic cell and high threshold NM of the other basic cell of two basic cells And the S transistor those constructed by arranging in a matrix so as to face.
[0034]
  A semiconductor integrated circuit according to the present invention includes a low threshold Mth MOS transistor and the Mth MOS transistor.And the Mth MOS transistor having the same threshold asA macro cell formed using a low threshold Nth MOS transistor having a larger gate length, a CMOS logic circuit formed using an Mth MOS transistor, and a power control circuit serving as an Nth MOS transistor It is formed using a transistor.
[0035]
  The macro cell according to the present invention includes an Mth MOS transistor having a low threshold value and the Mth MOS transistor.And the Mth MOS transistor having the same threshold asThe Nth MOS transistor having a larger gate length and a low threshold is formed, the CMOS logic circuit is formed using the Mth MOS transistor, and the power supply control circuit is formed using the Nth MOS transistor. It is what is done.
[0036]
  The basic cell according to the present invention includes an Mth MOS transistor having a low threshold value and the Mth MOS transistor.And the Mth MOS transistor having the same threshold asThe CMOS logic circuit is formed using the Mth MOS transistor, and the power supply control circuit is formed using the Nth MOS transistor. Is.
[0037]
The basic cell according to the present invention includes one or a plurality of Nth MOS transistors, one or a plurality of Mth MOS transistors, and one or a plurality of Nth Nth transistors, which are sequentially arranged with the gate electrodes aligned in the row direction. A plurality of transistor groups composed of MOS transistors are arranged in the column direction.
[0038]
  The transistor array according to the present invention is an M-th MOS transistor arranged in order with the gate electrodes aligned in the row direction.And the Mth MOS transistor having the same threshold asOne or more low threshold Nth PMOS transistors having a larger gate length, one or more low threshold Mth MOS transistors, and Mth MOS transistorsAnd the Mth MOS transistor having the same threshold asA basic cell having a configuration in which a plurality of transistor groups each including one or a plurality of low threshold Nth NMOS transistors having a larger gate length are arranged in the column direction is one of two basic cells adjacent in the row direction. The Nth PMOS transistor of the basic cell and the Nth NMOS transistor of the other basic cell are arranged in a matrix so as to face each other, and a CMOS logic circuit is formed using the Mth MOS transistor. The control circuit is formed using an Nth PMOS transistor and an Nth NMOS transistor.
[0039]
  The transistor array according to the present invention is an M-th MOS transistor arranged in order with the gate electrodes aligned in the row direction.And the Mth MOS transistor having the same threshold asOne or more low threshold Nth PMOS transistors having a larger gate length, one or more low threshold Mth MOS transistors, and Mth MOS transistorsAnd the Mth MOS transistor having the same threshold asA basic cell having a configuration in which a plurality of transistor groups each including one or a plurality of Nth low threshold NMOS transistors having a larger gate length are arranged in the column direction is one of two basic cells adjacent in the row direction. The Nth PMOS transistor of the basic cell and the Nth PMOS transistor of the other basic cell face each other, or the Nth NMOS transistor and the other of the two basic cells adjacent in the row direction The basic cell is arranged in a matrix so as to face the Nth NMOS transistor of the basic cell, the CMOS logic circuit is formed using the Mth MOS transistor, and the power control circuit is the Nth PMOS transistor and / or It is formed using an Nth NMOS transistor.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below.
Embodiment 1 FIG.
In the first embodiment of the present invention, the CMOS logic circuit is formed using a low threshold MOS transistor that has a large leakage current when not operating but can operate at high speed, and is used to supply current to the CMOS logic circuit. A semiconductor integrated circuit provided with a power supply control circuit formed using a high-threshold MOS transistor having a low operating speed but low leakage current during non-operation will be described.
[0041]
1 is a configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. In FIG. 1, 1 is a semiconductor substrate, 2 is an internal region where a semiconductor integrated circuit is formed, 3 is a peripheral region where an input / output buffer cell is formed, and 4 is a low threshold MOS in the internal region 2 Macrocells 5 formed by using transistors and high-threshold MOS transistors are inter-cell wirings connecting the macrocells 4. In the internal region 2, a high threshold MOS transistor and a low threshold MOS transistor are formed.
[0042]
In this case, by connecting the macro cells 4 with inter-cell wiring 5, a CMOS logic circuit formed using a low threshold MOS transistor and a high potential formed using a high threshold MOS transistor. Side and low potential side power supply control circuits, and a semiconductor integrated circuit formed using a CMOS logic circuit and a power supply control circuit are formed. However, in some cases, a single macrocell forms a CMOS logic circuit and a high-potential side and low-potential-side power supply control circuit. That is, a semiconductor integrated circuit may be formed by one macro cell.
[0043]
As described above, according to the first embodiment, the semiconductor integrated circuit is composed of the macro cell formed using the low threshold MOS transistor and the high threshold MOS transistor. The wiring connecting the CMOS logic circuit formed using the threshold MOS transistor and the power supply control circuit formed using the high threshold MOS transistor is shorter than before, and the semiconductor integrated circuit malfunctions. The effect of reducing the risk of occurrence is obtained.
[0044]
Embodiment 2. FIG.
In the second embodiment of the present invention and the third embodiment of the present invention to be described later, as a semiconductor integrated circuit of the first embodiment, the CMOS logic circuit and the power control circuits on the high potential side and the low potential side have one macro cell. The CMOS logic circuit is composed of a two-input NAND circuit, the high potential side current control circuit is composed of one high threshold PMOS transistor, and the low potential side current control circuit is a high threshold NMOS. A macro cell in the case where a circuit composed of one transistor (a circuit corresponding to an X portion surrounded by a square in FIG. 7) is formed will be described.
[0045]
FIG. 2 is a block diagram of a macro cell according to Embodiment 2 of the present invention. In FIG. 2, reference numerals 11 and 12 denote low threshold first and second PMOS transistors (low threshold MOS transistors), and reference numerals 13 and 14 denote low threshold first and second NMOS transistors (low threshold MOS transistors). Threshold MOS transistors), 15 and 16 are the gate electrodes of the first and second PMOS transistors 11 and 12, 17 and 18 are the gate electrodes of the first and second NMOS transistors 13 and 14, and 19 is the first , A diffusion region functioning as a source or drain of the second PMOS transistors 11 and 12, and a diffusion region 20 functioning as a source or drain of the first and second NMOS transistors 13 and.
[0046]
Reference numeral 21 is a high threshold power control PMOS transistor (high threshold MOS transistor), 22 is a high threshold non-use PMOS transistor (high threshold MOS transistor), and 23 is a high threshold. Power supply control NMOS transistor (high threshold MOS transistor), 24 is a high threshold non-use NMOS transistor (high threshold MOS transistor), 25 is a gate electrode of the power control PMOS transistor 21, 26 is a gate electrode of the unused PMOS transistor 22, 27 is a gate electrode of the NMOS transistor 23 for power supply control, 28 is a gate electrode of the unused NMOS transistor 24, and 29 is a diffusion functioning as a source or drain of the PMOS transistor 21 for power supply control. The region 30 is a power control NMOS transistor 23. Source or diffused region serving as a drain, 31 is a power supply line connected to the high-potential power source, 32 is a power supply line that is connected to the low potential power source.
[0047]
Reference numerals 33 to 42 denote first to tenth conductive wirings, and 43 denotes a via hole. The first conductive wiring 33 connects the gate electrode 15 of the first PMOS transistor 11 and the gate electrode 17 of the first NMOS transistor 13. The second conductive wiring 34 connects the gate electrode 16 of the second PMOS transistor 12 and the gate electrode 18 of the second NMOS transistor 14. The third conductive wiring 35 is a diffusion region 19 that functions as the source or drain of the first and second PMOS transistors 11 and 12 and a diffusion region that functions as the source or drain of the first and second NMOS transistors 13 and 14. 20 is connected. The fourth conductive wiring 36 is connected to the gate electrode 25 of the power control PMOS transistor 21. The fifth conductive wiring 37 is connected to the gate electrode 27 of the power control NMOS transistor 23. The sixth and seventh conductive wirings 38 and 39 are a diffusion region 19 functioning as a source or drain of the first and second PMOS transistors 11 and 12 and a diffusion region functioning as a source or drain of the power control PMOS transistor 21. 29 is connected.
[0048]
The eighth conductive wiring 40 connects the diffusion region 20 functioning as the source or drain of the first and second NMOS transistors 13 and 14 and the diffusion region 30 functioning as the source or drain of the power supply control NMOS transistor 23. . The ninth conductive wiring 41 connects the diffusion region 29 functioning as the source or drain of the power control PMOS transistor 21 and the power supply line 31 connected to the high potential power supply. The tenth conductive wiring 42 connects the diffusion region 30 functioning as the source or drain of the power control NMOS transistor 23 and the power supply line 32 connected to the low potential power supply. One input signal to the two-input NAND circuit is input to the first conductive wiring 33, and the other input signal to the two-input NAND circuit is input to the second conductive wiring 34, so that the third conductive An output signal from the two-input NAND circuit is output to the conductive wiring 35, and an Active signal for power control to the gate electrode 25 of the power control PMOS transistor 21 is input to the fourth conductive wiring 36. The active bar signal to the gate electrode 27 of the power control NMOS transistor 23 is input to the conductive wiring 37. A, B, and Y in FIG. 2 correspond to A, B, and Y in FIG. In FIG. 2, wirings formed in the upper layers of the first to tenth conductive wirings 33 to 42 are not shown in order to simplify the drawing.
[0049]
In the macro cell according to the second embodiment of the present invention, a transistor comprising a low threshold PMOS transistor and a low threshold NMOS transistor arranged with the gate electrodes aligned in the row direction (Y direction in FIG. 2) Two pairs are arranged in the column direction (X direction in FIG. 2). That is, a transistor pair composed of the first PMOS transistor 11 and the first NMOS transistor 13 and a transistor pair composed of the second PMOS transistor 12 and the second NMOS transistor 14 are arranged in the column direction. Using these two transistor pairs, a CMOS logic circuit composed of a two-input NAND circuit is formed.
[0050]
Further, adjacent to the first and second PMOS transistors 11 and 12, the gate electrodes 15 and 16 of the first and second PMOS transistors 11 and 12 are aligned with the gate electrodes so that the high threshold PMOS is provided. Two transistors are arranged in the column direction. That is, the power control PMOS transistor 21 and the unused PMOS transistor 22 are arranged in the column direction. Using the power supply control PMOS transistor 21, a high potential side current control circuit composed of one high threshold PMOS transistor is formed.
[0051]
Further, adjacent to the first and second NMOS transistors 13 and 14, the gate electrodes 17 and 18 of the first and second NMOS transistors 13 and 14 are aligned with the gate electrode, so that the NMOS having a high threshold value is obtained. Two transistors are arranged in the column direction. That is, the power control NMOS transistor 23 and the non-use NMOS transistor 24 are arranged in the column direction. A power control NMOS transistor 23 is used to form a high potential side current control circuit composed of one high threshold PMOS transistor.
[0052]
As described above, according to the second embodiment, the macro cell is formed using the low threshold MOS transistor and the high threshold MOS transistor. A semiconductor integrated circuit that is less prone to malfunction because the wiring connecting the CMOS logic circuit formed using the power supply control circuit formed using a high-threshold MOS transistor is shorter than the conventional one. The effect which can be formed easily using is acquired.
[0053]
Embodiment 3 FIG.
FIG. 3 is a block diagram of a macro cell according to Embodiment 3 of the present invention. In FIG. 3, 51 is a high potential power line, 52 is a low potential power line, and 53 to 58 are 11th to 16th conductive lines. The eleventh and twelfth conductive wirings 53 and 54 connect the diffusion region 19 functioning as the source or drain of the first and second PMOS transistors 11 and 12 and the high potential power supply line 51. The thirteenth conductive wiring 55 connects the diffusion region 20 functioning as the source or drain of the first and second NMOS transistors 13 and 14 and the low potential power supply line 52. The fourteenth and fifteenth conductive wirings 56 and 57 connect the diffusion region 29 functioning as the source or drain of the power control PMOS transistor 21 and the high potential power supply line 51. The sixteenth conductive wiring 58 connects the diffusion region 30 functioning as the source or drain of the power control NMOS transistor 23 and the low potential power supply line 52. The constituent elements are the same as or equivalent to those shown with the same reference numerals in FIG.
[0054]
As described above, according to the third embodiment, since the macro cell is formed by using the low threshold MOS transistor and the high threshold MOS transistor, the same effect as in the second embodiment is obtained. Is obtained. Further, the high potential power supply line and the low potential power supply line are connected to the high potential power supply line and the low potential power supply line of another macro cell, respectively, thereby functioning as the source or drain of the first and second PMOS transistors 11 and 12. A wiring for connecting a diffusion region 19 and a diffusion region 29 functioning as a source or drain of the power control PMOS transistor 21 and a diffusion region 20 functioning as a source or drain of the first and second NMOS transistors 13 and 14 As a result, the impedance of the wiring in the part connecting the diffusion region 30 functioning as the source or drain of the power supply controlling NMOS transistor 23 is smaller than that in the first embodiment.
[0055]
Embodiment 4 FIG.
In the fourth embodiment of the present invention, a basic cell for forming the macro cell of the second and third embodiments will be described.
[0056]
FIG. 4 is a configuration diagram of a basic cell according to Embodiment 4 of the present invention. In FIG. 4, 61 and 62 are low threshold first and second PMOS transistors (low threshold MOS transistors), and 63 and 64 are low threshold first and second NMOS transistors (low threshold). Threshold MOS transistors), 65 and 66 are the gate electrodes of the first and second PMOS transistors 61 and 62, 67 and 68 are the gate electrodes of the first and second NMOS transistors 63 and 64, and 69 is the first electrode. , A diffusion region functioning as a source or drain of the second PMOS transistors 61 and 62, and a diffusion region 70 functioning as a source or drain of the first and second NMOS transistors 63 and 64.
[0057]
Reference numerals 71 and 72 denote high threshold third and fourth PMOS transistors (high threshold MOS transistors), and 73 and 74 denote high threshold third and fourth NMOS transistors (high threshold). 75 and 76 are gate electrodes of the third and fourth PMOS transistors 71 and 72, 77 and 78 are gate electrodes of the third and fourth NMOS transistors 73 and 74, and 79 is the third and third MOS transistors. A diffusion region 80 functions as a source or drain of the fourth PMOS transistors 71 and 72, and a diffusion region 80 functions as a source or drain of the third and fourth NMOS transistors 73 and 74.
[0058]
The basic cell according to the fourth embodiment of the present invention comprises a low threshold PMOS transistor and a low threshold NMOS transistor arranged with the gate electrodes aligned in the row direction (Y direction in FIG. 4). Two transistor pairs are arranged in the column direction (X direction in FIG. 4). That is, a transistor pair composed of the first PMOS transistor 61 and the first NMOS transistor 63 and a transistor pair composed of the second PMOS transistor 62 and the second NMOS transistor 64 are arranged in the column direction.
[0059]
Further, adjacent to the first and second PMOS transistors 61 and 62, the gate electrodes 65 and 66 of the first and second PMOS transistors 61 and 62 are aligned with the positions of the gate electrodes so that the high threshold PMOS is provided. Two transistors are arranged in the column direction. That is, the third PMOS transistor 71 and the fourth PMOS transistor 72 are arranged in the column direction.
[0060]
Further, adjacent to the first and second NMOS transistors 63 and 64, the gate electrodes 67 and 68 of the first and second NMOS transistors 63 and 64 are aligned with the gate electrode, so that the NMOS having a high threshold value is obtained. Two transistors are arranged in the column direction. That is, the third NMOS transistor 73 and the fourth NMOS transistor 74 are arranged in the column direction.
[0061]
In short, in the basic cell according to the fourth embodiment of the present invention, the high threshold PMOS transistor, the low threshold PMOS transistor, and the low threshold NMOS, which are sequentially arranged with the gate electrodes aligned in the row direction. Two transistor groups each including a transistor and a high-threshold NMOS transistor are arranged in the column direction. That is, a transistor group including a third PMOS transistor 71, a first PMOS transistor 61, a first NMOS transistor 63, and a third NMOS transistor 73, a fourth PMOS transistor 72, a second PMOS transistor 62, a second PMOS transistor 62, Transistor groups of the NMOS transistor 64 and the fourth NMOS transistor 74 are arranged in the column direction.
[0062]
As described above, according to the fourth embodiment, the basic cell is composed of the low threshold MOS transistor and the high threshold MOS transistor. A macro cell that can easily form a semiconductor integrated circuit that is less likely to cause malfunction because the wiring connecting the CMOS logic circuit formed and the power supply control circuit formed of a high-threshold MOS transistor is shorter than the conventional one. Thus, an effect that can be easily formed using this basic cell is obtained. Further, according to the fourth embodiment, the basic cell has one high-threshold MOS transistor, two low-threshold MOS transistors, and 1 Since two high-threshold MOS transistors are arranged in the column direction, two high-threshold MOS transistors are arranged in the column direction. In the case where the high threshold MOS transistor in the region arranged in (1) is not used, the effect that the region can be used as a wiring region is obtained.
[0063]
Embodiment 5. FIG.
In a fifth embodiment of the present invention and a sixth embodiment of the present invention described later, a transistor array having a configuration in which the basic cells of the fourth embodiment are arranged in a matrix will be described.
[0064]
5 is a block diagram of a transistor array according to a fifth embodiment of the present invention. In FIG. 5, reference numerals 81 to 84 denote first to fourth basic cells (basic cells). The components are the same as or equivalent to those shown in FIG. 4 with the same reference numerals, and detailed description thereof is omitted.
[0065]
In the transistor array according to the fifth embodiment of the present invention, the basic cell includes the high threshold PMOS transistor of one basic cell and the high threshold of the other basic cell of two basic cells adjacent in the row direction. The NMOS transistors are arranged in a matrix so as to face each other. That is, the first to fourth basic cells 81 to 84 include the third and fourth PMOS transistors 71 and 72 of the first basic cell 81 and the third and fourth NMOS transistors 73 of the second basic cell 82. , 74 are opposed to each other, and the third and fourth PMOS transistors 71, 72 of the third basic cell 83 are opposed to the third, fourth NMOS transistors 73, 74 of the fourth basic cell 84. They are arranged in a matrix.
[0066]
As described above, according to the fifth embodiment, the transistor array includes a basic cell, a high threshold PMOS transistor of one basic cell of two basic cells adjacent in the row direction, and the other basic cell. Power supply control formed using a high threshold PMOS transistor and a high threshold NMOS transistor because the cell is arranged in a matrix so as to face the high threshold NMOS transistor of the cell The semiconductor integrated circuit having a small area in which the circuits are efficiently arranged can be easily formed using this transistor array.
[0067]
Embodiment 6 FIG.
6 is a configuration diagram of a transistor array according to a sixth embodiment of the present invention. In FIG. 6, reference numerals 91 to 94 denote first to fourth basic cells (basic cells). The components are the same as or equivalent to those shown in FIG. 4 with the same reference numerals, and detailed description thereof is omitted.
[0068]
In the transistor array according to the sixth embodiment of the present invention, the basic cell includes a high threshold PMOS transistor of one basic cell and a high threshold of the other basic cell of two basic cells adjacent in the row direction. The PMOS transistors are arranged in a matrix so as to face each other. That is, the first to fourth basic cells 91 to 94 include the third and fourth PMOS transistors 71 and 72 of the first basic cell 91 and the third and fourth PMOS transistors 71 of the second basic cell 92. 72, and the third and fourth PMOS transistors 71 and 72 of the third basic cell 93 and the third and fourth PMOS transistors 71 and 72 of the fourth basic cell 94 are opposed to each other. They are arranged in a matrix.
[0069]
As described above, according to the sixth embodiment, the transistor array includes a basic cell, a high threshold PMOS transistor of one basic cell of two basic cells adjacent in the row direction, and the other basic cell. Since the cells are arranged in a matrix so as to face the high threshold PMOS transistors, the high threshold PMOS of one of the two basic cells adjacent in the row direction A small area semiconductor integrated circuit in which a transistor and a high-threshold PMOS transistor of the other basic cell are formed in the same well and the interval between two basic cells adjacent in the row direction is small can be easily obtained using this transistor array. The effect which can be formed is acquired.
[0070]
Embodiment 7 FIG.
In the seventh embodiment of the present invention, in the semiconductor integrated circuit of the first embodiment, the macro cell of the second and third embodiments, and the basic cell of the fourth embodiment, the high threshold MOS transistor is reduced. A case where the gate length is larger than that of the threshold MOS transistor will be described.
[0071]
In the MOS transistors having the same threshold value, the leakage current is smaller as the gate length is larger.
[0072]
Therefore, in the semiconductor integrated circuit of the first embodiment, when the gate voltage of the high threshold MOS transistor is larger than that of the low threshold MOS transistor, the same effect as in the first embodiment can be obtained and the non-operation The effect of reducing the leakage current of the semiconductor integrated circuit at that time can be obtained.
[0073]
Further, in the macrocells of the second and third embodiments, when the high threshold MOS transistor has a larger gate length than the low threshold MOS transistor, the same as in the second and third embodiments. In addition to the effect, it is possible to easily form a semiconductor integrated circuit with a small leakage current during non-operation using this macro cell.
[0074]
In the basic cell of the fourth embodiment, when the gate voltage of the high threshold MOS transistor is larger than that of the low threshold MOS transistor, the same effect as that of the fourth embodiment can be obtained and the non-operating state can be obtained. The macrocell capable of easily forming a semiconductor integrated circuit with a small leakage current is easily obtained using this basic cell.
[0075]
Embodiment 8 FIG.
In the eighth embodiment of the present invention, the semiconductor integrated circuit of the first embodiment, the macro cell of the second and third embodiments, the basic cell of the fourth embodiment, and the transistor array of the fifth and sixth embodiments. A case where another low threshold MOS transistor having a gate length larger than that of the low threshold MOS transistor is used instead of the high threshold MOS transistor will be described. Hereinafter, the low threshold MOS transistor used in the first to sixth embodiments is referred to as a low threshold Mth MOS transistor, and the high threshold used in the first to sixth embodiments. A low threshold MOS transistor used in place of the MOS transistor will be described as a low threshold Nth MOS transistor.
[0076]
In the MOS transistors having the same threshold value, the leakage current is smaller as the gate length is larger.
[0077]
Therefore, in the semiconductor integrated circuit of the first embodiment, instead of the high threshold MOS transistor, a low threshold Nth MOS transistor having a gate length larger than that of the low threshold Mth MOS transistor is used. In this case, the semiconductor integrated circuit is composed of a macro cell formed using a low threshold Mth MOS transistor and a low threshold Nth MOS transistor. The wiring connecting the CMOS logic circuit formed by using the power supply control circuit formed by using the Nth MOS transistor is shorter than the conventional one, and the effect of causing a malfunction of the semiconductor integrated circuit can be obtained. . In addition, the effect of reducing the leakage current of the semiconductor integrated circuit during non-operation can be obtained.
[0078]
Further, in the macrocells of the second and third embodiments, the low threshold Nth MOS whose gate length is larger than that of the low threshold Mth MOS transistor, instead of the high threshold MOS transistor. When the transistor is used, the macro cell is formed using the low threshold Mth MOS transistor and the low threshold Nth MOS transistor, and thus is formed using the Mth MOS transistor. A semiconductor integrated circuit which is less likely to cause malfunction because the wiring connecting the CMOS logic circuit and the power supply control circuit formed using the Nth MOS transistor is shorter than the conventional one is easily formed using this macro cell. The effect that can be obtained. In addition, it is possible to easily form a semiconductor integrated circuit with a small leakage current during non-operation using this macro cell.
[0079]
In the basic cell of the fourth embodiment, a low threshold Nth MOS transistor having a gate length larger than that of the low threshold Mth MOS transistor is used instead of the high threshold MOS transistor. In this case, since the basic cell is composed of the low threshold Mth MOS transistor and the low threshold Nth MOS transistor, the CMOS logic circuit formed of the Mth MOS transistor, A macro cell that can easily form a semiconductor integrated circuit that is less likely to cause malfunction due to a shorter wiring connecting to a power supply control circuit formed of an N MOS transistor than the conventional one is easily formed using this basic cell. The effect which can be done is acquired. In addition, the low cell Nth MOS transistor, the two low threshold Mth MOS transistors, and the low cell whose basic cells are arranged in order in the row direction with the gate electrodes aligned. Since two transistor groups of threshold Nth MOS transistors are arranged in the column direction, the Mth MOS transistor is arranged in the column direction when forming a macro cell using this basic cell. In the case where the Mth MOS transistor in the region that is being used is not used, there is an effect that that region can be used as a wiring region. Further, it is possible to easily form a macro cell that can easily form a semiconductor integrated circuit with a small leakage current during non-operation by using this basic cell. In addition, since it is not necessary to form a high-threshold MOS transistor, the number of masks used in forming the basic cell can be reduced, and the cost for forming the basic cell can be reduced.
[0080]
In the transistor array of the fifth embodiment, a low threshold Nth MOS transistor having a gate length larger than that of the low threshold Mth MOS transistor is used instead of the high threshold MOS transistor. In this case, the transistor array includes a basic cell, a low threshold Nth PMOS transistor of one basic cell of two basic cells adjacent in the row direction, and a low threshold N of the other basic cell. The power supply control circuit formed using the Nth PMOS transistor and the Nth NMOS transistor is efficiently arranged because it is arranged in a matrix so as to face the NMOS transistor. The semiconductor integrated circuit having an area can be easily formed using this transistor array.
[0081]
In the transistor array of the sixth embodiment, a low threshold Nth MOS transistor having a gate length larger than that of the low threshold Mth MOS transistor is used instead of the high threshold MOS transistor. In this case, the transistor array includes a basic cell, a low threshold Nth PMOS transistor of one basic cell of two basic cells adjacent in the row direction, and a low threshold N of the other basic cell. Since the first and second PMOS transistors are arranged in a matrix so as to face each other, the Nth PMOS transistor of one basic cell and the second basic cell of the two basic cells adjacent in the row direction are arranged. A small-area semiconductor integrated circuit in which N PMOS transistors are formed in the same well and the interval between two basic cells adjacent to each other in the row direction is small. Effect which can be easily formed by using a Sutaarei is obtained.
[0087]
【The invention's effect】
  According to the present invention, one or a plurality of high-threshold PMOS transistors having a threshold value higher than that of a low-threshold MOS transistor, in which the transistor array is sequentially arranged with the gate electrodes aligned in the row direction, Basic structure in which a plurality of transistor groups including one or a plurality of low threshold MOS transistors and one or a plurality of high threshold NMOS transistors having a threshold higher than that of the low threshold MOS transistors are arranged in the column direction A cell has a high threshold PMOS transistor of one of the two basic cells adjacent to each other in the row direction and the high threshold PMOS transistor of the other basic cell face each other or in the row direction. The high threshold NMOS transistor of one basic cell and the high threshold of the other basic cell of two adjacent basic cells Since the MOS transistor is configured to be configured by arranging in a matrix so as to face the semiconductor integrated circuit having a small area, the effect is obtained that it can be easily formed by using the transistor array.
[0091]
  According to the present invention, a semiconductor integrated circuit is connected to a low threshold Mth MOS transistor.,This Mth MOS transistorAnd the Mth MOS transistor having the same threshold asA macro cell formed using a low threshold Nth MOS transistor having a larger gate length, a CMOS logic circuit formed using an Mth MOS transistor, and a power control circuit serving as an Nth MOS transistor Since it is configured to be formed using a transistor, a wiring connecting a CMOS logic circuit formed using an Mth MOS transistor and a power supply control circuit formed using an Nth MOS transistor has been conventionally used. There is an effect that the length of the semiconductor integrated circuit becomes shorter and the possibility of malfunction of the semiconductor integrated circuit is reduced. Further, there is an effect that the leakage current of the semiconductor integrated circuit is reduced during non-operation.
[0092]
  According to the present invention, a macro cell is connected to a low threshold Mth MOS transistor.,This Mth MOS transistorAnd the Mth MOS transistor having the same threshold asThe Nth MOS transistor having a larger gate length and a low threshold is formed, the CMOS logic circuit is formed using the Mth MOS transistor, and the power supply control circuit is formed using the Nth MOS transistor. Since the wiring connecting the CMOS logic circuit formed using the Mth MOS transistor and the power supply control circuit formed using the Nth MOS transistor is shorter than the conventional one, malfunction is caused. There is an effect that a semiconductor integrated circuit that is less likely to occur can be easily formed using this macro cell. Further, there is an effect that a semiconductor integrated circuit having a small leakage current during non-operation can be easily formed using the macro cell.
[0093]
  According to the present invention, the basic cell includes a low threshold Mth MOS transistor and the Mth MOS transistor.And the Mth MOS transistor having the same threshold asThe CMOS logic circuit is formed using the Mth MOS transistor, and the power supply control circuit is formed using the Nth MOS transistor. Since the wiring connecting the CMOS logic circuit formed of the Mth MOS transistor and the power supply control circuit formed of the Nth MOS transistor is shorter than the conventional semiconductor integrated circuit, the semiconductor integrated circuit is less likely to cause a malfunction. There is an effect that a macro cell capable of easily forming a circuit can be easily formed using the basic cell. Further, there is an effect that a macro cell capable of easily forming a semiconductor integrated circuit with a small leakage current during non-operation can be easily formed using the basic cell. In addition, since it is not necessary to form a high-threshold MOS transistor, the number of masks used for forming the basic cell can be reduced, and the cost for forming the basic cell can be reduced.
[0094]
According to the present invention, the basic cell is arranged in order in the row direction with the gate electrode aligned, and one or more Nth MOS transistors, one or more Mth MOS transistors, and one or more first MOS transistors. Since a plurality of transistor groups composed of N MOS transistors are arranged in the column direction, the Nth MOS transistor is arranged in the column direction when forming a macro cell using this basic cell. When the Nth MOS transistor in the region is not used, this region can be used as a wiring region.
[0095]
  According to the present invention, the Mth MOS transistor in which the transistor array is arranged in order in the row direction with the position of the gate electrode aligned.And the Mth MOS transistor having the same threshold asOne or more low threshold Nth PMOS transistors having a larger gate length, one or more low threshold Mth MOS transistors, and Mth MOS transistorsAnd the Mth MOS transistor having the same threshold asA basic cell having a configuration in which a plurality of transistor groups each including one or a plurality of low threshold Nth NMOS transistors having a larger gate length are arranged in the column direction is one of two basic cells adjacent in the row direction. The Nth PMOS transistor of the basic cell and the Nth NMOS transistor of the other basic cell are arranged in a matrix so as to face each other, and a CMOS logic circuit is formed using the Mth MOS transistor. Since the control circuit is configured to be formed using the Nth PMOS transistor and the Nth NMOS transistor, the power supply control circuit formed using the Nth PMOS transistor and the Nth NMOS transistor is efficiently used. A small area semiconductor integrated circuit can be easily formed using this transistor array. There is an effect that can.
[0096]
  According to the present invention, the Mth MOS transistor is arranged in order with the position of the gate electrode aligned in the row direction.And the Mth MOS transistor having the same threshold asOne or more low threshold Nth PMOS transistors having a larger gate length, one or more low threshold Mth MOS transistors, and Mth MOS transistorsAnd the Mth MOS transistor having the same threshold asA basic cell having a configuration in which a plurality of transistor groups each including one or a plurality of low threshold Nth NMOS transistors having a larger gate length are arranged in the column direction is one of two basic cells adjacent in the row direction. The Nth PMOS transistor of the basic cell and the Nth PMOS transistor of the other basic cell face each other, or the Nth NMOS transistor and the other of the two basic cells adjacent in the row direction The basic cell is arranged in a matrix so as to face the Nth NMOS transistor of the basic cell, the CMOS logic circuit is formed using the Mth MOS transistor, and the power control circuit is the Nth PMOS transistor and / or Two basic cells adjacent to each other in the row direction because they are formed using the Nth NMOS transistor A small-area semiconductor integrated circuit in which the Nth PMOS transistor of one basic cell and the Nth PMOS transistor of the other basic cell are formed in the same well and the interval between two basic cells adjacent in the row direction is small. There is an effect that the transistor array can be easily formed.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.
FIG. 2 is a configuration diagram of a macro cell according to a second embodiment of the present invention.
FIG. 3 is a configuration diagram of a macro cell according to a third embodiment of the present invention.
FIG. 4 is a configuration diagram of a basic cell according to a fourth embodiment of the present invention.
FIG. 5 is a configuration diagram of a transistor array according to a fifth embodiment of the present invention.
FIG. 6 is a configuration diagram of a transistor array according to a sixth embodiment of the present invention.
FIG. 7 is a circuit diagram of an MT-CMOS circuit.
FIG. 8 is a configuration diagram of a conventional semiconductor integrated circuit.
FIG. 9 is a configuration diagram of a conventional semiconductor integrated circuit disclosed in Japanese Patent Application Laid-Open No. 8-18021.
FIG. 10 is a configuration diagram of a conventional macro cell.
FIG. 11 is a configuration diagram of a conventional high threshold MOS transistor circuit.
[Explanation of symbols]
4 macrocell, 11, 61 low threshold first PMOS transistor (low threshold MOS transistor), 12, 62 low threshold second PMOS transistor (low threshold MOS transistor), 13 63 Low threshold first NMOS transistor (low threshold MOS transistor) 14,64 Low threshold second NMOS transistor (low threshold MOS transistor), 21 High threshold PMOS transistor for power control (high threshold MOS transistor), 22 High threshold non-use PMOS transistor (high threshold MOS transistor), 23 High threshold power control NMOS transistor (high Threshold MOS transistor), 24 high threshold non-use NMOS transistor (high threshold MOS) 71, third PMOS transistor with high threshold (high threshold MOS transistor), 72 fourth PMOS transistor with high threshold (high threshold MOS transistor), 73 high threshold Third NMOS transistor (high threshold MOS transistor), 74 high threshold fourth NMOS transistor (high threshold MOS transistor), 81, 91 first basic cell (basic cell), 82, 92 Second basic cell (basic cell), 83, 93 Third basic cell (basic cell), 84, 94 Fourth basic cell (basic cell).

Claims (7)

  One or more high-threshold PMOS transistors having a threshold higher than that of the low-threshold MOS transistors, and one or more low-threshold MOSs, which are sequentially arranged with the gate electrodes aligned in the row direction A basic cell having a configuration in which a plurality of transistor groups each including one or a plurality of high threshold NMOS transistors having a threshold higher than that of a transistor and a low threshold MOS transistor are arranged in the column direction is divided into two adjacent cells in the row direction. The high threshold PMOS transistor of one basic cell and the high threshold PMOS transistor of the other basic cell face each other, or one of two basic cells adjacent in the row direction The high threshold NMOS transistor of one basic cell and the high threshold NMOS transistor of the other basic cell face each other. Transistor array, characterized in that it is constructed by arranging the Rikusu shape. In a semiconductor integrated circuit in which a power supply control circuit is provided in a path for supplying current to a CMOS logic circuit,
With a MOS transistor of the N low threshold gate length is larger than the MOS transistor of said M which has the same threshold as the first M of the MOS transistor and of said M MOS transistors of low threshold Composed of macrocells formed by
A semiconductor integrated circuit, wherein the CMOS logic circuit is formed using the Mth MOS transistor, and the power supply control circuit is formed using the Nth MOS transistor. In a macro cell for forming a semiconductor integrated circuit in which a power supply control circuit is provided in a path for supplying current to a CMOS logic circuit,
With a MOS transistor of the N low threshold gate length is larger than the MOS transistor of said M which has the same threshold as the first M of the MOS transistor and of said M MOS transistors of low threshold Formed,
A macro cell, wherein the CMOS logic circuit is formed using the Mth MOS transistor, and the power control circuit is formed using the Nth MOS transistor. In a basic cell for forming a macro cell for forming a semiconductor integrated circuit in which a power supply control circuit is provided in a path for supplying current to a CMOS logic circuit,
Consists, the MOS transistor of the N gate length is greater low threshold than MOS transistors of said M which has the same threshold as the first M of the low threshold MOS transistor and the MOS transistor of said M And
A basic cell, wherein the CMOS logic circuit is formed using the Mth MOS transistor, and the power control circuit is formed using the Nth MOS transistor. A group of transistors including one or more Nth MOS transistors, one or more Mth MOS transistors, and one or more Nth MOS transistors arranged in order in the row direction with the gate electrodes aligned. 5. The basic cell according to claim 4 , wherein a plurality of the cells are arranged in a direction. In a transistor array for forming a semiconductor integrated circuit in which a power supply control circuit is provided in a path for supplying current to a CMOS logic circuit,
One or a plurality of low threshold Nth transistors having the same threshold value as that of the Mth MOS transistor and having a gate length larger than that of the Mth MOS transistor, which are sequentially arranged with the gate electrodes aligned in the row direction . PMOS transistor, one or a plurality of low threshold Mth MOS transistors, and one or a plurality of low thresholds having the same threshold as that of the Mth MOS transistor and having a gate length larger than that of the Mth MOS transistor A basic cell having a configuration in which a plurality of transistor groups each having a value Nth NMOS transistor are arranged in the column direction is replaced with the Nth PMOS transistor of one basic cell and the other basic cell of two basic cells adjacent in the row direction. Arranged in a matrix so as to face the Nth NMOS transistor of the cell,
A transistor array, wherein the CMOS logic circuit is formed using the Mth MOS transistor, and the power control circuit is formed using the Nth PMOS transistor and the Nth NMOS transistor. In a transistor array for forming a semiconductor integrated circuit in which a power supply control circuit is provided in a path for supplying current to a CMOS logic circuit,
One or a plurality of low threshold Nth transistors having the same threshold value as that of the Mth MOS transistor and having a gate length larger than that of the Mth MOS transistor, which are sequentially arranged with the gate electrodes aligned in the row direction . PMOS transistors, one or a plurality of low threshold Mth MOS transistors and Mth MOS transistors, and one or a plurality of Nth transistors having the same threshold as that of the Mth MOS transistors and having a gate length larger than that of the Mth MOS transistors A basic cell having a configuration in which a plurality of transistor groups each composed of a low-threshold NMOS transistor are arranged in the column direction is divided into an Nth PMOS transistor of one basic cell and the other basic cell of two basic cells adjacent in the row direction. One base of two basic cells facing the Nth PMOS transistor of the cell or adjacent in the row direction And the N-th NMOS transistor of the N of the NMOS transistor and the other of the basic cells of the cell is constructed by arranging in a matrix so as to face,
A transistor array, wherein the CMOS logic circuit is formed using the Mth MOS transistor, and the power supply control circuit is formed using the Nth PMOS transistor and / or the Nth NMOS transistor.

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