JP4872264B2 - Semiconductor integrated circuit, power switch cell, and circuit cell with power switch - Google Patents

Description

  In the present invention, a circuit block is formed with a circuit cell connected between a power supply voltage supply line and a reference voltage supply line as a basic unit, such as a so-called multi-threshold CMOS (MTCMOS) integrated circuit. The present invention relates to a semiconductor integrated circuit including a switch transistor for controlling power supply in a circuit block, a power switch cell used in the semiconductor integrated circuit, and a circuit cell with a power switch.

With the recent high integration and miniaturization of CMOS integrated circuits, the power supply voltage has been lowered.
Lowering the power supply voltage is necessary from the viewpoints of both ensuring reliability associated with miniaturization and reducing power consumption. However, when the power supply voltage is lowered, the operating speed of the CMOS transistor is lowered, and thus the operating speed is reduced. It is necessary to lower the threshold voltage of the CMOS transistor from the viewpoint of improvement and securing of circuit operation margin. For example, in an LSI having a minimum dimension of 100 nm or less as in recent years, the power supply voltage Vdd needs to be lowered to about 1.0 V, and in that case, the threshold voltage of the transistor needs to be lowered to about 0.3 V.

  However, as is well known, an increase in leakage current in the subthreshold region becomes a problem as the threshold voltage decreases, and how to reduce this leakage current is a major issue.

  In order to solve this problem, MTCMOS (Multi-threshold Complementary Metal Oxide Semiconductor) technology as a circuit configuration contrivance in addition to process approach such as improving leakage characteristics or reducing parasitic capacitance to increase operation speed Has been proposed.

In a logic LSI to which MTCMOS technology is applied, a power supply voltage supply line is separated into a sub-wiring generally called a virtual power supply line and a main wiring for supplying a power supply voltage to the sub-wiring. A switch transistor for controlling the connection between the two wirings is provided between the main wiring and the sub wiring.
This configuration for power supply control may be provided on one of the power supply voltage supply line and the reference voltage supply line or on both.

In a cell placement type logic LSI, a large number of circuit cells having the function of a logic circuit are arranged in a circuit block to which the MTCMOS technology is applied, and a power switch cell having the switch transistor is appropriately arranged between the circuit cells. .
The circuit cell has a sub-wiring of a power supply voltage supply line or a reference voltage supply line, and a logic circuit region connected to the sub-wiring.
The power switch cell is connected between the main wiring of the power supply voltage supply line or the reference voltage supply line, the switch transistor connected between the main wiring and the sub wiring of the circuit cell, and turned on when the circuit cell is operated and turned off when the circuit cell is not operated. Have A switch transistor has a higher threshold voltage than a transistor in a logic circuit cell, and is a kind of generally called power transistor.

  In the cell arrangement method, circuit cells are connected by internal signal lines. Further, if necessary, circuit cells and circuit cells and power switch cells are connected to each other by a wiring layer to connect signal paths and power supply paths, thereby realizing a circuit having a desired function. .

  In a circuit block to which the MTCMOS technology is applied, when the transistor block is not used, the transistor switch is set to OFF, and the leakage current flowing through the transistor in each logic circuit cell in the circuit block is cut off. As a result, useless leakage current flowing in unused circuit blocks can be greatly reduced.

On the other hand, a macro cell (a circuit cell with a power switch) including a switch transistor for power supply control in a circuit cell having a function of a logic circuit has been proposed (see, for example, Patent Document 1).
By appropriately arranging the circuit cell with the power switch in the circuit block, the leakage current can be greatly reduced.
JP-A-11-136121

Since the switch transistor has a relatively high threshold voltage, if the on-resistance when driven by the internal power supply voltage is high, the switch transistor has a large power drop, and the power supply voltage value applied to the logic circuit region is substantially reduced. Make it smaller.
Therefore, the current drive capability of the switch transistor must be increased to some extent. Since the switch transistor has a large on-resistance when its gate width (the size of the long side of the effective gate electrode portion) is small, a certain degree of gate width is required to provide a high current driving capability.

  On the other hand, the power switch cell in which the switch transistor is formed or the power switch region in the power switch circuit cell is an element region that does not directly contribute to the function of the circuit block, and therefore the size thereof should be reduced as much as possible. Is desirable.

  The problem to be solved by the present invention is to reduce the size of the power switch cell or power switch region that does not directly contribute to the function of the circuit block without reducing the current drive capability.

The semiconductor integrated circuit according to the present invention, the circuit cells connected between a power supply voltage supply line and the reference voltage supply line have a circuit block is formed as the basic unit, the power supply voltage supply line, the reference At least one of the voltage supply lines includes a sub-wiring in the circuit cell and a main wiring arranged in one direction, and a switch transistor that controls connection and disconnection between the sub-wiring and the main wiring is provided in the circuit. disposed within the block, the gate electrode of said switching transistor is arranged from the same main wiring in the cell arrangement direction and parallel rows of circuit cell groups which receives the power supply, the power switch cell having the switching transistor, the power switch It is shared by two circuit cells orthogonal to the arrangement direction of the main wiring for supplying power to the cell.
In the present invention, the switch transistor may be provided in a circuit cell.

The power switch cell according to the present invention includes two gate electrodes parallel to each other, a common first source / drain region formed in a semiconductor region between the two gate electrodes, and the two gate electrodes. Two switch transistors having two second source / drain regions separated on each side of the first and second switch transistors connected to the first source / drain region common to the two switch transistors and arranged in one direction comprising: a main wiring of the power supply voltage supply line or the reference voltage supply line and the said two switch transistors are those, each of which controls the power supply to the adjacent circuit cell, wherein the two switch transistors 2 a wiring direction of the gate electrode of the wiring direction of the main wiring is set to the parallel line.
Another power switch cell according to the present invention includes a gate electrode having two gate finger portions parallel to each other, a first source / drain region formed in a semiconductor region between the two gate finger portions, and A single switch transistor having two second source / drain regions separated on each side of the two gate fingers, and connected to the first source / drain region of the single switch transistor A power supply voltage supply line or a main wiring of a reference voltage supply line arranged in one direction, and the single switch transistor controls power supply to adjacent circuit cells, The wiring direction of the two gate fingers of the switch transistor and the wiring direction of the main wiring are set in parallel.

A circuit cell with a power switch according to the present invention includes a logic circuit region, two gate electrodes parallel to each other, a common first source / drain region formed in a semiconductor region between the two gate electrodes, and Two switch transistors having two second source / drain regions separated on each side of the two gate electrodes and connected to the first source / drain region common to the two switch transistors A power supply voltage supply line or a main wiring of a reference voltage supply line arranged in one direction, and the two switch transistors are connected to one of the second source / drain regions and the logic circuit region To control the power supply to the logic circuit area, and independently of the control, the other circuit cell adjacent to the other second source / drain area. Of a controllable power supply, the wiring direction of said two gate electrodes of said two switch transistors, the wiring direction of the main wiring is set to the parallel line.
Another circuit cell with a power switch according to the present invention includes a logic circuit region, a gate electrode having two gate finger portions parallel to each other, and a first region formed in a semiconductor region between the two gate finger portions. A single switch transistor having a source / drain region and two second source / drain regions separated on each side of the two gate finger portions; and the first of the single switch transistor. A power source voltage supply line or a main wiring of a reference voltage supply line arranged in one direction and connected to the source / drain region of the first switch transistor, wherein the single switch transistor has one of the second source / drain regions A region is connected to the logic circuit region to control power supply to the logic circuit region, and the other second source / drain region To be controlled the power supply to the logic circuit region of a circuit cell adjacent, the wiring direction of the two gate fingers of said switching transistor, a wiring direction of the main wiring is set in parallel.

In the present invention, in order to share the switch transistor between circuit cells, the following configuration is desirable.
Preferably, the present invention includes two switch transistors having two gate electrodes parallel to each other, and a semiconductor region between the two gate electrodes is shared by the two switch transistors and connected to the main wiring. ing.
Alternatively, preferably, a single switch transistor having two gate finger portions parallel to each other is provided, and a semiconductor region between the two gate finger portions is connected to the main wiring.

Next, the operation of the present invention will be described.
The following description is based on the premise (example) that the main wiring of the power supply line is arranged in the row (row) direction.

Under this premise, the main wiring is a wiring for supplying power to circuit cell groups arranged in parallel in the row direction. This power supply is controlled via a switch transistor for one or a predetermined number of circuit cells for a group of circuit cells arranged in the row direction.
The size of the power switch cell in the column direction perpendicular to the row direction is not affected by the size of the circuit cells arranged around it. This is because the arrangement direction of the power switch cells is the row direction, and therefore, the size reduction in the column direction of the power switch cells is more flexible than the size reduction in the row direction.

Under the above assumptions, the direction in which the power switch cells and the power switch regions are arranged, the arrangement direction of the main wiring (that is, the length direction), and the cell arrangement direction of the circuit cell group supplied from the same main wiring are all in the row direction. It is.
Therefore, the gate electrode of the switch transistor is also arranged (long) in the row direction. The size in the row direction is sufficient as the size in the length direction of the gate electrode, and there is a sufficient space for the arrangement.
On the other hand, the width (gate length) direction size of the gate electrode is extremely smaller than the length (gate width) direction size of the gate electrode. For this reason, the switch transistor has a margin that the size in the column direction can be made smaller than the size in the length direction of the gate electrode even if the width of the source region and drain region is added to the width of the gate electrode.

  The above discussion is applicable not only to the power switch cell but also to the power switch region in the circuit cell. The above discussion is also valid if the row direction is replaced with the column direction and the column direction is replaced with the row direction.

  As described above, in the present invention, the gate electrode of the switch transistor is arranged substantially in parallel with the cell arrangement direction of the circuit cell group that receives power supply from the same main wiring. Therefore, considering the above discussion, the switch transistor according to the present invention is reduced in size in the width direction of the gate electrode even when the gate electrode is the same length as compared with the case where the arrangement of the gate electrode is orthogonal to the present invention. Can afford.

  Further, in the present invention, when two gate electrodes or gate finger portions are arranged in parallel and the main wiring is connected to the semiconductor region therebetween, the following effects are obtained.

In the switch transistor, a semiconductor region between two gate wirings is a source region, and two other semiconductor regions positioned outside in the width direction of the two gate wiring regions are both drain regions.
In other words, in this configuration, two semiconductor regions located on the two sides facing the width direction of the gate electrode of the switch transistor region are both drain regions. For this reason, when the switch transistor is shared by two circuit cells adjacent to the two opposite sides, the connection wiring does not intersect and becomes the shortest.

  According to the present invention, there is an advantage that the size of the power switch cell or the power switch region that does not directly contribute to the function of the circuit block can be reduced without degrading the current driving capability.

  Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 is a layout diagram of a semiconductor integrated circuit using MTCMOS according to an embodiment of the present invention. FIG. 2 shows a basic circuit of a circuit block to which MTCMOS is applied.

In the semiconductor integrated circuit of the present invention, all circuit blocks can be applied to MTCMOS.
On the other hand, in the layout example shown in FIG. 1, a specific functional circuit block among the functional circuit blocks 4 </ b> A to 4 </ b> E in the circuit area 3 located on the chip inner side than the arrangement area of the pads 2 located on the peripheral edge of the semiconductor integrated circuit 1, In this example, the MTCMOS configuration is applied only to the functional circuit blocks 4A and 4E, and the MTCMOS configuration is not applied to the remaining functional circuit blocks 4B, 4C, and 4D.
In the remaining circuit area 3 excluding these functional circuit blocks 4A to 4E, common circuits are arranged in the entire functional circuit blocks such as a power supply circuit, an input / output circuit and a timing control circuit, although not particularly shown. Yes.

  In the circuit block to which the MTCMOS configuration is applied in the present invention, at least one of the power supply voltage supply line and the reference voltage supply line is separated into a main wiring and a sub wiring generally called “virtual power supply line”. Connection to the wiring is controlled by a switch transistor. In addition, a logic circuit having a necessary function is connected to the sub wiring.

FIG. 2 shows an example in which MTCMOS is applied to both the power supply voltage supply side and the reference voltage supply side.
In FIG. 2, a first switch transistor SWP made of a PMOS transistor is connected between a first main wiring VDD for supplying a power supply voltage Vdd and a first sub wiring V-VDD. In addition, a second switch transistor SWN made of an NMOS transistor is connected between the second main wiring VSS for supplying the reference voltage Vss and the second sub-wiring V-VSS.

The first and second switch transistors SWP and SWN are composed of high threshold (H-Vth) transistors.
A first control voltage Vcp is applied to the gate of the first switch transistor SWP by a control line (not shown), and a second control voltage Vcn is applied to the gate of the second switch transistor SWN by another control line (not shown). .

  A logic circuit LC such as a logic gate having a desired function is connected between the first sub-wiring V-VDD and the second sub-wiring V-VSS. Although not specifically shown, the logic circuit LC is generally composed of a low threshold (L-Vth) CMOS circuit.

  When both the first and second switch transistors SWP and SWN are on, power is appropriately supplied to the logic circuit LC. On the other hand, when one or both of the first and second switch transistors SWP and SWN are in the OFF state, the power supply voltage supply from at least one of the first main wiring VDD and the second main wiring VSS is the first switch transistor SWP. And / or is interrupted by the second switch transistor SWN, and at least one of the first sub-wiring V-VDD and the second sub-wiring V-VSS is in an electrically floating state, so that the logic circuit LC does not operate. . Since the leakage current is prevented from flowing through the logic circuit LC in the off state, the power consumption during standby of the circuit block is reduced.

  As described above, when the MTCMOS configuration is applied, the circuit block becomes redundant in terms of circuit. Therefore, it is desirable to apply the MTCMOS configuration only to a circuit portion in which a leakage current is a problem during a low voltage operation.

  FIG. 3 is a block layout diagram showing a cell arrangement of a circuit block to which MTCMOS is applied. FIG. 4 is a cell layout diagram showing, as an example, a cell (hereinafter referred to as a slice cell) serving as a basic structural unit of the layout of FIG. 3 in the case of a 2-input NAND circuit.

As shown in FIG. 4, one slice cell 10 includes other slice cells 10u, 10d adjacent in the column direction corresponding to the vertical direction in the figure, and the first and second switch transistors SWP, SWNs share a switch area in which each is formed.
More specifically, the slice cell 10 includes a PMOS switch region 11 shared with another slice cell 10u, an NMOS switch region 12 shared with another slice cell 10d, and a logic gate region 13.

The NMOS switch region 12 has a first main wiring VSS that is long in the row (row) direction at the center in the column direction, and a layout that is line symmetric in the column direction about the center line of the first main wiring VSS. Has a pattern.
Similarly, the PMOS switch region 11 is provided with a second main wiring VDD that is long in the row direction at the center in the column direction, and is symmetrical in the column direction about the center line of the second main wiring VDD. The layout pattern is as follows.
The central axis of each main wiring is a cell boundary in the column direction.

  As described above, the slice cell of the present embodiment has a layout suitable for sharing the first and second switch transistors SWP and SWN of FIG. 2 between the cells.

The circuit block 4 of FIG. 3 is formed by arranging a large number of such slice cells 10.
In the circuit block 4 shown in FIG. 3, the cell size in the row direction is the minimum basic size W or an arbitrary multiple of the basic size W. A relatively small logic gate circuit such as the NAND circuit shown in FIG. 4 needs only a basic cell size W in the row direction. However, in other large logic gate circuits, the row size depends on the scale. The cell size in the direction can be arbitrarily selected as 2W, 3W,.
The cell size in the row direction is not limited to the illustrated example, that is, it is not necessarily required to be a multiple of the basic size W.

In any slice cell, the cell size in the column direction is defined to be constant.
For this reason, in the example of FIG. 3 in which a large number of these different types of slice cells are arranged, the PMOS switch region 11 shared by two cells is connected in the row direction to form one line. Similarly, the NMOS switch region 12 shared by two cells is connected in the row direction to form one line. As seen in FIG. 3 as a whole, the line-like PMOS switch regions 11 and NMOS switch regions 12 are alternately arranged at predetermined intervals in the column direction.
Such a cell arrangement method is called a cell slice method.

Next, the layout of the slice cell 10 will be described in more detail with reference to FIG.
In FIG. 4, for improved visibility, the wiring and contacts are shown as thin lines, black circles, or white circles as in the case of circuit connection, and are different from actual wiring and contact patterns.
In FIG. 4, the symbol “GM” represents a gate metal having a structure such as a polysilicon single layer or a multilayer of polysilicon and a refractory metal. Also, reference numeral “1M” is the 1st wiring layer, reference numeral “2M” is the 2nd wiring layer, reference numeral “1C” is the 1st contact that connects the gate metal or well and the 1st wiring layer, and reference numeral “2C” is the 1st wiring layer and 2nd. This represents a 2nd contact that connects the wiring layers. In FIG. 4, the 1st contact is represented by a black circle, and the 2nd contact is represented by a white circle.

Two wells having an impurity concentration profile for increasing the threshold (H-Vth) on the wafer of the semiconductor integrated circuit, that is, an N well (NWELL (H-Vth)) 14 for the PMOS switch region 11, In addition, a P well (PWELL (H-Vth)) 15 for the NMOS switch region 12 is formed.
Further, two wells having an impurity concentration profile for lowering the threshold (L-Vth) on the wafer, that is, an N well 16 for the PMOS transistor in the logic gate region 13 and a P for the NMOS transistor A well 17 is formed.

First, the layout of the two switch areas will be described.
On the N-well 14, two openings of the element isolation insulating layer are formed.
The gate electrode 20 of the first switch transistor SWP in FIG. 2 is overlaid on the larger opening. The gate electrode 20 has two gate finger portions 20A and 20B that are long in the row direction, and one ends thereof are connected to each other. Each of the gate finger portions 20A, 20B has the same width and intersects the large opening in the same way.

  By using the gate electrode 20 and the element isolation insulating layer as a self-aligned mask, a P-type impurity is introduced into a portion other than the region intersecting the gate electrode 20 in the opening by introducing a P-type impurity into the large opening. PDIFF) is formed. This P-type impurity region includes a source region 21s between the gate finger portions 20A and 20B and two drain regions 21d1 and 21d2.

  On the other hand, an N-type impurity is introduced into the smaller opening formed on the N-well 14 to form an N-type contact region 22.

A first main wiring VDD composed of a 2nd wiring layer (2M) is arranged along a cell boundary passing through the center of the width in the column direction of the source region 21s.
The first main wiring VDD is connected to the source region 21s via a connection pad layer 24 including a 2st contact (2C) 23, a 1st wiring layer (1M), and a 1st contact (1C) 25.
The first main wiring VDD is connected to the N-type contact region 22 via a connection layer 27 including a 2st contact (2C) 26, a 1st wiring layer (1M), and 1st contacts (1C) 28 and 28. ing. As a result, the N well 14 is fixed at the power supply voltage Vdd.

  A first contact (1C) 29 is provided on the gate electrode 20, and the gate electrode 20 is connected to a control line (not shown) for applying the first control voltage Vcp of FIG. Yes. This control line is arranged in the column direction, and is provided as one control line passing over the PMOS switch region 11 in the entire cell array of FIG.

The pattern of the PMOS switch region 11 is the same in the NMOS switch region 12.
In the NMOS switch region 12, a source region 31s that is an N-type impurity region (NDIFF) is formed in place of the source region 21s of the PMOS switch region 11. Instead of the drain regions 21d1 and 21d2 in the PMOS switch region 11, drain regions 31d1 and 31d2 which are N-type impurity regions are formed. A P-type contact region 32 is formed instead of the N-type contact region 22. Further, the second main wiring VSS is arranged in the row direction instead of the first main wiring VDD.
Since the other configuration including the gate electrode 20 is the same as that of the PMOS switch region 11, the description thereof is omitted here.

FIG. 5 shows a circuit diagram of the NAND gate.
The NAND gate has two pairs of transistors having a common gate, that is, a PMOS transistor P1 and an NMOS transistor N1, and a PMOS transistor P2 and an NMOS transistor N2. All of these four transistors are low threshold (L-Vth) transistors.

The drains of the two PMOS transistors P1 and P2 are both connected to the first sub-wiring V-VDD. The first input signal Sin1 is supplied to the gate of the PMOS transistor P1, and the second input signal Sin2 is supplied to the gate of the PMOS transistor P2. Further, the sources of the two PMOS transistors are shared, and an output signal Sout is output therefrom.
NMOS transistors N2 and N1 are connected in cascade between the output node of the output signal Sout and the second sub-wiring V-VSS.

A layout of the NAND gate will be described.
As shown in FIG. 4, two large and small openings of the element isolation insulating layer are formed on the N well 16. Similarly, two large and small openings of the element isolation insulating layer are formed on the P well 17.
Among these, the first common gate electrode 41 and the second common gate electrode 42 which cross two large openings in the column direction are arranged in parallel to each other. The first and second common gate electrodes 41 and 42 constitute input nodes for the first and second input signals Sin1 and Sin2 in FIG. In FIG. 4, the input / output lines for these signals are not shown.

By introducing a P-type impurity into the N well 16 shown in FIG. 4 using the first and second common gate electrodes 41 and 42 and the element isolation insulating layer as a self-alignment mask, the first opening in the large opening is obtained. A P-type impurity region (PDIFF) is formed in a portion other than the region intersecting with the second common gate electrodes 41 and 42. The P-type impurity region includes a common drain region 43d between the first and second common gate electrodes 41 and 42 and two source regions 43s1 and 43s2.
Similarly, by introducing N-type impurities into the P well 17 using the first and second common gate electrodes 41 and 42 and the element isolation insulating layer as a self-alignment mask, the first and second common gate electrodes 41 and 42 in the large opening portion are introduced. An N-type impurity region (NDIFF) is formed in a portion other than the intersecting region with the second common gate electrodes 41 and 42. The N-type impurity region includes a floating region 44f between the first and second common gate electrodes 41, 42, a drain region 44d, and a source region 44s.

On the other hand, an N-type impurity is introduced into the smaller opening formed on the N-well 16 to form an N-type contact region 45. The N-type contact region 45 includes a first main wiring VDD provided in the PMOS switch region 11 via a wiring layer 47 including a first contact (1C) 46, a first wiring layer (1M), and a second contact (2C) 48. It is connected to the.
Similarly, a P-type contact region 49 is formed by introducing a P-type impurity into the smaller opening formed on the P-well 17. The P-type contact region 49 is a second main wiring VSS provided in the NMOS switch region 12 via a wiring layer 51 including a first contact (1C) 50, a first wiring layer (1M), and a second contact (2C) 52. It is connected to the.

A first sub-wiring V-VDD that is long in the column direction is wired above the element isolation insulating layer between the N-well 16 and the N-well 14. Similarly, a second sub wiring V-VSS that is long in the column direction is wired above the element isolation insulating layer between the P well 17 and the P well 15.

The source region 43s1 of the PMOS transistor P1 is connected to the first sub-wiring V-VDD via a wiring layer 54 including a first contact (1C) 53, a first wiring layer (1M), and a second contact (2C) 55. .
Similarly, the source region 43s2 of the PMOS transistor P2 is connected to the second sub-wiring V-VDD via the wiring layer 57 including the first contact (1C) 56 and the first wiring layer (1M) and the second contact (2C) 58. Has been. The wiring layer 57 extends into the PMOS switch region 11 and is connected to the drain region 21d1 of the switch transistor via a first contact (1C) 65. This connection relationship is the same for the other slice cells 10u.

  The common drain region 43d of the PMOS transistors P1 and P2 is connected to the drain region 44d of the NMOS transistor N1 via the wiring layer 60 including the first contact (1C) 59 and the first wiring layer (1M) and the first contact (1C) 61. Has been. The source region 44s of the NMOS transistor N2 is connected to the second sub-wiring V-VSS via the wiring layer 63 including the first contact (1C) 62 and the first wiring layer (1M) and the second contact (2C) 64. . The wiring layer 63 extends on the NMOS switch region 12 and is connected to the drain region 31d1 of the switch transistor. This connection relationship is the same for other slice cells 10d.

FIG. 6 shows an arrangement diagram centering on the three slice cells in the second row in the slice cell group of 3 rows × 3 columns.
In FIG. 6, all slice cells 10 are provided with first and second switch transistors SWP and SWN.
In this arrangement, a cell array, such as a gate array, is formed up to the pattern before forming the first wiring layer (1M) of the cell. This is particularly effective when designing by placing and wiring.

On the other hand, an arrangement in which the first and second switch transistors SWP and SWN are not provided in all slice cells is also possible. In this case, slice cells 10 with power switches are arranged every predetermined number in the row direction.
However, in the standard cell system, since the unit size W of the slice cell 10 in the row direction is determined, if the first and second switch transistors SWP and SWN are provided for each slice cell 10 as shown, This is preferable because the current driving capability for the slice cell 10 can be made uniform at a high level and a useless area does not occur.

  Hereinafter, the effect of this embodiment will be described by comparison with a comparative example.

[Comparative example]
FIG. 7 shows a cell layout diagram of the slice cell of the comparative example.
The comparative example is different from the layout of FIG. 4 in the configuration of the PMOS switch region 110 and the NMOS switch region 120 of FIG.

Two large and small openings are formed on the N well 14 in the PMOS switch region 110, and a gate electrode 101 that is long in the column direction is disposed in the larger opening. One end of the gate electrode is connected to a control line (not shown) via a first contact (1C) 101A.
A drain region 102 d and a source region 102 s are formed as P-type impurity regions in the opening around the gate electrode 101. The drain region 102d is connected to the first main wiring VDD via a wiring layer 104 including a 1st contact (1C) 103, a 1st wiring layer (1M), and a 2st contact (2C) 105. The source region 102s is connected to the wiring layer 57 via the 1st contact (1C), and thereby connected to the first sub-wiring V-VDD.

  On the other hand, an N-type impurity region 106 is formed in the smaller opening on the PMOS switch region 110. The N-type impurity region 106 is connected to the first main wiring VDD via a wiring layer 108 including a first contact (1C) 107, a first wiring layer (1M), and a second contact (2C) 109.

In this switch transistor layout, the gate electrode 101 needs to have a necessary length (gate width), and the 1st contact (1C) 101A is provided at one end thereof. The size will definitely increase.
In addition, the pattern on both sides in the column direction of the center line of the first main wiring VDD is asymmetric, and there is a disadvantage that the wiring length becomes long for sharing.

  Although not specifically described in detail, such a configuration is the same in the NMOS switch region 120, and there is a disadvantage that it is difficult to increase the size in the column direction and to share the cells.

On the other hand, the cell layout of this embodiment shown in FIG. 4 has the following advantages.
First, as described above, since the layout of the switch transistor is line symmetric in the column direction with the cell boundary as the central axis, it is shared by two slice cells in the column direction, although it is a single switch transistor. It is easy.
More specifically, in the switch transistor shown in FIG. 4, the semiconductor region between the two gate wirings (gate finger portions 20A and 20B) has two regions located outside the source region and the region between the two gate wirings in the width direction. The other semiconductor regions are both drain regions.
For this reason, when the switch transistor is shared by two circuit cells adjacent to each other on the two sides facing each other, in which two drain regions of the switch region are adjacent to each other, the connection wiring does not intersect. And there is an advantage that it becomes the shortest.

The arrangement direction of the gate finger portions 20A and 20B is the row direction. Therefore, the arrangement direction of the gate finger portions 20A and 20B substantially coincides with the cell arrangement direction of a group of circuit cells (slice cells 10) that receive power supply from the same main wiring.
In this example, the arrangement direction of the first and second common gate electrodes 41 and 42 of the logic gate transistors in the slice cell 10, that is, the PMOS transistors P1 and P2 and the NMOS transistors N1 and N2, is the column direction. Therefore, the arrangement direction of the gate finger portions 20A and 20B is substantially orthogonal to the arrangement direction of the gate electrode of the logic gate transistor.

In general, the first and second common gate electrodes 41 and 42 in the logic gate region 13 are generally orthogonal to the power supply wiring (see Patent Document 1 and Comparative Example). This is due to the following reason.
When the first and second common gate electrodes 41 and 42 shown in FIGS. 4 and 7 are arranged in the column direction, the first sub-wiring V-VDD and the second sub-wiring V-VSS arranged in the row direction. When viewed from the above, all ends of the logic gate transistor source regions 43s1, 43s2 and 44s, and the logic gate transistor drain regions 43d, 44d, etc. are aligned on any sub-wiring side. In addition, like the wiring layers 54, 57 and 63 in FIG. 4, it is possible to connect the wiring layers with the shortest distance straight without straddling the gate electrode.

As described above, the slice cell 10 of the present embodiment shown in FIG. 4 has the advantage that the wiring is easy and the shortest in all the regions of the logic gate region 13, the PMOS switch region 11, and the NMOS switch region 12. is there.
In addition, in the PMOS switch region 11 and the NMOS switch region 12, since the gate finger portions 20A and 20B are arranged in the row direction, the size H (see FIG. 6) in the column direction is compared with the comparative example of FIG. And can be small.
Therefore, according to the present embodiment, it is possible to realize a semiconductor integrated circuit in which wiring is easy, a useless area for wiring routing does not occur, and the occupied area of the power switch area is small.

[Second Embodiment]
In the slice cell 10 of the first embodiment shown in FIG. 4, each of the PMOS switch region 11 and the NMOS switch region 12 includes one switch transistor. For this reason, it is not possible to separately control power supply between the two slice cells 10 that are adjacent in the column direction and share the switch transistor.

  In the present embodiment, two switch transistors are provided in each of the PMOS switch region 11 and the NMOS switch region 12 without increasing the area in order to increase the degree of freedom of control of power supply.

FIG. 8 shows a cell layout diagram of this embodiment.
8 differs from FIG. 4 in that two gate electrodes of the switch transistor in the PMOS switch region 11 are provided as indicated by reference numerals 70 and 71 and are not connected. The gate electrode 70 is connected to a control line (not shown) via a first contact (1C) 72. The gate electrode 71 is connected to another control line (not shown) via a first contact (1C) 73. These two control lines can be driven independently.

  8 is different from FIG. 4 in that two gate electrodes of switch transistors in the PNMOS switch region 12 are provided as indicated by reference numerals 80 and 81 and are not connected. The gate electrode 80 is connected to a control line (not shown) via a first contact (1C) 82. The gate electrode 81 is connected to another control line (not shown) via a first contact (1C) 83. These two control lines can be driven independently.

As described above, in this embodiment, the gate electrode 20 of the first embodiment can be separated into two switch transistors having a common source only by wiring them to independent control lines. Therefore, power supply control can be independently performed in two slice cells 10 adjacent in the column direction.
By appropriately arranging the slice cells of FIG. 8 and the slice cells of FIG. 4, it is possible to stop power supply to some cell groups in the same circuit block, and to perform more efficient power control. Will be able to do.

  The other slice cell configurations are the same in FIGS. 8 and 4, and the diagrams shown in FIGS. 1 to 3, 5 and 6 are applied to this embodiment.

[Third Embodiment]
This embodiment is not a slice cell system but a case where a region having a switch transistor is provided as a power switch cell independent of a logic gate cell.

FIG. 9 shows a partially enlarged view of the circuit block.
In this embodiment, the PMOS switch cell region and the NMOS switch cell region are formed in a parallel stripe shape in the row direction. A PMOS power switch cell 90 is disposed in the PMOS switch cell region, and an NMOS power switch cell 91 is disposed in the NMOS switch cell region.
These power switch cells 90 and 91 can be arranged in the respective regions at predetermined intervals in the row direction, but it is preferable to arrange as many as possible in order to increase the current driving capability. In FIG. 9, they are arranged without leaving a useless space.

  The PMOS power switch cell 90 has a layout pattern substantially similar to the PMOS switch region 11 shown in FIG. 4, and the NMOS power switch cell 91 has a layout pattern substantially similar to the NMOS switch region 12 shown in FIG.

A space between the arrangement of the PMOS power switch cells 90 and the arrangement of the NMOS power switch cells 91 is a logic gate cell region, and logic gate cells 92A, 92B, and 92C for realizing a desired circuit function are provided in the logic gate cell region. Has been placed.
In the case of a NAND gate, logic gate cells 92A, 92B, and 92C have a layout pattern substantially similar to that of logic gate region 13 in FIGS.
Each of the first sub-wiring V-VDD and the second sub-wiring V-VSS is shared by the logic gate cells 92A, 92B, and 92C and the PMOS power switch cell 90 or the NMOS power switch cell 91.

In this embodiment, the power switch cell is provided independently of the logic gate cell, so that the size in the row direction can be arbitrarily set for each of the power switch cell and the logic gate cell. This provides the advantage of a high degree of freedom in arrangement.
In particular, the sizes of the logic gate cells adjacent to each other and the power switch cells 90 and 91 do not coincide with each other in the row direction and the column direction, but the power switch cells 90 and 91 are arranged in the column direction around the center line. Because of the line symmetry, by fixing the position of the power switch cell in the column direction, the power switch cell can be efficiently laid out in terms of area.

The present invention is not limited to the first to third embodiments, and various modifications can be made without departing from the spirit of the present invention.
For example, in FIG. 4, FIG. 6, FIG. 8 and FIG. 9, the number of gate electrodes or finger portions of the MOS transistor constituting the switch transistor is 2, but this number should be increased from 2 to increase the switch transistor size. It can also be enlarged.
Especially when the switch transistor is shared between circuit cells, this number must be an even number.
Thereby, the current drive capability of each switch transistor can be improved.

  4 and 8, well isolation is performed to arrange a high threshold (H-Vth) transistor and a low threshold (L-Vth) transistor, but the well is shared. High threshold and low threshold transistors can also be formed in the same well depending on the difference in the amount of ions implanted when forming the impurity regions. In that case, the number of wells may be two, a common P well and a common N well, and the cell area can be reduced accordingly.

It is a layout diagram of a semiconductor integrated circuit according to the first to third embodiments of the present invention. The basic circuit of the circuit block of 1st and 2nd embodiment is shown. It is a block layout diagram showing a cell arrangement of circuit blocks of the first and second embodiments. It is a cell layout diagram of the slice cell of the first embodiment. It is a circuit diagram of a NAND gate. FIG. 3 is an arrangement diagram of slice cell groups of 3 rows × 3 columns. It is a cell layout figure of a comparative example. It is a cell layout figure of 2nd Embodiment. It is a partial enlarged view of the circuit block of 3rd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit, 4, 4A, 4E ... MTCMOS application circuit block, 10 ... Slice cell, 11 ... PMOS switch area | region, 12 ... NMOS switch area | region, 13 ... Logic gate area | region, 20, 70, 71, 80, 81 , 101 ... Gate electrode, 20A, 20B ... Gate finger part, 90 ... PMOS power switch cell, 91 ... NMOS power switch cell, 92A to 92C ... Logic gate cell, SWP ... First switch transistor, SWN ... Second switch transistor, VDD ... 1st main wiring, V-VDD ... 1st sub wiring, VSS ... 2nd main wiring, V-VSS ... 2nd sub wiring

Claims (9)

The circuit cells connected between a power supply voltage supply line and the reference voltage supply line have a circuit block is formed as the basic unit,
At least one of the power supply voltage supply line and the reference voltage supply line is composed of a sub-wiring in the circuit cell and a main wiring arranged in one direction,
A switch transistor for controlling connection and disconnection between the sub-wiring and the main wiring is disposed in the circuit block,
The gate electrode of the switching transistor is disposed in the cell arrangement direction and parallel rows of circuit cell groups which receives the power supply from the same main wiring,
A semiconductor integrated circuit in which a power switch cell having the switch transistor is shared by two circuit cells orthogonal to the arrangement direction of the main wiring for supplying power to the power switch cell . The power switch cell shared by the two circuit cells includes two switch transistors having two gate electrodes parallel to each other,
The semiconductor region between the gate electrodes of the two is said is shared by two switch transistors, the semiconductor integrated circuit according to claim 1 which is connected to the main wiring. The main wiring, the through upper semiconductor region, and a semiconductor integrated circuit according to claim 2 disposed on the gate electrode and the parallel rows of the two. The power switch cell shared by the two circuit cells includes a single switch transistor having two gate fingers parallel to each other,
The semiconductor region between the gate finger portion of the two is, the semiconductor integrated circuit according to claim 1 which is connected to the main wiring. The main wiring, the through upper semiconductor region, and a semiconductor integrated circuit according to claim 4 which is arranged in the two gate finger portion and the parallel line. Two gate electrodes parallel to each other, a common first source / drain region formed in a semiconductor region between the two gate electrodes, and 2 separated on each side of the two gate electrodes Two switch transistors having two second source / drain regions ;
A main wiring of a power supply voltage supply line or a reference voltage supply line connected to the first source / drain region common to the two switch transistors and arranged in one direction;
With
Each of the two switch transistors controls power supply to adjacent circuit cells,
The two wiring direction of said two gate electrodes of the switching transistors, power switch cell and the wiring direction is set to the parallel line of the main line. A gate electrode having two gate finger portions parallel to each other, a first source / drain region formed in a semiconductor region between the two gate finger portions, and each side of the two gate finger portions A single switch transistor having two second source / drain regions separated by
A main wiring of a power supply voltage supply line or a reference voltage supply line connected to the first source / drain region of the single switch transistor and arranged in one direction;
With
The single switch transistor controls power supply to adjacent circuit cells,
The two wiring direction of the gate finger unit, a power supply switch cell and the wiring direction is set to the parallel line of the main line of the switching transistor. Logic circuit area,
Two gate electrodes parallel to each other, a common first source / drain region formed in a semiconductor region between the two gate electrodes, and 2 separated on each side of the two gate electrodes Two switch transistors having two second source / drain regions ;
A main wiring of a power supply voltage supply line or a reference voltage supply line connected to the first source / drain region common to the two switch transistors and arranged in one direction;
With
In the two switch transistors, the logic circuit region is connected to one of the second source / drain regions to control power supply to the logic circuit region, and the other second transistor is controlled independently of the control. It is possible to control power supply to other circuit cells adjacent to the source / drain region of
It said two of said two wiring direction of the gate electrode, the main wiring with power switch circuit cell and the wiring direction is set to the parallel line of the switching transistor. Logic circuit area,
A gate electrode having two gate finger portions parallel to each other, a first source / drain region formed in a semiconductor region between the two gate finger portions, and each side of the two gate finger portions A single switch transistor having two second source / drain regions separated by
A main wiring of a power supply voltage supply line or a reference voltage supply line connected to the first source / drain region of the single switch transistor and arranged in one direction;
With
The single switch transistor has one of the second source / drain regions connected to the logic circuit region to control power supply to the logic circuit region and the other second source / drain region. The power supply to the logic circuit area of the circuit cell adjacent to can be controlled,
The two wiring direction of the gate finger unit, the main wiring with power switch circuit cell and the wiring direction is set to the parallel line of the switching transistor.

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