JP3245663B2 - Logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit operable at a low voltage, and more particularly, to a high-speed operation realized by a low-threshold logic circuit comprising a low-threshold field-effect transistor during operation. The present invention relates to an improvement of a logic circuit that realizes low leakage characteristics by turning off a high threshold power control field effect transistor during operation.

[0002]

2. Description of the Related Art In recent years, low voltage operation of integrated circuits has been promoted in order to meet the demand for portability of various electronic devices.
As an example of this type of circuit, IEE "" 1V Hig
h-Speed Digital Circuit Technology With 0.5μm Mu
lti-Threshold CMOS ”Proceedings of IEEE A
SIC CONFERENCE PP.186-189, SEPT.199
MT-CMOS (Multi-Threshold
A CMOS (CMOS) circuit is shown in FIG.

In FIG. 1, G denotes a logic gate, which is a low-threshold P-channel MOSFET (LV _th -PMOS).
FET) · Q3, Q4 and N-channel MOSFET
(LV _th -NMOSFET) · Q5, Q6. One of the power supply terminals of the logic gate G is connected to a high-potential pseudo power supply line VDDV, and the other is connected to a low-potential pseudo power supply line GNDV. A high-threshold P-channel MOSFET (HV _th -PMOSFE) is provided between the pseudo power supply line VDDV and the real power supply line (high potential) VDD.
T: power control MOSFET). Q1 is connected, and the pseudo power supply line GNDV and the real power supply line GND (low potential: ground potential)
Between the high threshold N-channel MOSFET (HV _th
-NMOSFET: power control MOSFET) · Q2 is connected. Also, LV _th -PMOSFET · Q
3, the back gate (substrate potential) of Q4 is the actual power supply line VDD.
And the back gates of the LV _th -NMOSFETs Q5 and Q6 are connected to the real power supply line GND, and the HV _th -PM
The back gate of the OSFET Q1 is connected to the real power line VDD, and the back gate of the HV _th -NMOSFET Q2 is connected to the real power line GND. Note that, in the figure, SLA and SLB are control lines, and Q1 and Q
2 gates. The logic gate G is
Similarly, multiple connections are made.

In this MT-CMOS circuit, during normal operation, SLA is set to a low potential and SLB is set to a high potential. As a result, Q1 and Q2 become conductive, and VDDV and GN
DV is connected to VDD and GND. In this case, since the logic gate G is constituted by the MOSFETs Q3 to Q6 having a low threshold value, it is possible to operate at high speed even with a power supply voltage as low as about 1V. HV _th -MOSFET ・
Q1 and Q2 are V _th = 0.5 used in a general process.
To 0.7V. LV _th -MOSFET Q3-Q6
Is set to about _Vth = 0.2 to 0.3 V so that the transistor does not become normally on even if there is manufacturing variation. FIG. 6 shows the delay of the logic gate G at this time. Logic gate is set to HV _th
In the case of using a MOSFET, that is, in the case of a normal logic gate, the delay rapidly deteriorates when the power supply voltage is about 1 V. On the other hand, in the logic gate G composed of only the LV _th -MOSFET, the delay shows only a gradual deterioration. Therefore, at a power supply voltage of about 1 V, LV _th −
The logic gate G composed of only the MOSFET is HV _th -M
The speed is three times or more that of a logic gate constituted by an OSFET. As a result, in the MT-CMOS circuit shown in FIG. 5, the speed characteristic near the power supply voltage 1 V is different from the HV _th -MOS
It can be seen that this is greatly improved over a normal logic gate constituted by FETs.

However, the leakage current of the LV _th -MOSFET is 1000 times or more that of the HV _th -MOSFET, and the current consumption during non-operation (at the time of standby) cannot be ignored. That is, when a MOSFET with a low threshold value is used, there is a problem that the leakage current during standby is extremely large. Therefore, in the MT-CMOS circuit, the above-described problem is avoided by the following method.
That is, at the time of standby, SLA is set to a high potential,
The LB and a low potential, by blocking the Q1 and Q2, LV _th -MOSFET · logic gate G Q3 to Q6
Cuts the leakage current generated by In this case, HV _th −
Since the leakage current of only MOSFET · Q1 and Q2, becomes 1/1000 or less with respect to circuit power during standby is configured only with LV _th matrix memory. As described above, the use of the MT-CMOS circuit has an advantage that high-speed operation at a low power supply voltage and low power at a standby time can be simultaneously realized.

By the way, in this MT-CMOS circuit,
The pseudo power supply lines VDDV, GNDV, the pseudo power supply lines VDDV,
Power control MOSFETs Q1 and Q2 between GNDV and actual power supply lines VDD and GND and their control lines S
LA and SLB are required, and general CAD
Can not handle. Therefore, a standard cell (logic cell) compatible with MT-CMOS as shown in FIG. 7 has been proposed. This figure shows the standard cell SL
An example is shown in which 0 to SLn + 1 are arranged to configure an MT-CMOS circuit. This standard cell has pseudo power supply lines VDDV, GND in addition to power supply lines VDD, GND in the cell.
It has a DV and control lines SLA and SLB, and can be automatically connected just by arranging cells. Note that power cells SL0, SL0, which supply a voltage to each cell,
In SLn + 1, high threshold power control MOSFETs Q1 and Q2 controlled by control lines SLA and SLB are arranged. When this standard cell is used, HV _th
-By laying out the same layout as a normal CMOS logic cell composed of MOSFETs, the MT-C
A MOS circuit can be configured.

The standard cells SL1 to SLn include logic gates G1 to Gn each having a logic function. Logic gates G1~Gn is constituted by LV _th matrix memory. One of the power supply terminals of the logic gates G1 to Gn is connected to a high-potential pseudo power supply line VDDV, and the other is connected to a low-potential pseudo power supply line GNDV. The pseudo power supply lines VDDV and GNDV receive current supply from the real power supply lines VDD and GND via Q1 and Q2. Further, the actual power supply line VD held by the standard cells SL1 to SLn
D and GND have L at logic gates G1 to Gn.
_Vth- substrate potential fixing contacts CTV and C for obtaining substrate potentials of PMOSFET and NMOSFET
A TG is provided.

[0008]

However, in such a conventional MT-CMOS circuit, the actual power supply line VDD, the actual power supply line GND,
Four wirings of the pseudo power supply line VDDV and the pseudo power supply line GNDV are required, and the occupied area of the standard cells SL1 to SLn increases. Further, since a normal CMOS logic cell composed of HV _th -MOSFETs includes only a power supply line and a GND line, a circuit layout using this CMOS logic cell cannot be directly applied to an MT-CMOS circuit, and the Efficiency deteriorates.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem. It is an object of the present invention to reduce the area of a logic cell and to reduce the design efficiency of a logic circuit. Is to provide.

[0010]

SUMMARY OF THE INVENTION To achieve this object, the present invention provides a low threshold P channel and N channel.
A low-threshold logic circuit composed of a channel-type field-effect transistor; first and second pseudo power lines connected to one and the other of the power supply terminals of the low-threshold logic circuit; A high-threshold first field-effect transistor connected between the first line and the first real power supply line;
Circuit having a high threshold value second field effect transistor connected between the pseudo power supply line and the second real power supply line, the P-channel type field effect in the low threshold value logic circuit The back gate of the transistor is connected to the first pseudo power supply line, and the back gate of the N-channel field effect transistor in the low threshold voltage logic circuit is connected to the second pseudo power supply line. .

[0011]

Therefore, according to the present invention, the substrate potentials of the P-channel field-effect transistor and the N-channel field-effect transistor in the low threshold voltage logic circuit are
It is taken from the first pseudo power supply line and the second pseudo power supply line.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail based on embodiments. FIG. 1 shows an embodiment of the present invention. In the figure, G is a logic gate, and LV _th -PMOSFE
T • Q3, Q4 and LV _th -NMOSFET • Q5
Q6. One of the power supply terminals of the logic gate G is connected to a high-potential pseudo power supply line VDDV, and the other is connected to a low-potential pseudo power supply line GNDV. Then, H is applied between the pseudo power supply line VDDV and the actual power supply line VDD.
_Vth- PMOSFET Q1 is connected to the pseudo power supply line G
HV _th −NMOS FE between NDV and actual power supply line GND
T · Q2 is connected.

Here, the difference from the conventional circuit shown in FIG. 5 is that the back gates of the LV _th -PMOSFETs Q3 and Q4 are connected not to the actual power supply line VDD but to the pseudo power supply line VDDV, and the LV _th -NMOSFET The back gates of Q5 and Q6 are not real power lines GND but pseudo power lines GND
V is connected to V. HV _th -PMOS
The back gate of the FET Q1 is connected to the real power line VDD, the back gate of the HV _th -NMOSFET Q2 is connected to the real power line GND, and the control lines SLA and SLB are connected to the gates of Q1 and Q2. , And a plurality of logic gates G are similarly connected.
Is the same as the conventional circuit shown in FIG.

In this MT-CMOS circuit, as in the conventional circuit, during normal operation, SLA is set to a low potential and SL
B is set to a high potential. As a result, Q1 and Q2 conduct, and VDDV and GNDV are connected to VDD and GND. At this time, LV _th -PMOSFETs Q3, Q
The substrate potential of 4 is taken from VDDV, LV _th -NMOS
The substrate potentials of the FETs Q5 and Q6 are taken from GNDV. In this case, the logic gate G is a low threshold MOSFE
Since it is composed of T.Q3 to Q6, it can operate at high speed even with a low power supply voltage of about 1V. Also,
During standby, the HV _th -PMOSFETs Q1, Q
By turning off 2, a low leak characteristic is realized.

FIG. 2 is a diagram showing the MT-CMOS circuit as an actual layout pattern. That is, the standard cells SL0 'to SLn + 1' are arranged and the MT-C
1 shows an example in which a MOS circuit is configured. The standard cells SL1 'to SLn' include logic gates G1 to Gn each having a logic function. Logic gates G1 to G
n is constituted by an LV _th -MOSFET. One of the power supply terminals of the logic gates G1 to Gn is connected to a high-potential pseudo power supply line VDDV, and the other is connected to a low-potential pseudo power supply line GN.
DV is connected. Pseudo power supply lines VDDV, GNDV
Receives current supply from the real power supply lines VDD and GND held by the power cells SL0 ′ and SLn + 1 ′ via Q1 and Q2. In addition, the standard cells SL1 'to SL
The pseudo power supply lines VDDV and GNDV held by n ′ are connected to LV _th -PMOSF in the logic gates G1 to Gn.
Substrate potential fixing contacts CTV and CTG for obtaining the substrate potential of the ET and the NMOSFET are provided.

In this MT-CMOS circuit, pseudo power supply lines VDDV, G are provided in standard cells SL1 'to SLn'.
It is only necessary to provide two wirings of NDV, that is, the actual power supply lines VDD and GND can be omitted, and the area of the standard cells SL1 'to SLn' can be reduced. In this embodiment, as a result of the actual layout, the conventional M
It has been found that the area can be reduced by about 15% as compared with the T-CMOS circuit. According to the present embodiment, the standard cells SL1 ′ to SLn ′ are HV _th -MOSFETs.
Since the configuration is the same as a normal logic cell configured with
The circuit layout using the normal logic cells can be applied as it is, and the design efficiency does not deteriorate.

FIG. 3 shows an example of a layout pattern when a normal CMOS logic cell composed of HV _th -MOSFET is used. G1 'to Gn' are normal CMOS logic gates. SL0 ″ and SLn + 1 ″ are normal power cells. In this case, the logic gates G1 'to G1
By changing the impurity concentration of the transistor in n ', the threshold value is lowered, and the power cells SL0 ", SLn + 1"
Is replaced with the power cells SL0 'and SLn + 1' shown in FIG. 2, an MT-CMOS circuit similar to that of FIG. 2 can be obtained.
From this, as shown in FIG.
The threshold value of a transistor in a circuit block or macro cell (functional circuit block) BL designed by MOS is lowered by changing the impurity concentration, and HV _th -MOS
By adding the FETs Q1 and Q2 and the inverter INV, the MT-CMOS circuit according to the present invention can be made to have characteristics of low power supply voltage, high speed, and low leakage during standby.

In the above-described embodiment, the logic gates G1 to Gn may be various logic gates (for example, an AND gate, an OR gate, a NAND gate, a NOR gate, etc.) and may have a configuration in which a plurality of various logic gates are connected. . In the above-described embodiment, Q1, Q2,
The transistors forming the logic gates G1 to Gn are MOS
Although the FET is used, that is, an insulated gate field effect transistor is used, a junction field effect transistor may be used. In addition, power supply cells SL0 'and SLn + 1'
Need not necessarily be provided at the end, and may be arranged at any position.

[0019]

As apparent from the above description, according to the present invention, the back gate of the P-channel field effect transistor in the low threshold voltage logic circuit is connected to the first pseudo power supply line, Since the back gate of the N-channel field effect transistor in the low threshold logic circuit is connected to the second pseudo power supply line, the P channel field effect transistor and the N channel type in the low threshold logic circuit are connected. The substrate potential of the field effect transistor is taken from the first pseudo power supply line and the second pseudo power supply line, so that the actual power supply line can be omitted from the logic cell, and the area of the logic cell can be reduced. Will be able to do it. Further, the logic cell is set to HV _th -MOSFE
Since the configuration can be the same as that of a normal logic cell formed by T, the circuit layout using the normal logic cell can be applied as it is, and the design efficiency does not deteriorate.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing the MT-CMOS circuit shown in FIG. 1 in an actual layout pattern.

FIG. 3 shows a normal CM composed of HV _th -MOSFETs
FIG. 9 is a diagram illustrating a layout pattern when an OS logic cell is used.

FIG. 4 is a diagram showing an application example of the present invention to a functional circuit block already designed in the normal CMOS in the past.

FIG. 5 is a diagram illustrating a conventional MT-CMOS circuit.

FIG. 6 is a diagram showing a comparison of delays of logic gates.

FIG. 7 is a diagram showing a conventional circuit example using a standard cell compatible with MT-CMOS.

[Explanation of symbols]

Q1 Power control MOSFET (H
_Vth- PMOSFET) Q2 Power control MOSFET (H
_Vth- NMOSFET) Q3, Q4 P-channel MOSFET (L
_Vth- PMOSFET) Q5, Q6 N-channel MOSFET (L
_Vth- NMOSFET) VDD Real power line (high potential) GND Real power line (low potential) VDDV Pseudo power line (high potential) GNDV Pseudo power line (low potential) SLA, SLB Control line CTV, CTG Substrate potential fixing contact SL0'-SLn + 1 'Standard cells G1-Gn Logic gate

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Junzo Yamada 1-6, Uchisaiwai-cho, Chiyoda-ku, Tokyo Nippon Telegraph and Telephone Corporation (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 19 / 0948

Claims (3)

(57) [Claims] 1. A low-threshold logic circuit comprising low-threshold P-channel and N-channel field effect transistors, and a first power supply terminal connected to one and the other of a power supply terminal of the low-threshold logic circuit. And a second pseudo power supply line; a high threshold first field effect transistor connected between the first pseudo power supply line and the first real power supply line;
A high threshold second field effect transistor connected between the pseudo power supply line and the second real power supply line, wherein the P-channel type electric field in the low threshold value logic circuit is provided. The back gate of the effect transistor is connected to the first pseudo power supply line, and the back gate of the N-channel field effect transistor in the low threshold voltage logic circuit is connected to the second pseudo power supply line. Logic circuit to be characterized. 2. A first to N-th low threshold logic circuit comprising P-channel and N-channel field effect transistors having low thresholds, and a first to N-th low threshold logic circuit. First and second pseudo power supply lines connected to one and the other of the power supply terminals; and a high threshold first power supply connected between the first pseudo power supply line and the first real power supply line. A logic circuit comprising a field-effect transistor and a high-threshold second field-effect transistor connected between the second pseudo power supply line and the second real power supply line; The back gate of the P-channel type field effect transistor in the N low threshold logic circuit is the first gate.
And a back gate of an N-channel field effect transistor in the first to Nth low threshold voltage logic circuits is connected to the second power supply line.
A logic circuit, wherein the logic circuit is connected to a pseudo power supply line. 3. The device according to claim 1, wherein the low-threshold P-channel and N-channel field-effect transistors and the high-threshold first and second field-effect transistors are MOSFETs. Logic circuit.