JPH1051296A - Logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize, to reduce the power consumption and to attain a high-speed processing and a low-voltage circuit operation by combining two kinds of MOS transistors(TRs) with high and low threshold voltages and connecting the drain connecting points in common by a local power supply line. SOLUTION: A threshold voltage of TRs QN11, QN21 is set higher until a sub-threshold leak current is allowed, on the assumption that the TRs are controlled to be nonconductive. Thus, the power consumption in the standby state is suppressed. The absolute value of the threshold voltage of other N- channel MOS TRs is set lower, to attain a high-speed processing and a low- voltage circuit operation in the operating state of an LSI. Furthermore, drain contact points of the TRs QN11, QN21 are connected in common by a metal used for wiring in the LSI or a local power supply line LPL of a diffusion layer. Thus, the TRs QN11, QN21 act as TRs whose channel width is a sum of channel widths of both, thereby making the chip area small.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor MOS logic circuit capable of operating at a low voltage and operating at high speed, and more particularly to using a high-threshold MOS transistor while suppressing an increase in power consumption in a standby state. And a logic circuit for reducing the area.

[0002]

2. Description of the Related Art In order to reduce the size and weight of portable devices, there is an increasing demand for operating an LSI with a single battery. Inevitably, the power supply voltage is reduced from the conventional 5 V to 3 V to about 1 V. However, as the power supply voltage decreases, the operating speed of the LSI rapidly decreases. This is mainly due to an increase in the delay time of the logic gate constituting the LSI. The delay time of a CMOS logic gate strongly depends on the threshold voltage (V _TH ) and the power supply voltage (Vcc) of the MOS transistor constituting the CMOS logic gate. That is, “Vcc−V _TH ”
The delay time increases significantly with the decrease of.

[0003] Such a gate delay can be shortened by lowering the threshold voltage, but there is a problem that the sub-threshold leakage current increases exponentially as the threshold voltage decreases. Here, the sub-threshold leakage current is a useless current flowing between the drain and source of the MOS transistor in an off state. Since the power consumption of the LSI in the standby state is determined by the sub-threshold leakage current, the power consumption of the LSI used in a portable device is particularly high.
Therefore, it is required that the sub-threshold leakage current be small.

In order to meet such a demand, there has been proposed a method of forming a logic gate by combining MOS transistors having different threshold voltages. For example, "Saburo Takashima
The semiconductor device is disclosed in Japanese Patent Application Laid-Open No. 6-208790.
Hereinafter, this technique will be described with reference to FIG.

FIG. 7A is a circuit diagram showing a configuration of a two-input NAND gate. IN (1) and IN (2) are input contacts, OUT is an output contact, QN (1) and QN (2) are N
chMOS transistors, QP (1) and QP (2) are Pch
A MOS transistor and Vcc are a power supply. The threshold voltage of the transistor QN (1) is set higher than that of the transistor QN (2) (encircled in the figure). Here, it is assumed that one input contact IN (1) is controlled to an “L” (low voltage) level (the transistor QN (1) is controlled to be in an off state) during standby of the LSI. By setting the threshold voltage of the transistor QN (1) high enough to allow the threshold leak current, power consumption during standby can be suppressed to a desired value. The remaining transistor QN
(2), QP (1) and QP (2) have no restrictions on the threshold voltage, and by reducing the absolute value of the threshold voltage, it is possible to achieve high speed and low voltage in the operating state of the LSI. The reason why the absolute value is denied here is that the threshold voltage of the PchMOS transistor in the case of the enhancement type becomes a negative value.

FIG. 7B is a circuit diagram showing a configuration of a two-input NOR gate. IN (1) 'and IN (2)' are input contacts, OUT 'is an output contact, QN (1)' and QN
(2) 'is an Nch MOS transistor, QP (1)' and Q
P (2) 'is a PchMOS transistor. Transistor QP (1) ′ has a threshold voltage of transistor QP
(2) It is set higher than '(circled in the figure). Here, it is assumed that one input contact IN (1) ′ is controlled to “H” (high voltage) level (transistor QP (1) ′ is turned off) during the standby state of the LSI. , Transistor QP (1) ′ to the extent that a subthreshold leakage current can be tolerated.
, The power consumption during standby can be suppressed. The remaining transistor QP
(2) ', QN (1)', and QN (2) 'have no restriction on the threshold voltage, and by reducing the threshold voltage in absolute value, it is possible to achieve high speed and low voltage in the operating state of the LSI. .

[0007] A special example of a logic gate is an inverter. This can be achieved by setting the threshold voltage of the Nch or Pch MOS transistor among the MOS transistors constituting the inverter high in absolute value.

[0008]

FIG. 7 (a)
In the above, the input contact IN (1) is controlled to the "L" level in the standby state of the LSI as described above, but is controlled to the "H" level during the operation of the LSI. Therefore, at this "H" level, transistor QN
(1) is a conduction state, and the gate delay of the input contact IN (2) determines the operation performance of the LSI. This input contact IN
The gate delay of (2) is based on the transistors QP (2) and QN
This can be shortened by setting the threshold voltage of (2) low.

However, the conducting transistor QN
(1) has a finite conduction resistance, and the resistance is such that the potential of the output contact OUT of the logic gate changes from “H” level to “L”.
When changing to a level, it hinders. This is a problem particularly when a large load capacitance is connected to the output contact of the logic gate. To suppress the effect of the conduction resistance of the transistor QN (1) on the gate delay, the transistor QN (1)
The channel width of N (1) may be set large, but this will increase the occupation area of the logic gate. Since the logic gate is the main circuit constituting the LSI, this
This is a problem because it leads to an increase in the size of the SI chip.

Although the NAND gate of FIG. 7A has been described above, the NOR gate of FIG. 7B has a similar problem due to the effect of the conduction resistance of the transistor QP (1) '.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an object of the present invention is to reduce power consumption during standby in a logic circuit composed of MOS transistors having different threshold voltages while simultaneously using a low power supply voltage. It is an object of the present invention to provide a logic circuit which can operate at high speed and can reduce an occupied area.

[0012]

According to a first aspect of the present invention, there is provided a logic circuit including at least two or more NAND gates.
A drain contact of the Nch MOS transistor is commonly connected between the NAND gates each having a gate electrode of the S transistor connected to the same circuit contact;
The threshold voltage of the MOS transistor is set higher than those of the other Nch MOS transistors.

The logic circuit according to the second invention has at least NA
In a logic circuit including an ND gate and an inverter,
The NAND gate in which a source electrode in the NAND gate is connected to ground and a gate electrode of an NchMOS transistor and an input contact of the inverter are connected to the same circuit contact.
Between the gate and the inverter, the drain contact of the NchMOS transistor and the output contact of the inverter are commonly connected, and the threshold voltage of the NchMOS transistor and the threshold voltage of the NchMOS transistor in the inverter are set to those of other NchMOS transistors. It was configured to be set higher than

A logic circuit according to a third aspect of the present invention is the logic circuit including at least two or more NOR gates, wherein the gate electrode of a Pch MOS transistor whose source contact is connected to a power supply is connected to the same circuit contact. , The drain contacts of the PchMOS transistors are commonly connected, and the threshold voltage of the PchMOS transistor is set to be higher in absolute value than that of the other PchMOS transistors.

The logic circuit according to the fourth invention has at least NO
In a logic circuit including an R gate and an inverter, a source contact in the NOR gate has a Pch connected to a power supply.
A drain electrode of the Pch MOS transistor and an output contact of the inverter are commonly connected between the NOR gate and the inverter, wherein a gate electrode of a MOS transistor and an input contact of the inverter are connected to the same circuit contact; The threshold voltage of the PchMOS transistor and the threshold voltage of the PchMOS transistor in the inverter are set to be higher in absolute value than those of the other PchMOS transistors.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a circuit diagram showing a configuration of a logic circuit according to a first embodiment of the present invention. This is because in the M-input NAND gate A and the N-input NAND gate B,
This is an example in which NchMOS transistors having a high threshold voltage are shared so that the channel width can be reduced. IN
(1m) (m = 1, 2,..., M: the same applies hereinafter) and I
N (2n) (n = 1, 2,..., N: the same applies hereinafter) is an input contact, and OUT (1) and OUT (2) are output contacts. QN (1m) and QN (2n) are NchMOS transistors, and QP (1m) and QP (2n) are PchMOS transistors. Here, the transistors QN (11) and Q
N (21) is set to a higher threshold voltage than other NchMOS transistors (circled in the figure).

Here, control signal φ is controlled to "L" level during standby of the LSI (transistor QN
(11) and QN (21) are controlled to be in an off state), and the transistors QN (11) and QN (2) are controlled to the extent that a subthreshold leakage current can be tolerated.
By increasing the threshold voltage of 1), it is possible to suppress the power consumption in the styvan state. There is no restriction on the threshold voltage of the remaining NchMOS transistors and PchMOS transistors. By setting the threshold voltages low in absolute value, it is possible to achieve high speed and low voltage in the operating state of the LSI. LPL (1) is a local power line that connects the drain contacts of the transistors QN (11) and QN (21) to each other. There is no particular limitation on the method of realizing the local power supply line LPL (1), and the local power supply line LPL (1) can be realized by a metal or a diffusion layer used as a wiring in the LSI.

Now, as is apparent from the circuit of FIG. 1, the transistors QN (11) and QN (21) are simultaneously switched by the control signal φ. Further, since the drain contacts of both transistors QN (11) and QN (21) are commonly connected by local power supply line LPL, the channel width of transistors QN (11) and QN (21) is the sum of the channel widths of both transistors. It functions as a large-sized transistor. As a result, the channel width of transistor QN (11) can be reduced if the requirement for the gate delay of input contact IN (1m) of M-input NAND gate A is constant. The same applies to the transistor QN (21). However, if the outputs of M-input NAND gate A and N-input NAND gate B simultaneously change from “H” level to “L” level, both transistors QN
Decreasing the channel width of (11) and QN (21) causes an increase in delay time, but such cases are rare.

[Second Embodiment] FIG. 2 shows a special case of the first embodiment in which the N-input NAND circuit shown in FIG.
FIG. 3 is a diagram illustrating a logic circuit having a configuration in which a gate B is replaced with an inverter C. In the case of inverter C, local power supply line LPL
(1) is connected to the output contact OUT (2) of the inverter C, but the operation and effect are the same as those in the first embodiment.

[Third Embodiment] In a logic circuit combining two NAND gates or a logic circuit combining a NAND gate and an inverter, a high threshold voltage N
FIG. 3 shows an example of a logic circuit that can easily realize the common use of chMOS transistors. NAND gates 1 and 2 have two inputs,
These and the circled numbers shown on the inverter 3 are for distinguishing the input contacts. 4 is also an inverter. ○
NchMOS whose gate electrode is connected to the input contact 1
The transistor has a higher threshold voltage than other MOS transistors, and its source is connected to ground.

FIGS. 3A and 3B show logic circuits for obtaining a complementary signal from the input signal IN. The control signal φ is L
The SI is controlled to the “L” level during standby and to the “H” level during operation. In operation, NAND gates 1 and 2 perform an operation of outputting complementary output signals (when one potential is at "H" level, the other potential is at "L" level). In a logic circuit for creating such a complementary signal, 2
The outputs of the two NAND gates 1 and 2 do not change from “H” level to “L” level at the same time.
Since the high threshold voltage NchMOS transistors of the ND gates 1 and 2 do not turn on at the same time, a large effect of area reduction can be obtained by applying the circuit shown in the first embodiment here.

FIG. 3C shows an example of a logic circuit when the second embodiment is applied. Again, during LSI operation,
Control signal φ is controlled to “H” level. Throughout the operation period of this LSI, the inverted output contact * OU of the inverter 3
T2 maintains the “L” level. In such a circuit, by applying the circuit described in the second embodiment here, there is a great effect of reducing the area.

[Fourth Embodiment] FIG. 4 shows a fourth embodiment of the present invention.
FIG. 3 is a circuit diagram showing a configuration of a logic circuit according to the embodiment. This is an example in which a high threshold voltage PchMOS transistor is shared between the M-input NOR gate D and the N-input NOR gate E, so that the channel width can be reduced. IN (1m) 'and IN (2n)' are input contacts, OU
T (1) 'and OUT (2)' are output contacts. QN
(1m) 'and QN (2n)' are NchMOS transistors, and QP (1m) 'and QP (2n)' are PchMOS transistors. Here, the transistor PN (11) ′
And QP (21) 'are set to a higher threshold voltage than other NchMOS transistors.

Here, it is assumed that the inversion control signal * φ is controlled to the “H” level during the standby of the LSI (the transistors QP (11) ′ and QP (21) ′ are controlled to be off). In addition, by increasing the threshold voltages of the transistors QP (11) ′ and QP (21) ′ to such an extent that the sub-threshold leakage current can be tolerated, it is possible to suppress the power consumption in the styban state. Remaining N
There is no restriction on the threshold voltage of the chMOS transistor and the PchMOS transistor. By setting the threshold voltage to be low in absolute value, it is possible to achieve high speed and low voltage in the operation state of the LSI. LPL (2) is a local power supply line that connects the drain contacts of transistors QP (11) ′ and QP (21) ′ to each other. Transistors QP (11) ′ and QP (2) can be provided without increasing gate delay by such a local power supply line LPL (2).
Reducing the channel width of 1) ′ is equivalent to the first method described above.
This is the same as the embodiment.

[Fifth Embodiment] FIG. 5 is a diagram showing a logic circuit in which the N-input NOR gate E in FIG. 4 is replaced with an inverter F as a special case of the fourth embodiment. In the case of inverter F, local power supply line LPL
(2) is connected to the output contact OUT (2) ′ of the inverter F, but the operation and effect are the same as those in the fourth embodiment.

[Sixth Embodiment] In a logic circuit combining two NOR gates or a logic circuit combining a NOR gate and an inverter, a high threshold voltage PchM
FIG. 6 shows an example of a logic circuit which can easily realize the common use of the OS transistor. The NOR gates 5 and 6 have two inputs, and the numbers marked with a circle on the inverter 7 are used to distinguish input contacts. 8 is an inverter. ○ attached 1
The Pch MOS transistor whose gate electrode is connected to the input contact has a higher threshold voltage than other MOS transistors, and its source is connected to the power supply.

FIGS. 6A and 6B show logic circuits for obtaining a complementary signal from the input signal IN. Inversion control signal *
φ is controlled to “H” level during standby of the LSI and to “L” level during operation. In operation, NOR gates 5 and 6 perform an operation of outputting complementary output signals. In the logic circuit for generating such a complementary signal, the outputs of the two NOR gates 5 and 6 do not simultaneously change from “L” level to “H” level, that is, the high threshold voltage of both NOR gates 5 and 6 Are not turned on at the same time, the application of the circuit described in the fourth embodiment to this embodiment provides a great effect of area reduction.

FIG. 6C shows an example of a logic circuit when the fifth embodiment is applied. Again, during LSI operation,
Inversion control signal * φ is controlled to the “L” level. This L
During the operation period of SI, the output contact OU of the inverter 7
T2 maintains the “H” level. By applying the circuit described in the fifth embodiment to such a circuit,
There is a great effect of area reduction.

In the first to sixth embodiments, the drain contact of the MOS transistor having a high threshold voltage is connected between the two logic gates via the local power supply lines LPL (1) and LPL (2) and shared. Although an example has been shown, a similar configuration can be realized between three or more logic gates, and the effect of reducing the occupied area can be obtained similarly.

[0030]

As described above, according to the present invention, in a logic circuit capable of realizing low power consumption, low voltage, and high speed, that is, a logic circuit in which a high threshold voltage MOS transistor and a low threshold voltage MOS transistor are combined. Since the drain contacts of the MOS transistors having the same polarity and having the same high threshold voltage of different logic gates are commonly connected, the MOS transistors having the high threshold voltage are shared, so that the respective channel widths can be reduced. There is an advantage that the occupied area can be reduced. For this reason, if the logic circuit of the present invention is applied to an LSI in which power consumption during standby is a major problem, such as in a portable device, the problem can be solved, the chip area can be reduced, and the yield is greatly improved. There is.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a logic circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a logic circuit according to a second embodiment of the present invention.

FIG. 3 is a logic diagram of a third embodiment showing an application example of the logic circuits of the first and second embodiments.

FIG. 4 is a circuit diagram showing a configuration of a logic circuit according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a logic circuit according to a fifth embodiment of the present invention.

FIG. 6 is a logic diagram of a sixth embodiment showing an application example of the logic circuits of the fourth and fifth embodiments.

FIG. 7 is a circuit diagram showing a configuration of a conventional logic circuit.

[Explanation of symbols]

 A: M-input NAND gate B: N-input NAND gate C: Inverter D: M-input NOR gate E: N-input NOR gate F: Inverter

Claims (4)

[Claims] In a logic circuit including at least two or more NAND gates, a gate electrode of an Nch MOS transistor whose source contact is connected to ground is connected between the NAND gates whose gate electrodes are connected to the same circuit contact.
The drain contacts of the MOS transistors are commonly connected, and the threshold voltage of the N-channel MOS transistor is
A logic circuit characterized by being set higher than that of an S transistor. 2. A logic circuit including at least a NAND gate and an inverter, wherein the gate electrode of an NchMOS transistor whose source contact in the NAND gate is connected to ground and the input contact of the inverter are connected to the same circuit contact. A drain connection of the NchMOS transistor and an output contact of the inverter are commonly connected between the NAND gate and the inverter;
A logic circuit, wherein a threshold voltage of a chMOS transistor and a threshold voltage of an NchMOS transistor in the inverter are set higher than those of other NchMOS transistors. 3. A logic circuit including at least two NOR gates, wherein a source contact is connected to a power supply connected to a power supply.
The PchMO is connected between the NOR gates whose gate electrodes are connected to the same circuit contact.
A logic circuit, wherein drain contacts of S transistors are commonly connected, and a threshold voltage of the PchMOS transistor is set to be higher in absolute value than that of another PchMOS transistor. 4. In a logic circuit including at least a NOR gate and an inverter, a source contact in the NOR gate is connected to a power supply, and a gate electrode of a PchMOS transistor connected to a power supply and an input contact of the inverter are connected to the same circuit contact. A drain connection of the PchMOS transistor and an output contact of the inverter are commonly connected between the NOR gate and the inverter, and the PchMO
Threshold voltage of S transistor and PchM in the inverter
A logic circuit wherein the threshold voltage of the OS transistor is set to be higher in absolute value than that of the other PchMOS transistors.