JP2011018438A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an SRAM (Static Random Access Memory) which has low power consumption and is operated by low voltage of 1 V or less while securing static noise margin.SOLUTION: A semiconductor device includes static type memory cells each of which comprises: first and second drive MOS transistors; transfer MOS transistors; and load MOS transistors. The semiconductor device further includes; a pair of bit lines; an input/output circuit; a logic circuit; and a memory power source line for supplying a power source potential to the static type memory cells formed in an array state, wherein the first transfer MOS transistor is connected to one of the pair of bit lines, the second transfer MOS transistor is connected to the other of the pair of bit lines, an input/output circuit power source of the input/output circuit and a core power source used for the logic circuit are input to the semiconductor device, the memory power source line is connected to a second operation potential point, and is supplied with a power source from the core power source.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for an SRAM (Static Random Access Memory) that secures an operation margin during writing and operates at a low voltage and low power.

  In recent years, more and more devices have been ported, and the demand for lower power consumption of large-scale semiconductor integrated circuits (LSIs) has increased. Therefore, LSI technology that operates at a voltage of 1 V or less is required. In the future, there is an increasing demand for lowering the operating voltage from LSIs operating at an operating voltage of about 0.9V, and it is considered that an LSI operating at an operating voltage of about 0.5V will be required.

  When the LSI is operated at a low voltage, the threshold voltage of the MOS transistor is lowered so that an operating current can be obtained even at a low voltage. However, when the threshold voltage of the MOS transistor in the SRAM memory cell is lowered, the static noise margin, which is a margin for noise, is lowered, and the read operation becomes unstable. This is shown in (a) and (b) of FIG. A double-headed arrow line indicated by reference numeral 11 in FIG. 24A is a static noise margin of a conventional memory cell in which the threshold value is not lowered. On the other hand, as shown in FIG. 24B, the static noise margin 12 of the memory cell whose threshold is lowered is small.

  FIG. 2 is a circuit configuration diagram of an SRAM memory cell. SRAM memory cells consist of N-channel MOS transistors (drive MOS transistors) N1, N2 with their sources connected, and P-channel MOS transistors (load MOS transistors) with their drains connected to the drains of the drive MOS transistors N1, N2, respectively. P1, P2, gates connected to the word line WL, bit lines BL, / BL (here, the symbol “/” is used in place of the bar symbol indicating inversion) and the driving MOS transistors N1, N2 N-channel MOS transistors (transfer MOS transistors) N3 and N4 having source / drain paths connected to the drains of the two transistors.

  In FIG. 2, reference numeral 4 is the source line of the load MOS transistors P1 and P2, that is, the power line of the memory cell, 5 is the source line of the drive MOS transistors N1 and N2, that is, usually the ground line of the memory cell, and Data holding node (storage node) of the cell, Vw is the voltage of the word line WL, Vb1 and Vb2 are the voltages of the bit lines BL and / BL, Vddm is the voltage of the power line 4 of the memory cell, and Vssm is the ground line of the memory cell 5 voltage. Vn1 and Vn2 are the voltages of the data holding nodes 6 and 7, respectively, and the data is “1” or “0”, which are opposite to each other.

Next, a method conventionally employed in order to prevent the static noise margin of the SRAM memory cell having such a configuration from being lowered even when the threshold value of the MOS transistor is lowered will be described.
In order not to lower the static noise margin of the SRAM memory cell even if the threshold value of the MOS transistor is lowered, the conductance of the drive MOS transistors N1 and N2 of the memory cell is compared with the conductance of the transfer MOS transistors N3 and N4. It needs to be bigger. In order to achieve this, a voltage Vdd ′ higher than the high-level voltage Vdd of the word line WL is applied as the voltage Vddm of the power line 4 of the memory cell connected to the sources of the load MOS transistors P1 and P2. The voltage applied to the gate electrodes of the driving MOS transistors N1 and N2 may be made higher than the voltage applied to the gate electrodes of the transfer MOS transistors N3 and N4. As a result, the conductances of the driving MOS transistors N1 and N2 are increased, and the static noise margin is also increased as indicated by reference numeral 13 in FIG.

  Therefore, in a conventional SRAM memory intended for low voltage operation, as disclosed in Japanese Patent Laid-Open No. 9-185886, a memory cell in which the power supply line voltage of the entire memory cell array is increased or read only at the time of reading. That is, a high voltage is applied to the power supply line of the memory cell selected at the time of reading.

  The reason why the voltage Vddm of the power supply line of the memory cell is boosted only at the time of reading is that the operation margin at the time of writing decreases as the ratio of the conductance of the load MOS transistors P1 and P2 and the conductance of the driving MOS transistor increases. For this reason, conventionally, the voltage Vddm of the power supply line 4 of the selected memory cell or memory cell array is boosted only at the time of reading, and the operation margin at the time of writing is suppressed from decreasing.

  In Japanese Patent Laid-Open No. 9-185886, the power supply potential of the memory cell applied to the memory cell is steadily changed to a peripheral circuit or the like as long as the potential is such that the write operation is possible. It is described that it can be set higher than the power supply potential.

In addition, in a normal SRAM memory cell as well as a low voltage operation, in order to increase the static noise margin at the time of reading, it is necessary to make the conductance of the driving MOS transistor larger than the conductance of the transfer MOS transistor as described above. For this reason, the gate width of the driving MOS transistor is manufactured larger than the gate width of the transfer MOS transistor.
In particular, as disclosed in Japanese Patent Laid-Open No. 2001-28401, in the memory cell layout used in the conventional SRAM memory shown in FIG. 9, the diffusion regions of the driving MOS transistor and the transfer MOS transistor are formed without bending. Nevertheless, the diffusion region was not a simple rectangle due to the difference in the gate width size. In FIG. 9, reference numeral 33 is a contact, 34 is an N-type diffusion layer serving as the source and drain of N-channel MOS transistors (hereinafter referred to as NMOS transistors) N1, N2, N3, N4, and 35 is a poly-layer serving as a gate electrode. Silicon, 36 is one SRAM memory cell region, and 39 is a P-type diffusion layer which becomes sources and drains of P-channel MOS transistors (hereinafter referred to as PMOS transistors) P1, P2, P3 and P4.

  Further, in Japanese Patent Laid-Open No. 2001-28401 of the same conventional example, the transfer MOS transistors N3, N4 are compared with the drive MOS transistors N1, N2 in order to set the ratio of the gate width of the drive MOS transistor to the transfer MOS transistor to 1. This is realized by changing the manufacturing process such as increasing the cell ratio by increasing the oxide film thickness or by reducing the impurity concentration in the low-concentration drain region for reducing the electric field, thereby increasing the so-called cell ratio. It is described.

JP-A-9-185886 JP 2001-28401 A

  However, according to the conventional method of applying a high voltage to the power supply line of the memory cell array only at the time of reading, the power supply voltage Vddm of the memory cell array changes to a desired voltage Vdd ′ higher than the power supply voltage Vdd of the peripheral circuit. Takes time. Furthermore, it consumes extra power required to charge and discharge the power supply line to raise and lower the voltage of the power supply line of the memory cell array, and although it is an SRAM circuit that operates at a low voltage, low power consumption can be realized. Disappear. This increases the power consumption to some extent even when boosting only the power supply voltage Vddm of the selected memory cell to be read. In addition, when the power supply voltage of the memory cell is steadily higher than the power supply voltage of the peripheral circuit or the like, the ground voltage of the memory cell is set to be higher than the ground voltage of the peripheral circuit during writing and standby, It is necessary to set the ground voltage of the memory cell to be the same as the ground voltage of the peripheral circuit only during the read operation. Consequently, the voltage between the power supply lines needs to be raised or lowered relatively, and the extra power required for charging / discharging the power supply lines is required. Will consume.

  Further, by forming the diffusion regions 34 and 37 and the polycrystalline silicon (polysilicon) layer 35 linearly as shown in FIG. 9 to make a highly symmetric layout, the previous symmetry is reduced and the polysilicon is also formed. Compared to the bent layout, the manufacturing variation can be suppressed. However, in this layout, the gate width W1 of the driving MOS transistors N1 and N2 and the gate width W3 of the transfer MOS transistors N3 and N4 are different to adjust the conductance, and the diffusion regions 34 and 37 are completely formed as shown in FIG. I didn't want to make it rectangular. Actually, by setting the ratio W1 / W3 of the gate width W1 of the drive MOS and the gate width W3 of the transfer MOS to 1.5-2, the ratio of the conductance of the drive MOS transistor and the transfer MOS transistor is adjusted to reduce static noise. A margin was secured. For this reason, although variations at the time of manufacture are reduced as compared with SRAM memory cells before adopting this layout, it is considered that there are more variations than when a completely rectangular diffusion region is formed.

  Further, as described in Japanese Patent Laid-Open No. 2001-28401 of the same conventional example, in order to set the gate width ratio W1 / W3 to 1, the impurity concentration in the low-concentration drain region is changed to make a difference in driving force. If the manufacturing process is changed by increasing the cell ratio or the like, the manufacturing conditions become complicated, resulting in a decrease in yield or an increase in manufacturing steps, resulting in high costs.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device suitable for an SRAM memory that can achieve both low voltage operation with a static noise margin and low power consumption.

  It is also an object of the present invention to provide a semiconductor memory device that enables a rectangular layout of the diffusion region by setting the gate width ratio of the driving MOS transistor and the transfer MOS transistor to 1 while ensuring a static noise margin, and having a small manufacturing variation. It is.

  In order to solve the above-described problems, a semiconductor device according to the present invention includes N-channel first and second drive MOS transistors, N-channel first and second transfer MOS transistors, and a P-channel first. Static type memory cells composed of first and second load MOS transistors are formed in an array on a semiconductor substrate, and source electrodes of the first and second drive MOS transistors are connected to a first operating potential point. A semiconductor device in which the source electrodes of the first and second load MOS transistors are connected to a second operating potential point, and the potential of the second operating potential point is the first in the read operation state and the write operation state of the memory cell. And a potential higher than the high level potential applied to the gate electrode of the second transfer MOS transistor, and the potential at the first operating potential point is memorized. The read operation state and the write operation state of the cell are the same, the potential of the second operation potential point is the same in the read operation state and the write operation state of the memory cell, and a pair of bit lines, an input / output circuit, and a logic A first power MOS transistor connected to one of the bit line pair, and a second power transfer MOS transistor having a circuit and a memory power supply line for supplying a power supply potential to static memory cells formed in an array. The transistor is connected to the other of the bit line pair, the input / output circuit power supply of the input / output circuit and the core power supply used for the logic circuit are input to the semiconductor device, and the memory power supply line is connected to the second operating potential point. It is connected and power is supplied from a core power supply.

  According to the present invention, it is possible to realize an SRAM that secures a static noise margin and operates with low power consumption and a low voltage of 1 V or less.

2 is a block diagram showing a memory cell array and peripheral circuits in Embodiment 1, and a power supply configuration supplied to them. FIG. 1 is a circuit configuration diagram of an SRAM memory cell to which the present invention is applied. FIG. FIG. 6 is a diagram illustrating a change in potential of each part of the memory cell during the memory operation in the first embodiment. It is a figure which shows the change of the voltage of each part of the memory cell at the time of memory operation in the case of boosting only at the time of reading in the conventional example. FIG. 6 is a block diagram showing a memory cell array and peripheral circuits in Embodiment 2, and a power supply configuration supplied to them. FIG. 10 is a block diagram illustrating a configuration example in the case where different voltages are supplied as a power supply voltage of a memory cell array between a writing time and a reading time as in the conventional example. FIG. 9 is a block diagram showing a memory cell array and peripheral circuits in Embodiment 3 and a power supply configuration supplied to them. FIG. 10 is a diagram illustrating an example of a layout of memory cells in a fourth embodiment. FIG. 3 is a diagram showing a layout example of a conventional memory cell of the SRAM memory cell array circuit shown in FIG. 2. FIG. 10 is a diagram illustrating an example of a layout of memory cells in a fifth embodiment. FIG. 10 is a diagram illustrating an example of a layout of memory cells in a sixth embodiment. FIG. 16 is a diagram illustrating an example of a layout of memory cells in a seventh embodiment. FIG. 19 is a block diagram showing a memory cell array and peripheral circuits in Embodiment 8, and a power supply configuration supplied to them. FIG. 16 is a block diagram showing a memory cell array and peripheral circuits in Embodiment 9, and a power supply configuration supplied to them. It is a block diagram which shows the connection of the power supply wiring at the time of applying the power supply structure of FIG. 13 to system LSI. FIG. 15 is a block diagram showing connection of power supply wiring when the power supply configuration of FIG. 14 is applied to a system LSI. FIG. 3 is a circuit diagram of an SRAM memory cell configured such that a well potential of a MOS transistor constituting the SRAM memory cell shown in FIG. 2 can be applied by a well power supply line. FIG. 25 is a diagram illustrating a power supply voltage application pattern example A when active and inactive applied to a memory cell in the tenth embodiment. FIG. 25 is a diagram illustrating a power supply voltage application pattern example B when active and inactive applied to a memory cell in the tenth embodiment. FIG. 22 is a diagram illustrating a power supply voltage application pattern example C when active and inactive applied to a memory cell in the tenth embodiment. FIG. 25 is a diagram showing an example of a power supply voltage application pattern D when active and inactive applied to a memory cell in Embodiment 10. FIG. 29 is a diagram showing an example E of a power supply voltage application pattern when active and inactive applied to a memory cell in the tenth embodiment. FIG. 22 is a diagram illustrating a power supply voltage application pattern example F when active and inactive applied to a memory cell in the tenth embodiment. It is a figure which shows the relationship between a prior art example and the static noise margin of the memory cell of this invention. 3 is a diagram illustrating a relationship between power supply voltages Vdd and Vdd ′ at which the memory cell in Embodiment 1 operates. FIG.

  Several preferred embodiments of a semiconductor memory device according to the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference symbols denote the same components.

<Embodiment 1>
1 shows a memory cell array 30 constituting an SRAM memory according to the present invention, a memory peripheral circuit 31 including a word driver and a decoder, a memory peripheral circuit 32 including a sense amplifier and a decoder, a memory cell array 30 and a peripheral circuit. 3 is a block diagram showing a relationship between voltages Vdd and Vddm of power supply lines 2 and 4 supplied to circuits 31 and 32. FIG. A voltage Vdd ′ higher than the voltage Vdd of the power supply line 2 of the peripheral circuits 31 and 32 other than the memory cell array is applied to the power supply line 4 of the memory cell array 30. Although the source line of the memory cell driving MOS transistor in the memory cell array 30 and the ground line of other peripheral circuits are not shown, the same ground voltage Vss is applied.

  The configuration of the memory cell of the SRAM memory in the present embodiment is the same as the memory cell of the conventional SRAM memory shown in FIG. 2 in which one memory cell is composed of six transistors. However, the memory cell will be described with reference to FIG. The same applies to other embodiments.

  In the memory cell of FIG. 2, the voltage of the word line WL is Vw, the voltages of the bit lines BL and / BL are Vb1 and Vb2, respectively, the voltage of the power line 4 of the memory cell is Vddm, and the voltage of the ground line 5 of the memory cell is Vssm. The voltages of the data holding nodes 6 and 7 of the memory cell are Vn1 and Vn2, respectively. The power supply voltage of the peripheral circuit is Vdd and the ground voltage is Vss.

  By maintaining the power supply line voltage Vddm of the memory cell at the word line voltage Vw and the voltage Vdd ′ higher than the bit line voltages Vb1, Vb2, the gate-source voltages of the driving MOS transistors N1, N2 of the SRAM cell are transferred to the transfer MOS transistors N3, It becomes larger than the gate-source voltage of N4. As a result, the conductances of the driving MOS transistors N1 and N2 are larger than the conductances of the transfer MOS transistors N3 and N4, and the noise margin of the SRAM memory cell is increased. Therefore, the threshold value of the MOS transistor is lowered to operate at a low voltage. It becomes possible to set.

  FIG. 3 shows a change in potential of each part of the memory cell during the memory operation in this embodiment, and FIG. 4 shows a change in voltage of each part of the memory cell during the memory operation when the voltage is boosted only during reading in the conventional example. Show. 3A and 3B, (a) shows the change in the potential of the word line voltage Vw and the power supply line voltage Vddm of the memory cell, and (b) shows the change in the voltages Vn1 and Vn2 of the data holding nodes of the memory cell. ) Indicates the voltage change of the bit line voltages Vb1 and Vb2.

  FIG. 4C shows that the bit line potential before reading is high, which is different from the example shown in the conventional example, but when the same operation as the example of FIG. 3 shown in the present invention is performed. If it does, it will become the electric potential shown in Drawing 4 (a)-(c). As the power supply voltage Vddm of the memory array, Vdd which is a voltage equivalent to that of the peripheral circuit is usually applied.

  At the time of reading, a voltage Vdd 'higher than the power supply voltage of the peripheral circuit is applied as the power supply voltage Vddm of the memory array, and then the word line voltage Vw is raised from low to high to select the selected memory cell Data holding nodes (storage nodes) 6 and 7 are connected to the bit lines BL and / BL, respectively. At the same time, a potential difference is generated between the bit line voltages Vb1 and Vb2 by the MOS transistor of the memory cell, and the data of the memory cell is read.

  At the time of writing, the same voltage Vdd as the power supply voltage of the peripheral circuit is applied as the power supply voltage Vddm of the memory array. After the power supply voltage Vddm of the memory array changes to the voltage Vdd, the word line voltage Vw is raised and data is written from the write circuit (not shown) to the bit lines BL and / BL, and the bit line voltages Vb1 and Vb2 are High and low respectively. As a result, the voltages Vn1 and Vn2 of the storage node in the memory cell respectively become high and low voltages for storing the data to be written, and the data is written.

  In the case of FIG. 4, the voltages Vn1 and Vn2 of the storage nodes in the memory cell to be inverted at the time of writing are smaller than in the case of FIG. In addition, when writing and reading are performed alternately, it is necessary to boost and step down the memory array power supply. That is, as shown in FIG. 4A, when the memory is operated at a low voltage, in the conventional example, the power supply voltage Vddm of the memory cell is boosted from the voltage Vdd to the voltage Vdd ′ only at the time of reading. In this method, it is necessary to repeat the step-up and step-down of the power supply voltage Vddm of the memory cell for each operation, which increases power consumption.

  In contrast, in this embodiment, as can be seen from FIG. 3A, the power supply voltage Vddm of the memory cell array is always higher than the power supply voltage Vdd of the peripheral circuit regardless of reading and writing during the operation of the memory. The voltage Vdd ′ is applied.

  At the time of reading, the word line voltage Vw rises from low to high, and the storage nodes 6 and 7 in the selected memory cell are connected to the bit lines BL and / BL, respectively. At the same time, a potential difference is generated between the bit line voltages Vb1 and Vb2 by the MOS transistor of the memory cell, and the data of the memory cell is read.

  At the time of writing, the word line voltage Vw rises and data is written from the write circuit (not shown) to the bit lines BL and / BL, and the bit line voltages Vb1 and Vb2 become high and low, respectively. As a result, the voltages Vn1 and Vn2 of the storage node in the memory cell respectively become high and low potentials for storing the data to be written, and the data is written.

  In this embodiment, since the voltage Vdd 'higher than the power supply voltage Vdd of the peripheral circuit is always applied to the memory cell power supply line 4, power consumption due to stepping up and down of the power supply line 4 as in the conventional example is suppressed. It is done.

  Since the power supply voltage Vddm of the memory cell is always kept at a high potential, the voltage Vn1 of the storage node is kept high, and even when the power supply voltage Vdd of the peripheral circuit is low, data is not corrupted at the time of reading. Further, since the voltage Vw of the word line is the power supply voltage Vdd of the peripheral circuit, the voltage of the bit line is kept below Vdd.

  FIG. 25 shows the relationship between the power supply voltages Vdd and Vdd ′ at which the memory cell of this embodiment operates. When Vdd is taken on the horizontal axis and the power supply voltage Vdd ′ of the memory cell array boosted on the vertical axis, the region denoted by reference numeral 15 becomes the operating range of the memory cell array, and even with a low power supply voltage of about 0.5V, the SRAM It can be seen that the memory cell is operating.

  In the case where different voltages are supplied at the time of writing and reading as the voltage of the power supply line 4 of the memory cell array as in the conventional example, for example, a switch circuit 38 and a control circuit (not shown) as shown in FIG. Is required. The switch circuit 38 is a circuit that switches the input terminal a or the input terminal b according to the value of the control signal line 37 from the control circuit and connects it to the output terminal c. Thus, the control signal line 37 input to the terminal d is connected to the power supply line 4 connected to the output terminal c of the switch circuit 38, the power supply line 2 of the potential Vdd of the peripheral circuit connected to the input terminal a, and the input. Different power supply potentials can be supplied to the memory cell array 30 by controlling the high potential power supply line 4 ′ having a potential Vddm higher than Vdd connected to the end b so as to be switched and connected at the time of writing and reading. In the conventional example, a circuit as shown in FIG. 6 or a circuit that dynamically changes the power supply voltage is required, and the chip area is larger than that in the configuration of FIG.

<Embodiment 2>
FIG. 5 shows another embodiment of the power supply structure of the peripheral circuit of the memory including the memory cell array, the sense amplifier, the decoder and the like constituting the SRAM memory according to the present invention. The difference from the configuration of FIG. 1 described above is that the same voltage Vdd as the voltage Vddm of the memory array power supply line 4 is applied to the memory cell array 30 as well as the source of the memory cell driving MOS transistor. The source line voltage Vssm of the line 5 is that a voltage lower than the ground voltage Vss of the ground line 2s of peripheral circuits other than the memory cell array is applied.

  By keeping the source line voltage Vssm of the memory cell driving MOS transistor lower than the word line voltage Vw and the bit line voltages Vb1, Vb2, the gate-source voltages of the driving MOS transistors N1, N2 of the SRAM cell are transferred to the transfer MOS transistor N3. , It becomes larger than the gate-source voltage of N4. As a result, the conductances of the driving MOS transistors N1 and N2 are larger than the conductances of the transfer MOS transistors N3 and N4, and the noise margin of the SRAM memory cell is increased. Therefore, the threshold value of the MOS transistor is set to operate at a low voltage. It can be lowered.

<Embodiment 3>
FIG. 7 shows another embodiment of the power supply structure of the peripheral circuit of the memory including the memory cell array, sense amplifier, decoder and the like constituting the SRAM memory according to the present invention. The memory cell array 30 is similar to the configuration of FIG. 5 except that the memory array power supply voltage Vddm is connected to a voltage Vdd ′ higher than the power supply voltage Vdd of circuits other than the memory cell array.

  Even in such a configuration, the memory array power supply voltage Vddm is kept higher than the word line voltage Vw and the bit line voltages Vb1 and Vb2, and the source line voltage Vssm of the memory cell driving MOS transistor is kept higher than the word line voltage Vw and the bit line voltages Vb1 and Vb2. By keeping it low, the gate-source voltage of the driving MOS transistors N1, N2 of the SRAM cell becomes larger than the gate-source voltage of the transfer MOS transistors N3, N4, and the conductance of the driving MOS transistors N1, N2 is the transfer MOS transistor N3. Therefore, it becomes larger than the conductance of N4. As a result, the noise margin of the SRAM memory cell is increased, and the threshold value of the MOS transistor can be lowered in order to operate at a low voltage.

<Embodiment 4>
FIG. 8 is an example of a memory cell layout according to the present invention of the SRAM memory cell circuit shown in FIG. In FIG. 8, the same components as those of the conventional memory cell layout shown in FIG. 9 of the SRAM memory are denoted by the same reference numerals.

  The driving MOS transistor N1 and the transfer MOS transistor N3 are formed in the P well region Pw1, and the driving MOS transistor is parallel to the boundary between the P well region Pw1 and the N well region Nw1 where the load MOS transistors P1 and P2 are formed. The center line of the diffusion layer 34 of N1 and the transfer MOS transistor N3 is configured to be substantially straight, and the diffusion layer 34 has a line-symmetric layout with respect to this center line.

Similarly, the driving MOS transistor N2 and the transfer MOS transistor N4 are formed in the P well region Pw2, and are parallel to the boundary between the P well region Pw2 and the N well region Nw1 where the load MOS transistors P1 and P2 are formed. The center line of the diffusion layer 34 of the driving MOS transistor N2 and the transfer MOS transistor N4 is substantially linear, and the diffusion layer 34 has a layout symmetrical with respect to the center line.
A dotted line 36 represents one memory cell, and this memory cell is folded in a vertical direction and a horizontal direction to constitute a memory array.

  As described above, in the conventional memory cell, in order to make the conductance of the drive MOS transistors N1 and N2 larger than the conductance of the transfer MOS transistors N3 and N4, the gate width W1 of the drive MOS transistors N1 and N2 is changed to the transfer MOS. The gate width W3 of the transistors N3 and N4 needs to be made larger, and a MOS transistor having a ratio of W1 / W3 of 1.5 or more is usually used.

  On the other hand, as described in the first embodiment, since the voltage Vdd ′ higher than the voltage Vw of the word line WL is applied as the power supply voltage Vddm of the memory cell, the conductance of the driving MOS transistor is the conductance of the transfer MOS transistor. In the memory cell layout of this embodiment, the ratio W1 / W3 of the gate width W1 of the driving MOS transistor and the gate width W3 of the transfer MOS transistor can be made smaller than 1.4. . Thereby, the area is smaller than that of the conventional memory cell.

<Embodiment 5>
FIG. 10 is another example of the memory cell layout according to the present invention of the SRAM memory cell circuit shown in FIG. In FIG. 10, the same reference numerals are assigned to the same components as those of the conventional memory cell layout shown in FIG. 9 of the SRAM memory. Since the memory cell used in the layout of FIG. 10 is applied with the voltage Vdd ′ higher than the word line WL as the power supply voltage Vddm of the memory cell as in the memory cell of the fourth embodiment, the drive MOS transistor and the transfer MOS transistor The gate width ratio W1 / W3 is made smaller than that of the conventional memory cell, and in particular, the gate width ratio W1 / W3 is set to 1.

  When the gate width ratio W1 / W3 is 1, in the memory cell in which the diffusion regions of the driving MOS transistors N1, N2 and the transfer MOS transistors N3, N4 are linearly formed as shown in FIG. Region 34 can be formed completely rectangular. As a result, it is possible to greatly reduce the variation that occurs when the diffusion region is formed on the silicon substrate, and it is possible to manufacture memory cells with high dimensional accuracy, that is, memory cells with little performance variation. In addition, since the gate widths of the driving MOS transistors N1 and N2 are smaller than the conventional one, the memory cell area 36 can be reduced.

<Embodiment 6>
FIG. 11 is a memory cell layout in which the ratio W1 / W3 of the gate width W1 of the driving MOS transistors N1, N2 and the gate width W3 of the transfer MOS transistors N3, N4 is 1, as in the memory cell layout of FIG. Furthermore, this is a memory cell layout example in which the gate width W2 of the load MOS transistors P1, P2 in the memory cell is the same as the gate widths W1 and W3 of the drive MOS transistor and the transfer MOS transistor.

  In general, in the SRAM memory cell, it is necessary to make the conductance of the load MOS transistor smaller than the conductance of the transfer MOS transistor in order to obtain sufficient stability during writing. On the other hand, in the memory cell used in the layout of FIG. 11, the conductance of the load MOS transistor is reduced by increasing the threshold voltage of the load MOS transistors P1 and P2, thereby reducing the transfer MOS transistor and the drive MOS transistor. The gate width is further reduced. As a result, the area of the entire memory cell is further reduced.

<Embodiment 7>
The memory cell layout of FIG. 12 is a memory cell in which the ratio W1 / W3 of the gate width W1 of the driving MOS transistors N1, N2 and the gate width W3 of the transfer MOS transistors N3, N4 is 1, as in the memory cell layout of FIG. However, the gate widths W1 and W3 are made larger than the gate widths of the load MOS transistors P1 and P2 by at least twice (W1 / W2> 2).
By increasing these gate widths, it becomes possible to increase the memory cell current and to increase the memory operation speed. This indicates that the present invention can be used not only as an SRAM circuit operating at a low voltage but also as an SRAM circuit operating at high speed.

<Eighth embodiment>
FIG. 13 is a diagram showing a connection configuration example of power supply lines of a memory circuit including a memory cell array 30, a peripheral circuit 31 including a word driver and a decoder, and a peripheral circuit 32 including a sense amplifier and a decoder. It is.
The memory circuit is supplied with a single power supply voltage Vdd by the power supply line 2, and the peripheral circuits 31 and 32 operate with this power supply voltage Vdd. On the other hand, in the memory cell array 30, an output line obtained by boosting the power supply voltage Vdd supplied from the power supply line 2 to the voltage Vddm by the booster circuit 21 is used as the memory array power supply line 4. As a result, a configuration in which a power supply voltage Vddm higher than that of the peripheral circuit is applied to the memory cell array 30 can be realized.

  FIG. 15 is a schematic diagram showing connection of power supply wirings when such a power supply configuration is applied to a system LSI. FIG. 15 shows a power supply structure of a system LSI including a memory circuit including a memory peripheral circuit 25 and a memory cell array 30, an input / output circuit 23, and a logic circuit 24. The system LSI in the figure is supplied with a core power supply voltage Vdd for operating the logic circuit 24 and an input / output circuit (IO) high-voltage power supply Vddio for operating the input / output circuit 23.

Reference numeral 21 in the figure is a booster circuit, the memory peripheral circuit 25 is supplied with the core power supply voltage Vdd used in the logic circuit, and the memory cell array 30 is supplied with a voltage higher than the voltage Vdd using the booster circuit 21. The boosted power supply voltage Vddm is supplied.

<Ninth Embodiment>
FIG. 14 shows another example of the connection configuration of the power supply lines of the memory circuit including the memory cell array 30, the peripheral circuit 31 including a word driver and a decoder, and the peripheral circuit 32 including a sense amplifier and a decoder. FIG.

This memory circuit includes a power supply voltage Vdd supplied by the power supply line 2 for operating the peripheral circuits 31 and 32 of the memory, and a high voltage power supply voltage for IO that is higher than the voltage Vdd used in the input / output circuit of the LSI. Vddio is supplied by the power line 4 ′. The peripheral circuits 31 and 32 operate with the power supply voltage Vdd. On the other hand, in the memory cell array 30, an output line obtained by stepping down the power supply voltage Vddio supplied from the power supply line 4 ′ to the voltage Vddm by the step-down circuit 22 is used as the memory array power supply line 4. As a result, a configuration in which the power supply voltage Vddm higher than that of the peripheral circuit is applied to the memory cell array 30 can be realized.
FIG. 16 shows connection of power supply wiring on a chip when such a power supply configuration is applied to a system LSI. FIG. 16 shows a power supply structure of a system LSI including an input / output circuit, a logic circuit, and a memory circuit. The system LSI in the figure is supplied with a core power supply voltage Vdd for operating the logic circuit 24 and an IO high-voltage power supply voltage Vddio for operating the input / output circuit 23.

  Reference numeral 22 in the figure is a step-down circuit, the core power supply voltage Vdd used for the logic circuit is supplied to the peripheral circuit 25 of the memory, and the memory cell array 30 is used for IO high voltage using the step-down circuit 22. A power supply voltage Vddm lower than the power supply voltage Vddio and higher than the core power supply voltage Vdd is supplied.

<Embodiment 10>
In the present embodiment, voltage application pattern examples A to F of the power supply voltage applied to the SRAM memory cell during the period during which the SRAM circuit is operated (when active) and during the period when the SRAM circuit is not operated (when inactive) will be described.

  FIG. 17 is a circuit diagram of an SRAM memory cell configured such that the well potential of the MOS transistor constituting the SRAM memory cell shown in FIG. As shown in FIG. 17, the P well feed line 8 is connected to the P well in the memory cell in which the NMOS transistor is formed, and the N well feed line 9 is connected to the N well in the memory cell in which the PMOS transistor is formed. The Vbn is the voltage of the P-well power supply line 8, and Vbp is the voltage of the N-well power supply line 9.

(1) Power supply voltage application pattern example A:
FIG. 18 is a diagram showing voltages applied to the SRAM memory cell when the SRAM circuit is active and inactive. FIG. 18A shows the power supply voltage Vddm of the memory cell and the voltage Vbp of the N-well power supply line. Indicates the ground voltage Vssm of the memory cell and the voltage Vbn of the P-well power supply line 8.
In this power supply voltage application pattern example, a voltage Vdd ′ higher than the power supply voltage Vdd of the peripheral circuit is applied as the memory cell power supply voltage Vddm and the N-well power supply line voltage Vbp when active, and the same voltage as the power supply voltage of the peripheral circuit when inactive. Vdd is applied to each. As the ground voltage Vssm of the memory cell and the voltage Vbn of the P-well power supply line, a constant ground voltage Vss is always applied regardless of whether it is active or inactive. With such a power supply voltage application pattern, it is possible to suppress a leakage current when inactive.

(2) Power supply voltage application pattern example B:
FIG. 19 is a diagram showing voltages applied to the SRAM memory cell when the SRAM circuit is active and inactive. FIG. 19A shows the power supply voltage Vddm of the memory cell and the voltage Vbp of the N-well power supply line. ) Indicates the ground voltage Vssm of the memory cell and the voltage Vbn of the P-well power supply line.
In this power supply voltage application pattern example, as in FIG. 18, when active, a voltage Vdd ′ higher than the power supply voltage Vdd of the peripheral circuit is applied as the memory cell power supply voltage Vddm and the N-well power supply line voltage Vbp. Unlike the case of FIG. 18, when active, a voltage lower than the power supply voltage Vdd of the peripheral circuit is applied to the extent that data in the memory cell can be held. Even with such a power supply voltage application pattern, it is possible to suppress the leakage current when inactive.

(3) Power supply voltage application pattern example C:
20A and 20B are diagrams showing voltages applied to the SRAM memory cell when the SRAM circuit is active and inactive. FIG. 20A shows the power supply voltage Vddm of the memory cell, and FIG. 20B shows the ground voltage Vssm of the memory cell. (C) shows the voltage Vbp of the N-well power supply line, and (d) shows the voltage Vbn of the P-well power supply line.
In FIGS. 21 to 23 below, voltages (a) to (d) indicate the same voltages as in FIG.
In this power supply voltage application pattern example, a voltage Vdd ′ higher than the power supply voltage Vdd of the peripheral circuit is applied as the memory cell power supply voltage Vddm when active, and a voltage Vdd equal to the power supply voltage of the peripheral circuit is applied when inactive.
A constant ground voltage Vss is always applied to the ground voltage Vssm of the memory cell regardless of whether it is active or inactive.
The voltage Vdd 'applied to the source electrode of the PMOS transistor is applied when active, and the voltage Vdd applied to the source electrode of the PMOS transistor when inactive as the voltage Vbp of the N-well power supply line that gives the substrate bias of the PMOS transistor. A voltage higher than 'is applied.

  The voltage Vss applied to the source electrode of the NMOS transistor is applied when active, and the voltage Vss applied to the source electrode of the NMOS transistor when inactive, as the voltage Vbn of the P-well power supply line that gives the substrate bias of the NMOS transistor A lower voltage is applied respectively.

  Such a power supply voltage application pattern can also suppress a leakage current when inactive.

(4) Power supply voltage application pattern example D:
In FIG. 21, the applied voltage pattern of the power supply voltage Vddm of the memory cell is different from the power supply voltage application pattern example of FIG. 20 described above. As shown in FIG. 21 (a), the voltage Vdd ′ higher than the power supply voltage Vdd of the peripheral circuit is applied as the memory cell power supply voltage Vddm when active, in the voltage application pattern example shown in FIG. 20 (a). However, it is different from the voltage application pattern example shown in FIG. 20A in that a voltage lower than the power supply voltage Vdd of the peripheral circuit is applied when inactive.
Such a power supply voltage application pattern can also suppress a leakage current when inactive.

(5) Power supply voltage application pattern example E:
22 is different from the above-described power supply voltage application pattern example of FIG. 20 in the voltage application pattern of the voltages Vbp and Vbn of the well power supply lines. As shown in FIG. 22 (c), a voltage lower than the voltage Vdd ′ applied to the source electrode of the PMOS transistor is applied as the voltage Vbp of the N-well power supply line 9 that gives the substrate bias of the PMOS transistor when activated. When inactive, a voltage higher than the voltage Vdd applied to the source electrode of the PMOS transistor is applied.

As shown in FIG. 22 (d), a voltage higher than the voltage Vss applied to the source electrode of the NMOS transistor is applied as the voltage Vbn of the P-well power supply line 8 that gives the substrate bias of the NMOS transistor when it is active. When active, a voltage lower than the voltage Vss applied to the source electrode of the NMOS transistor is applied.
With such a power supply voltage application pattern, it is possible to increase the current by lowering the threshold voltage of the MOS transistor when active, and to suppress the leakage current when inactive.

(6) Power supply voltage application pattern example F:
23 differs from the above-described power supply voltage application pattern example of FIG. 20 in a voltage application pattern of the power supply voltage Vddm of the memory cell and the voltage Vbp of the N-well power supply line.

  That is, as shown in FIG. 23A, as the power supply voltage Vddm of the memory cell, a voltage Vdd ′ higher than the power supply voltage Vdd of the peripheral circuit is applied when active, and a voltage lower than the power supply voltage Vdd of the peripheral circuit when inactive. Is applied.

Further, as shown in FIG. 23 (c), the voltage Vbp 'applied to the source electrode of the PMOS transistor when applied is applied as the voltage Vbp of the N-well power supply line 9 that gives the substrate bias of the PMOS transistor, and is inactive. Sometimes, a voltage lower than the voltage Vdd ′ applied when active to the source electrode of the PMOS transistor and higher than the voltage Vddm when inactive is applied. A voltage higher than the voltage Vss applied to the NMOS source electrode when active is applied to the NMOS substrate electrode, and a voltage lower than the voltage Vss applied to the NMOS source electrode when not active. .
Even with such a power supply voltage application pattern, the threshold voltage of the MOS transistor can be lowered to increase the current when active, and the leakage current when inactive can be suppressed.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various design changes can be made without departing from the spirit of the present invention. Of course.

  As described above, as apparent from the above-described embodiments, according to the present invention, it is possible to realize an SRAM that secures a static noise margin and operates with low power consumption and a low voltage of 1 V or less.

  2 ... peripheral circuit power supply line, 2s ... ground potential line, 4 ... memory cell power supply line, 4 '... high voltage power supply for IO, 5 ... memory cell ground line, 6, 7 ... memory cell data holding node (storage node), 8 ... P-well power supply line, 9 ... N-well power supply line, 11, 12, 13 ... static noise margin, 15 ... operating range of memory cell array, 21 ... boost circuit, 22 ... voltage down circuit, 23 ... input / output circuit, 24 ... Logic circuit, 25 ... Memory peripheral circuit, 30 ... Memory cell array, 31, 32 ... Peripheral circuit, 33 ... Contact, 34 ... N-type diffusion layer, 35 ... Polysilicon (gate electrode), 36 ... One SRAM memory cell region , 37 ... control signal line, 38 ... switch circuit, 39 ... P-type diffusion layer, BL, / BL ... bit line, Vdd, Vddm, Vdd ', Vddio ... power supply voltage, Vss, Vssm ... ground voltage, Vbn ... P well Feed line voltage, Vbp ... N-well feed line voltage, Vw ... Word line voltage, Vb1, Vb2 ... Bit line voltage, N1, N2 ... Drive MOS transistor, N3, N4 ... Transfer MOS transistor, P1, P2 ... Load MOS Transistor, Nw1... N well region, Pw1, Pw2... P well region, WL... Word line, W1... Gate width of driving MOS transistor, W2.

Claims (1)

Static memory composed of N-channel first and second drive MOS transistors, N-channel first and second transfer MOS transistors, and P-channel first and second load MOS transistors Cells are formed in an array on a semiconductor substrate, source electrodes of the first and second drive MOS transistors are connected to a first operating potential point, and source electrodes of the first and second load MOS transistors are A semiconductor device connected to two operating potential points,
In the read operation state and the write operation state of the memory cell, the potential of the second operating potential point is set to a potential higher than the high level potential applied to the gate electrodes of the first and second transfer MOS transistors,
The potential at the first operating potential point is the same between the read operation state and the write operation state of the memory cell,
The potential of the second operating potential point is the same in the read operation state and the write operation state of the memory cell,
And a pair of bit lines, an input / output circuit, a logic circuit, and a memory power supply line for supplying a power supply potential to the static memory cells formed in the array,
The first transfer MOS transistor is connected to one of the bit line pairs, the second transfer MOS transistor is connected to the other of the bit line pairs,
The semiconductor device receives an input / output circuit power source of the input / output circuit and a core power source used for the logic circuit,
The memory device is a semiconductor device, wherein the memory power supply line is connected to the second operating potential point, and power is supplied from the core power supply.

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