JPH1139879A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which assures higher updating rate and saves power consumption. SOLUTION: In a semiconductor device having an SRAM section 1, circuits elements 18, 19, 20, 21 for selectively changing a substrate potential of SRAM section 1 is provided and the threshold value voltage of MOSFET of the SRAM section 1 is changed with these circuit elements. Thereby, the threshold value voltage is changed for the writing and reading operations and the total power consumption, can be controlled while the high speed operation is maintained when it is required.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device such as an LSI, and more particularly to an SRAM (Static Random Access) for storing a program in a rewritable FPGA (Field Programmable Gate Array).
ss Memory).

[0002]

2. Description of the Related Art An SRAM 1 as shown in FIG. 7 is used as a temporarily rewritable memory in a semiconductor device composed of an integrated circuit such as an LSI. This SRAM 1 shows one cell, and such cells are usually arranged in an array. This SRAM1
In this example, the two inverters 2 and 3 hold signals, and the memory is held as long as power is supplied. As shown in FIG. 8, normally, inverters 2 and 3 are connected to two nMOS
It is configured using an FET 4 and two pMOSFETs 5.
In the case where a plurality of SRAMs are arranged in an array, a switch for writing and reading is further provided as shown in FIG. 9 in order to select a memory cell. In FIG. 9, reference numeral 6 denotes a switch connected to a write bit line and a word line, and reference numeral 7 denotes a switch connected to a read bit line and a word line.

The characteristics of the transistor of the SRAM 1 are designed in accordance with the purpose of use of the SRAM. For example, when very high-speed writing and reading are required, the same performance as that used in logic is required. However, a transistor with poor performance may be used when writing and reading may take time because data is not frequently rewritten. Generally, high-performance transistors consume large amounts of power,
It is necessary to consider from the point of power consumption.

Here, the relationship between the performance of a transistor used in an SRAM and the power consumption will be described focusing on the threshold voltage of the transistor. FIG. 10 is a graph showing the relationship between the gate voltage and the drain current of the transistor. The threshold voltage is, as shown in FIG.
The gate voltage when the drain current increases rapidly. In general, the drive current of a transistor is proportional to the square of the difference between the gate voltage and the threshold voltage. Therefore, lowering the threshold voltage increases the driving capability, while raising the threshold voltage lowers the driving capability. In other words, when the threshold voltage is low, the speed of writing and reading increases.

[0005] On the other hand, from the viewpoint of power consumption, the lower the threshold voltage, the higher the power consumption. In this case, it is necessary to examine what components of the power consumption are large in the following three points. There is. (1) First, a current for driving a load at the time of reading can be considered. FIG. 11 shows a case where the load capacity 8 is charged and discharged by the SRAM 1. The power consumption for this one reading does not depend on the threshold voltage if the load is the same. Only the time it takes to drive the load changes. (2) Next, there is a through current flowing when the inverter is inverted at the time of writing. FIG. 12 is a diagram for explaining a through current 9 flowing through a pair of transistors 5 and 4 constituting an inverter. Through current 9 is nMOSFET
4. The current that flows when both pMOSFETs 5 are in the ON state, and increases as the threshold voltage decreases. (3) Finally, there is power consumption during standby. This is what is commonly known as leakage current. As shown in FIG. 13, even if the gate voltage is 0 V, the drain current does not always become completely zero, and a slight current flows. This is called leak current, and increases exponentially as the threshold value decreases. Although depending on the structure of the transistor, when the threshold value drops from about 80 mV to about 120 mV, the leak current increases by one digit.

In view of the above, when the contents are frequently accessed and the contents are rewritten, the threshold voltage may be lowered while giving priority to the speed, but in this case, the power consumption increases. On the other hand, it is understood that the speed is not so required, and when the standby state is long, the threshold voltage may be increased to reduce the power consumption. However, in reality, there is definitely a conflicting demand for a faster writing while the waiting time is long. This is, for example, a special FP
In this case, GA is used. FPGA is a Fi
eld Programmable GateArray
, And its function can be rewritten unlike an ordinary LSI. FIG. 14 is a conceptual diagram showing an FPGA. The mechanism is such that a large number of basic cells 10 each having a set of flip-flops and inverters are arranged in an array, and wirings in the basic cells 10 and wirings 11 between cells are switched by a switch matrix 12 such as a pass transistor. In order to realize an LSI having various functions. The on / off state of this switch is stored and stored in a memory. By rewriting the contents of the memory, an LSI having a different function can be produced.

[0007] In some cases, the memory for storing the program of the FPGA retains its contents even when the power supply is stopped, such as a flash memory, but the contents are lost when the power supply is stopped, such as an SRAM. In some cases, it is lost.
When an SRAM is used as a storage memory, a program must be externally loaded every time the power is turned on. Therefore, it is necessary to reduce the time required for writing to shorten the rise time. As a special example of how to use an FPGA, there is a case where a program of the same FPGA is rewritten many times while a device is operating to perform different processing. At this time, how many times the data is rewritten within a certain period of time becomes important as the capability of the FPGA. Therefore, there is a desire to reduce the rewriting time of the SRAM in this case as well. That is, it is required to reduce the threshold voltage of the SRAM transistor.

[0008]

However, when the program is not being rewritten, the SRA
The M transistor simply keeps the pass transistor switch on or off. This state is shown in FIG. FIG. 15 shows one SRAM 1
FIG. 4 is a diagram showing a case where the pass transistor 13 is switched by the switch. In this case, the leak current leaking from the load such as the gate electrode of the pass transistor 13 and the wiring 11 is very small. Therefore, most of the power consumption during the non-rewriting operation is a leakage current generated in the transistor of the SRAM 1. Therefore, it is preferable that the threshold voltage be high in order to reduce the leak current during the time when no rewriting is performed.

Such a problem becomes more apparent as the power supply voltage of the FPGA becomes smaller. The current mainstream power supply voltage is 3.3 V, but considering operation with one dry cell, it is necessary to operate at a high speed of about 1 V or less. In this case, the threshold voltage is 0.
It becomes about 2 V, and the leak current cannot be ignored. SRAM that simply holds data
In addition, it is not preferable to consume power by useless leakage current. In particular, the number of SRAs equal to the number of switches of pass transistors
Since M exists, the ratio occupied by SRAM is high,
Reducing the power consumption is a major challenge.

[0010] The present invention focuses on the above problems,
The present invention has been made to solve this problem effectively, and an object of the present invention is to provide a semiconductor device having a high rewriting speed and low power consumption.

[0011]

Conventionally, since the threshold value of the SRAM transistor was constant, it was necessary to sacrifice either the rewriting speed or the power consumption. The present invention focuses on this point. , And a new operation mode of the SRAM. In particular, the present invention is applied to an FPGA whose contents are rewritten during operation of a device. The present invention solves the above problem by using S
In a semiconductor device having a RAM section, a circuit element for selectively changing the substrate potential of the SRAM section is provided, and the threshold voltage of the MOSFET in the SRAM section is changed by the circuit element.

As a result, the substrate potential of the SRAM portion is changed by, for example, opening and closing a switch as a circuit element for changing the potential. The aspect of the change of the substrate potential is the SRAM
At the time of writing of the portion, the substrate potential is set so as to lower the threshold voltage, and at the time of holding, the substrate potential is set so as to raise the threshold. For example, MOS as the switch
A pass transistor composed of an FET can be used. As the pass transistor, an nMOSFET is used to lower the substrate potential, and a pMOSFET is used to raise the substrate potential. This is nMOS
If an attempt is made to increase the potential using the source of the FET, the nMOSFET is turned off when the potential of the source reaches a value obtained by subtracting the threshold voltage from the gate voltage. This is to avoid the problem of the source follower circuit being lowered. pM
When lowering the potential at the OSFET source, nMOSF
A similar problem occurs only when the direction of the potential is opposite to that in the case of ET. Therefore, the configuration as described above prevents the formation of the source follower circuit.

Further, a pumping circuit can be used as a potential switching circuit element instead of the switch. Such a semiconductor device can be employed in a field programmable gate array (FPGA). Further, when such a semiconductor device includes a logic circuit portion, the substrate potential of the logic circuit portion can be controlled separately from the SRAM portion. The threshold voltage of the substrate of the logic circuit portion is increased during standby, and reduced during active state.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a graph showing the relationship between the substrate potential and the threshold voltage for explaining the substrate effect, FIG. 2 is a principle diagram for switching the substrate potential,
FIG. 3 is a circuit diagram in the case where the switch for switching the substrate potential is constituted by a MOSFET. The same components as those described in the drawings described above are denoted by the same reference numerals and described. The problem with the conventional SRAM is that the threshold voltage of the transistor in the SRAM cannot be changed during operation. At present, the threshold voltage is determined by the amount of impurity implantation for adjusting the threshold voltage performed in the manufacturing process. Normally, the injection amount is set so that the optimum threshold value is obtained when the potential of the substrate is the same as that of the source, and wiring is performed so that the potential of the substrate always matches the source.

In such a conventional method, the threshold voltage cannot be changed after the device is manufactured. However, there are methods for electrically changing the threshold. It is to use a phenomenon known as the substrate effect. When the potential of the substrate is set to a value different from that of the source using this phenomenon, the threshold voltage can be changed. FIG.
FIG. 11 shows an example of a change in the threshold value due to the substrate potential of the nMOSFET. It can be seen that the threshold voltage is increased as the substrate potential is shifted in the negative direction. So, SR
If the substrate potential is changed according to the operation of the AM, the threshold value can be changed, and the operation can be speeded up while reducing power consumption. That is, when writing to the SRAM, the threshold voltage is set low, that is, the substrate potential is set high, and when the SRAM enters the holding operation, the threshold voltage is set high, that is, the substrate potential is set low. You should keep it. This is for the nMOSFET, and in the case of the pMOSFET, the directions of the potentials are all reversed.

FIG. 2 shows a more specific configuration for realizing this. As described with reference to FIG. 8, the SRAM 1 configuring one cell includes two nMOSFETs 4 and two pMOSFETs.
The cells are arranged in an array on the substrate to form an SRAM section. In addition, SRA
Here, one SRAM 1 is representatively described as the M section. Wiring 1 connected to the substrate of MOSFET4,5
4, 15 are switches 16A, 16B, 17A, respectively.
17B, these switches are configured as pass transistors, and serve as circuit elements for changing the substrate potential. That is, the substrate voltage can be changed by switching the switch group. For example, the switch 16A is connected to -5V, the switch 16B is connected to 0V, the switch 17A is connected to 1V, and the switch 17B is connected to 6V. In this case, the nMOSFET 4 and the pMOSF
Each substrate is connected to a different switch group in order to have a different substrate voltage level from ET5.

In the nMOSFET 4, the switches 16A and 16B are connected to wirings having different potentials. One switch 16B is set to, for example, 0V and the same potential as the source, and the other switch 16A is set to a potential of about -5V. The threshold voltage is about 0.2 V when the substrate potential is 0 V, but becomes about 0.5 V when the substrate potential is -5 V (see FIG. 1). pMO
In the case of SFET5, it is just the opposite of the case of nMOSFET. That is, of the two switches 17A and 17B, one switch 17A is set to 1V, and the other switch 17B is set to 6V. When it is desired to lower the threshold voltage, the substrate voltage is set to the same as the power supply voltage, for example, 1V. When it is desired to increase the threshold voltage, the substrate voltage is connected to, for example, 6V.

FIG. 3 shows a configuration for realizing the switch. Here, the switches 16A, 16B, 17A, 17B
In this case, it is necessary to be careful that the substrate side is a MOSFET.
If wiring is performed so as to be the source of T, this becomes a source follower circuit and must be avoided. That is, the reason is that if an attempt is made to increase the potential using the source of the nMOSFET, the nMOSFET is turned off when the potential of the source reaches a value obtained by subtracting the threshold voltage from the gate voltage. This is for avoiding a problem of the source follower circuit that becomes lower by the threshold value. A similar problem occurs when lowering the potential at the pMOSFET source, except that the direction of the potential is opposite to that of the nMOSFET. Therefore,
In order to prevent this, when used for the substrate of the nMOSFET, the switch 16 for lowering the voltage from 0V to -5V is used.
An nMOSFET 18 is used for A, and a pMOSFET 19 is used for the switch 16B when increasing the voltage from -5V to 0V.

Similarly, when used for a substrate of a pMOSFET, the switch 17A for lowering the voltage from 6V to 1V is used.
, The pMOSFET 21 is used as the switch 17B when increasing the voltage from 1V to 6V. These MOSFETs 18 to 2
In order to perform the switching control of 1, a switching control signal is applied to each gate. By doing so, the substrate voltage can be reliably maintained at a predetermined value. In the case where the switch 17A is connected to the power supply voltage, for example, 1 V, as described above,
When the MOSFET 20 is used and used for 6 V, a pMOSFET 21 is used as the switch 17B. At this time, the nMOSFET 20 and the pMOSFETs 21 and 1
8 and 19 are ON and OFF in the opposite direction for the same signal value
Therefore, it can be performed with a single wiring, which is very convenient.

When writing and reading of SRAMs are simultaneously performed on a large number of SRAM elements, it is not necessary to attach MOSFETs for these switches to each of the SRAM elements, but one to several MOSFETs for many SRAMs. Good. With such a configuration, by switching the switching control signal between “0” and “1” at the time of writing and at the time of reading (at the time of holding operation), the substrate potential of each SRAM unit can be easily changed. As a result, the rewriting speed can be increased, and the power consumption during holding can be reduced.

Incidentally, as described above, the method of changing the threshold voltage by changing the substrate voltage is not limited to using only the SRAM element, but can be applied to a logic circuit portion. In the case of the SRAM, the distinction is made between the time of writing and the time of reading, but in the case of the logic circuit, the distinction is made depending on whether the logic circuit is in the active state or the sleep state. A state in which the logic circuit can execute logic calculation at high speed, that is, a state in which the threshold voltage is low is an active state, and a state in which the logic circuit has a low calculation capability but a small leak current is a sleep state. The control of the active and sleep states may be finely controlled for each block in the logic circuit unit, but here, for simplicity, the entire semiconductor device as an LSI enters the active state or sleep state. The discussion will proceed as follows.

In this case, the semiconductor device has four modes according to the states of the logic circuit section and the SRAM section.
FIG. 4 shows this mode. That is, the active state (the state where the threshold value is low) of both the logic circuit portion and the SRAM is set to the AA mode,
The logic circuit section is in a sleep state but the SRAM writing is fast and active state is in the SA mode. The logic circuit section is in an active state that can be executed at high speed but the SRAM is in the sleep and read-only state in the AS mode. The logic circuit section is also in the SRA mode.
M is also a sleep state, and there are four SS modes in which the entire semiconductor device is in a sleep state (standby state).

By controlling these four states,
The calculation capability of the semiconductor device per a certain power consumption can be maximized. Here, the control is performed by an external CPU.
The method is described below. FIG. 5 shows a conceptual diagram thereof. A signal from the external CPU 22 can be controlled by two pins 23 and 24. One pin 23 is a pin (logic circuit control pin) for controlling the active and sleep modes of the logic circuit unit 25, and the other pin 24
Is a pin (SRAM control pin) for controlling the activation and sleep of the SRAM 1. In both cases, for example, "1" is active and "0" is sleep. still,
In the figure, 26 is a ROM for storing various programs, and 27 is a data line.

First, assuming that the semiconductor device is an FPGA, an operation of first reading a program from the ROM 26 is performed. At this time, the SRAM control pin 24 is set to "
1 ". At this time, there are two options for the logic circuit control pin 23. One is in an active state and is in a standby state. In this case, it is desired to execute the operation immediately after reading is completed. There is a state where the logic circuit unit 25 is waiting for a program to be read from the SRAM 1. To activate the logic circuit unit 25 from sleep, the SRA
In many cases, this does not cause a problem because the time required for reading M1 is much shorter.

When the reading of the program is completed, the SR
The AM control pin 24 issues a sleep command, that is, "0". Then, the threshold voltage of the SRAM 1 is increased, and the leak current is reduced. Then, the FPGA starts operating according to the program. When all operations are temporarily interrupted to enter the standby state, both the logic circuit control pin 23 and the SRAM control pin 24 become "0", and the apparatus enters the standby state. At this time, operation is possible at a very slow operation speed. Also, since all the states are kept on standby, the logic circuit control pin 23
Becomes "1", it is possible to quickly return to the high-speed operation again.

When a request to rewrite the program in the SRAM 1 arises during the operation, the SRA
Set the M control pin 24 to “1” and set the new program to R
Load from OM26. When the loading is completed, the SRAM control pin 24 is returned to "0". As described above, both the SRAM 1 and the logic circuit unit 25 can operate at high speed when active, and can minimize power consumption during standby.

In the above embodiment, a method of changing the substrate potential through a switch has been described as a method of changing the substrate potential. Alternatively, a type of pumping may be used as a circuit element for changing the substrate potential. There is a method using a circuit. FIG. 7 shows the conceptual diagram of FIG. 6. here,
A p-well 28 is provided on the surface of the n-type substrate, for example, S
The nMOSFET 4 of the RAM is provided. And
This substrate, that is, a switch A,
Pumping circuit 30 including A ', B, B' and capacitor 29
Are connected.

The operation of the pumping circuit 30 is as follows. First, switches A and A 'open, and switches B and
B ′ is closed and the capacitor 29 is charged with the voltage of Vdd. Next, the switches A and A 'are closed and the switches B and B'
Is opened, and the substrate (well 28) of the nMOSFET 4 is charged in the negative direction. This is repeated a plurality of times to reach the target substrate potential. To return the potential of the p-well 28 to the ground, the switches A and B can be opened and the switches A 'and B' can be closed to immediately return to the ground level. If two such pumping circuits 30 are prepared for the SRAM and the logic circuit, the same operation as that described above can be performed.
It should be noted that the value of the substrate potential in the above embodiment is merely an example, and is not limited to this.

[0029]

As described above, according to the semiconductor device of the present invention, the following excellent functions and effects can be exhibited. Since the substrate potential of the SRAM portion in the semiconductor device is changed by a predetermined circuit element, for example, a switch or a pumping circuit, the threshold voltage of the MOSFET can be arbitrarily changed. Therefore, at the time of writing in the SRAM portion, the threshold voltage is lowered to enable high-speed operation. At the time of holding and reading, the threshold voltage is increased to suppress power consumption. It is possible to simultaneously suppress the power consumption as a whole. When a logic circuit is provided in addition to the SRAM, the threshold voltage can be individually controlled according to the state of each part, for example, whether the apparatus is in a standby state or an active state. High-speed operation when required while suppressing the power consumption of the device.

[Brief description of the drawings]

FIG. 1 is a graph showing a relationship between a substrate potential and a threshold voltage for explaining a substrate effect.

FIG. 2 is a principle diagram for switching a substrate potential.

FIG. 3 is a circuit diagram in a case where a switch for switching a substrate potential is constituted by a MOSFET.

FIG. 4 is a diagram illustrating four modes according to states of a logic circuit unit and an SRAM unit.

FIG. 5 is an explanatory diagram for explaining a control mode of a substrate voltage when the semiconductor device has a logic circuit portion and an SRAM portion.

FIG. 6 is a schematic circuit diagram when a pumping circuit is used as a circuit element for changing a substrate potential.

FIG. 7 is a configuration diagram showing one SRAM.

FIG. 8 is a circuit configuration diagram when the SRAM is configured by MOSFETs.

FIG. 9 is a circuit configuration diagram for selecting an SRAM.

FIG. 10 is a graph showing a relationship between a gate voltage and a drain current of a transistor.

FIG. 11 is a configuration diagram showing a state when charging / discharging a load capacity by an SRAM;

FIG. 12 is a diagram illustrating a through current flowing through a pair of transistors included in the inverter.

FIG. 13 is an explanatory diagram for explaining a leak current.

FIG. 14 is a conceptual diagram showing an FPGA.

FIG. 15 is a diagram showing a case where a pass transistor is switched by one SRAM.

[Explanation of symbols]

1 ... SRAM (SRAM section), 4, 5 ... M of SRAM section
OSFET, 16A, 16B, 17A, 17B ... switch, 18, 19, 20, 21 ... MOSFET (circuit element for changing substrate potential) as pass transistor, 30 ...
Pumping circuit (circuit element for changing substrate potential).

Claims (10)

[Claims] In a semiconductor device having an SRAM section, a circuit element for selectively changing a substrate potential of the SRAM section is provided, and the circuit element is used to control the M of the SRAM section.
A semiconductor device characterized in that a threshold voltage of an OSFET is changed. 2. The semiconductor device according to claim 1, wherein said SRAM section is divided into a plurality of sections, and wherein a substrate potential is changed for each divided section. 3. The semiconductor device according to claim 1, wherein said circuit element is a switch for connecting to an outside having said substrate potential. 4. The semiconductor device according to claim 3, wherein said switch comprises a pass transistor comprising a MOSFET. 5. The semiconductor device according to claim 4, wherein the pass transistor uses an nMOSFET when lowering the substrate potential, and uses a pMOSFET when raising the substrate potential. 6. The semiconductor device according to claim 1, wherein the semiconductor device has a pumping circuit as the circuit element, and the substrate potential is supplied by the pumping circuit. 7. The MOSFET of the SRAM section, wherein a substrate potential is set so as to lower a threshold voltage at the time of writing and a substrate potential is set so as to raise the threshold voltage at the time of holding. 7. The semiconductor device according to any one of 1 to 6. 8. The semiconductor device according to claim 1, wherein said semiconductor device is a field programmable gate array (FPGA). 9. The semiconductor device according to claim 1, further comprising a logic circuit portion, wherein the logic circuit portion is configured to be capable of controlling a substrate potential and changing a threshold voltage separately from the SRAM portion. The semiconductor device according to claim 1, wherein: 10. The substrate potential of the logic circuit unit according to claim 9, wherein the threshold voltage is set to be high in a standby state and to be low in an active state. Semiconductor device.