JPS58211391A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To realize the high-speed reading, by switching one of two power supplies of a static memory cell to the third power supply during the reading of a memory cell and therefore increasing the potential difference of a memory compared with the potential difference of a pause mode period of the memory. CONSTITUTION:A memory cell consists of resistance element loads R1 and R2, transistors T1-T4 and a pair of bit lines BL and BL'. The high and low potential voltages of the memory cell are set at the VDDC and SDDC respectively, and the back gate voltage of transistors T1-T4 is set at VXBN respectively. Thus the potential difference between a power supply VDD and the other power supply -VB of the memory cell can be increased compared with the pause mode period of the memory. This ensures the high-speed reading.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The problem of failure occurs in static semiconductor memory devices in which a circuit memory is used as a memory for a one-chip microcomputer.

[Departure technique + Tos behind and its problems] As memory becomes more integrated and bulkier, the memory cells connected to the bit line become smaller and their 1mm m+ capacity becomes smaller. Become. On the other hand, the number of memory cells connected to one focus edge increases, and the capacity of the bit line increases. Therefore, the time it takes for one memory cell to drive a pair of bit lines and create a potential difference between them that can be used for reading increases, and therefore the time required for reading data becomes longer. Furthermore, % of memory for low oil consumption and electricity consumption.
Or, it has become necessary to take a step out of IIi,
In this case, the capacity of the memory cell is further reduced, and the length of time between input and output of the memory cell is becoming longer.

In order to reduce the electrical capacitance of the focus line that acts as a load, there is a method to minimize the drain area of the transfer transistor of the memory cell connected to the bit line to reduce its diffusion capacitance. To meet you (l)) Cell no Kakeru! t
In order to improve the III capability, a method has been used to increase the gate width of the cell transistor. However, the former (
In method b), the minimum drain sandalwood of the transfer transistor is a bottle formed by the drain and the metal wiring dove)
Therefore, the diffusion capacitance of the bit line cannot be made very small. However, as transistors become smaller, the punch-through breakdown voltage of the transistor becomes lower, so it is necessary to increase the substrate concentration. On the other hand, in the latter method (b), increasing the gate width of the transistor leads to an increase in the cell size.
This can be done if the cell pattern has some extra area, but if there is no extra cell area, the only thing you can do is increase the gate width of the transistor by 10%. is also extremely difficult to realize.

[Purpose of the invention]

The present invention was made in view of the above-mentioned problem, and is easy to use compared to the conventional method of reducing the capacitance of a bit line or increasing the gate width of a cell transistor, which is physically difficult. Furthermore, the present invention provides a semiconductor memory device that can effectively shorten the read time.

[Summary of the invention]

That is, in the semiconductor memory device of the present invention, one of the 2 power sources to be supplied to the static memory cell, *=, is switched to the 30th power supply when the memory cell is input/output, and this switching causes the 2 power supply of the memory to be switched to the 30th power supply. This is a power supply switching means for increasing the potential difference between the memory and the potential during the sleep mode period of the memory by an order of magnitude of VH.

Therefore, read! 1, that is, the X potential difference between the two voltages supplied to the memory cell during the read mode or all or part of the read cycle is larger than the potential difference during the rest mode period, so the focus line by the memory cell is The drive'*)I capability is increased and high-speed read operations can be performed.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings. First, the principle of the present invention will be explained. Figure 1 shows the static memory cell -? lL℃ resistance element load and enhancement type IK dynamic transistor i1 A pair of E/R type mesememory cells bit lines BL, BL and word iW
It shows the connection with L. However, here, both the memory cell drive transistor and the transfer transistor are N-channel transistors. The memory cells are arranged in the row and column directions, and the pins IfMBL and BL of -2 are commonly connected to the memory cells in the same column, and one word line WL is commonly connected to the memory cells in the same row. has been done.

In the above memory cell, one end of the valley of the resistive element R,, it, is connected to the first 1 kL source VDD on the high potential side, and the other end (node fl) of the resistive element Imo and the first 1 kL source VDD on the low potential side. An enhancement type N-channel transistor (O8) transistor (driving transistor) Tt is connected between the voltage 1M1 (-VB) of 2 and the other end (node L) of the resistor element 1M1 (-VB).
N of enhancement w between and the second power supply (VB)
Channel MOS transistor (drive transistor) T
2 is connected, the gate of this transistor '1' is connected to the node II, and the transistor Il'+
The gate of No. 8 is connected to the node L. moreover,
An enhancement-type N-channel transistor (transfer transistor) T& is connected between Ail 1iI2 node H and pinto iBl, and an enhancement-type N-channel transistor (O8) is connected between the previous node L and the bit edge BL. Kunster (transfer transistor)'r4
and for these transfers) -y y i;y star', [', , T4 nogate Howard @Wl,. Furthermore, the pack gate voltage of each of the transistors 'I'1 to T' is set to a voltage of -vB.

Assume that in the memory cell above, the transistor T is now off, the transistor T2 is on, the node H is still at a level 0, Vn, and the node L is at a low level transition 2L. Konotosa, Vn HaV
DD * Pressure - C: At J, VL + 1 - VB'y Pressure is 0 Here, pit gland B17 ¥ 1 person level - ■L
Figure 2 shows the characteristics of the voltage V versus the voltage bLI between the source and drain of the Kunister '1'2, which is drawn in by U+). Here, vT is the threshold voltage of the driving transistor T2, and the dependence of the threshold voltage on the substrate bias is ignored for the sake of simplicity. Vn"OV To-VB=-VBIMoL<HaVB2ToKOkiru+e The difference in characteristics lies in the fact that the source potential of the drive transistor '■'2 is different, and therefore the gate potential V
Even if H is constant, the gate potential differs depending on the source potential, and depending on the value of -VB, the 'I' of the spiral transistor 'J' mushroom
[The flow driving ability is significantly different.]

Low level potential■L is much smaller than VnVT by +J,
Therefore, the drive transistor '1'2 performs triode operation, and the difference in the V-I percentage of the drive transistor T2 due to the difference in the -■B potential is due to the difference in the V-I ratio between the source and drain as shown in FIG. Tonde■ is the difference in the rise near Ov. It can be seen that the more the -vB potential becomes a negative potential instead of Ov, the greater the ability to pull in the voltage WJ+ with respect to ILK.

FIG. 3 shows the pull-in time T from the precharge level to the low level potential side of the bottle illilHL which burns to -VB potential in the memory cell of FIG. 1, and -VB
The larger the negative voltage is, the more the cell's pull-in driving ability increases, and the bit-reading time T becomes correspondingly shorter. Also the third
The relationship shown in the figure holds true.

Therefore, the present invention provides a power supply VDD for one side of the cell and a power supply for the other side.
By making the potential difference between the memory and the memory (-VB) larger than the memory's rest mode period when entering the bladder, high-speed reading is performed.

Hereinafter, an example of a combination in which the present invention is applied to a Yuzu type state ink memory cell will be described.

First, let me explain the nomenclature of memory cells.''・5.

Of the E/1 type cells, the N-channel type is called the RN cell, the P-channel type is called the RP cell, and the CM (, l
Among S-type cells, those with N-channel transfer transistors are called CN cells, and those with P-channels are called CP nacelles. Figure 4 (a) shows a simplified example of application to f(, N cells. The details are shown in FIG. 4(b).

Note that the voltage on the high potential side of the cell is VDDC1, the voltage on the low voltage side is vSSCs, the back gate voltage of transistors 1'1 to T is VXBN, the word line is WL, the pair of pit lines are B1, i31... It is expressed as

FIG. 5(a) is a simplified illustration of an example of application to a P-cell, and the details are as shown in FIG. 5(b).

Here T, 1~Ill, / is P channel MO8)
The transistors R and R are resistive wires, and the bank gate voltage of the cell is represented by vxitp, and the other representations are the same as in FIG.

FIG. 6(a) simply shows an example of application to a CN cell, and the details are as shown in FIG. 6(b).

FIG. 7(aJ) schematically shows an example of application of the CP nacelle, and its details are as shown in FIG. 7(b).

In addition, in Figures 6 and 7, l115~T8 are N channel MO8) Run y, x, evening, 1゛,'~T
, ' is a P-channel MO8) transistor, VDDC is a high potential 111tl voltage, V SSC is a low potential side source, VA
N and VXJ3p are the puncture gates of the 1N channel transistor and the P channel transistor, respectively.
The impurity is supplied to the semiconductor substrate and the impurity diffusion j-, which is of a conductivity type opposite to that of the semiconductor substrate and which is provided in the semiconductor substrate.

Figures 8 to 11 show 'Toei' voltage control voltages selectively cultivated in the memory cells shown in Figures 4 to 7 above, and VDD and VSS are used in peripheral areas other than the memory cells. Two LEs used in the circuit (VDD>VSS
) Teal o VBBS Oyohi VB13Dki'c each above 2'th, 3rd frost outside the source's 1 pressure range, monument voltage -Cara 1, VBBS<VSS, Vnnp
>Vr) D-C Allo.

vDI)', 'VSS/ is the fourth is, Vs
s<VDD/<VDL), VSS, VssJ<
Vvo-C allo. Conformation, 3rd and 4th 'power supply'
Potential difference I VDDIVBBS l, l VBIID
Vssi is the '1L level difference between the two voltages of the memory cell during the sleep mode period of the memory, that is, l VIJD VSS
It is set to be larger than l.

(1) The first embodiment has a memory cell shown in FIG. 4 or 6, and the power supply voltage ratio of this memory cell is as shown in FIG. 8. VA L Teha VDDC
=VDD, VSSC=VXBN=VBBS KF
a, and in the case of Fig. 6, vxttp≧'l/n
set to oc.

(2) The second embodiment has a memory cell shown in FIG. 5 or FIG. 9 L Teha VDLIC
=VXBP=VB13D + VSSC=VSS K
In addition, in the case of Fig. 7, VXBN≦V8SC
is set to

According to the above-mentioned first and second embodiments, at the time of reading the memory cell, at least one of the electric potential side electric erosion ratio vDl) Cs low potential side power supply plow and pressure The voltage of the third power supply is outside the voltage range 12H (VDD to VSS) of the two power supplies for driving used in peripheral circuits other than VBBS or VBBD, and the iMov
Celno 2 VtX'l! V position M IVnD-Vnsl
, IVBBD-Vssl is larger than the potential difference IVDD VSS l between the two power supplies of the memory cell during the sleep mode period, so the Vss for the cell hint a
The pulling force in the direction of the Wt source voltage or VDD voltage output increases, and as described above with reference to FIG. 3, the bit line pulling time T becomes shorter, and the read time decreases. was 5 to 20% shorter than before.

(3) The third embodiment has a memory cell shown in FIG. 4 or FIG. 6, and the power supply voltage of this memory cell is the voltage relationship shown in FIG. Put it on the protrusion vI
)L)C=vl)J)' 5SC=vXBN=VB
BS, and in the case of FIG. 6, VXBi'≧V
DL) is set to S.

(4) The fourth example has a memory cell shown in FIG. 5 or FIG.
Two power supplies are provided, and the VNOE is available for reading and hanging.
= vX) 3P = VBBD, VSSC = VSS
', and in the case of Fig. 7, VXBN≦VSS
Set to S.

According to the third and fourth embodiments described above, during reading, a third power supply Vno, which is different from the driving 2' mVno, Vss used in the peripheral circuits other than the memory cell, is used.
nus or VBBD and a fourth power supply VDD' or VSS' serve as two power sources for the memory cell, and the potential difference between the third and fourth power supplies is set to be larger than the potential difference between the 2' power sources of the memory cell during the sleep mode period. In order to keep
The ability to drive the i to the bit line of the cell increases, and the third
As mentioned above with reference to the figure, the bit line pull-in time T is shortened, and the threading time t11 is 5 to 20 minutes longer than before.
Mantan Tsumugi was made.

In addition, in the first and third examples of the previous b pi, ■yu,””
Although it is set to VBBS, it is also possible to provide a power supply with a voltage lower than VBBS and set the voltage of this power supply to VXBN.Also, in the second and fourth embodiments, %VXliP"
'I set it to VBBD, but the voltage is higher than VBBD'
A power supply may be provided, and the 'rk pressure of this power supply may be set to vXJ3p.

Next, when reading the memory cell, one of the memory cells' IIQ is set to equalize the voltage difference between the two voltages of the memory cell to make it larger than that between the sleep mode JQI. We will now explain fifth to eighth embodiments in which the reading speed is increased.

(5) Fifth Embodiment With an RN cell as shown in Fig. 12, and an RN cell as shown in Fig. 8, (V 1) L)>V SS>V Bns
)'>w yx Kame+-t-, and VDi
x:=Vr)■), Vxb+1=Vnns,
VSS La (7t) (for a song with Luno VSSC line?'1
ill (Illil 'M'4. Between the N channels gated by the voltage Vin, + 08) Connect the transistor N1 between the VBBS line and the cell 0') V ssc line by the divisible voltage Vin2 Gate T+1
N channel Mss) is connected with a transistor N2. The rest mode period is V in
.

is the sieve level voltage, Vin2 is the low level voltage 1,
) The Kunister transistor N is on, the transistor N2 is off, and the voltage is 5sc-VSS. If we divide this into a statement and read it out, Vin is the low level voltage, and Vin2 is the low level voltage.
becomes a bell voltage, transistor N8 turns off, transistor N turns on, and V 88C""V B]
3S, and the memory cell's 2nd line voltage VDDC・v ssc
(6) Sixth embodiment has a CN cell as shown in FIG. 13, and as shown in FIG. 14! Yona l1m%ノ(vol)>Vss/>Vss)
Using 91 volts, vI)DC=vXBP=vDD
, VXBN-vss, connect an N-channel transistor N between the 'VSS line and the v ssc line of the cell, apply the above-mentioned Vin to its gate, and connect it to the v ssc line of the VSSSS fin. In this case, an N-channel transistor N2 is connected between them, and V in, as described above, is applied to its gate.

Therefore, compared to the potential difference (lVl)D-VSS/l) between the two voltages of the cell during the sleep mode period, it becomes VDD-vss during reading, which is relatively large.

(7) Seventh embodiment As shown in Fig. 15, it has an RP cell, and uses the power supply voltage with the relationship (VBBD>VDD>VSS) shown in Fig. 9L - vssc = vss, v) a3p =viD, P-channel transistor P1 whose gate is opened by voltage Vin1 between VDD line and VDD line
, and a P-channel transistor p2 whose gate is turned on by an open-side voltage ratio Vin2 is connected between the VBBD line and the cell's VDDC line. During the sleep mode period, Vin is a low level voltage, Vin
2 is at cylinder level voltage, transistor PK is on,
Transistor P2 is off and VDDC''VDD.

On the other hand, when the public is turned on, Vin is still at a level voltage, Vin2 is at a low level voltage, transistor P is turned off, transistor P2 is turned on, and VDD
C=VBBI) Tona IJ, J MoIJ Cellno 2 Electricity mtVDDC, V SSC The potential difference becomes large.

(8) Eighth Embodiment A CP cell is provided as shown in FIG. 16, and the electrolytic erosion voltage with the relationship (VDD>VDD ・> Vss) as shown in FIG. 17 is used. %VsSC=VXBN=VSS ,VX
IJP = VDD, and VDD' line and cell V
A P-channel transistor P1 is connected to the DDC line.
and apply ~in to its gate as described above, and connect P between the VL)D line and the VDDC line of the cell.
The channel transistor P2 is connected and the aforementioned Vin2 of 5 is applied to its gate. Therefore, the potential difference of the 2vL source of the cell during the rest mode period IV
Compared to DD/Vssl, it is IV when reading.
DI) - VSSI, which becomes relatively large.

Next, when reading the memory cell, the two power supplies of the memory cell are switched to make the potential difference between the two power supplies of the cell wider than that in the sleep mode period (and thus the read speed is increased). - A fourteenth embodiment will be described.

(9) Ninth embodiment As shown in FIG. 18, it has a 1-CN cell, and as shown in FIG.
C: T, J: 5 IN 4A (VBBD>'V
DD>VSS>VBBS) Ili source 'F'6. N-channel transistor N, gated by a control voltage Vin, between the VSS line and the Vssc line of the cell, using VXjJN = VB23S,
Connect a voltage group between the VBiiS line and the cell's VSSC line. by game) fblJ m
Connect the N-channel transistor N, which is
A control voltage V is applied between the DD line and the VDDC line of the cell.
Connect a P-channel transistor P3 whose gate is controlled by in, and connect the VIIBD line and the cell's VD1℃
Open side 1 voltage Vin between line and gate) ft
A P-channel transistor P4 controlled by tlJ is connected. The rest mode period is V in.

and Vin4 are sieve level voltages, V in, and V in,
is at a low level voltage, transistors N and P3 are on, transistors N and P4 are off, and VSSC
=vss-VDDC=VDD. On the other hand, Vt
In terms of input and output, Vin3 and Vin are at a low level.
The switching ratios V in and V in become high-level voltage ratios, transistors N and P are turned off, and transistor N4
and P4 is: t njJ, VSSC=VBBS,
VDDC=VBBD Toner+J, memory cell 2
Permissive Vptx: The potential difference between Vssc increases.

(10) 10th Embodiment In Fig. 19, add the RP cell to Boss 5 (Mamoru also shows 4 in Fig. 21).
VXBP
=V BBD, and the operation according to the ninth embodiment is performed, except that the fIli of the cell used and the voltage applied to the puncture gate of the cell are different from those of the ninth embodiment.

(11) Eleventh embodiment As shown in FIG. 20, it has a CI υS cell (CN cell in FIG. 6 or CP cell in FIG. 7), and the electrolytic erosion voltage has a relationship as shown in FIG. 21. and Vxin=VBn
s, VXBP=VBBL) t L fc Monoteatte, compared to the above-mentioned H4'9th Example, the only difference is the type of cell used and the cell bank gate application pressure, and the order of the 9th Example is different. The action is performed.

(12) Twelfth Embodiment This device has an RN cell as shown in FIG. 22, and uses an electrolytic erosion voltage having the relationship (VDp>VnoI>Vsy>Vss) shown in FIG. 25, and as shown in FIG. and the 21st
VBBI), VDD of the 9th example described above with reference to the figure
, VSS, VBBswo%N
D, VDD/', Vss', and Vss, the operation is faster than that of the ninth embodiment.

(13) 13th Embodiment The circuit shown in FIG. 23 has an It P cell at 5, and the power supply voltage used is similar to that shown in FIG. 25.
The power supply voltage of the 10th embodiment described above with reference to FIGS. 19 and 21 is replaced by the power source 1A shown in FIG. It is done.

(14) 14th embodiment As shown in Fig. 24, it has a CMOS cell (CN cell in Fig. 6 or CP cell in Fig. 7), and uses power supply voltages as shown in Fig. 25. is Q], and the 20th
The tkj *it voltage of the 11th embodiment described above with reference to FIG. V) Crops are made.

Next, the open side 1 voltage Vi in the fifth to fourteenth embodiments
The generation circuit for n, ~Vin, will be explained.

In the 26th 1, 20 is an open side 1 electric ratio generation circuit, 21
22 is a column decoder, 22 is l(, C (ridge C output/input) control circuit, N and N6 are channel transistors for bit lfM selection, SL and SL are sense 1N, N
v and N are channel transistors for charging the sense line, 23 is a sense amplifier, and although the electrolytic lines of the cell are not shown, -il pins) iBL, Bl,
Cells connected in co-trace are connected to the same %L source supply line. The control voltage generation circuit 20 includes a CMO8 inverter C1 consisting of a P-channel transistor P and an N-channel transistor N, and a P-channel transistor P. and an N-channel transistor NIo are connected in two stages, and the output of the previous stage inverter CI is set to V.
o, , and the output of the subsequent inverter C1□ is expressed as Vo.

Now, in the circuit shown in Fig. 26, the cell electrolytic connection relationship is i.
II, No. 5, Ninth Example (Fig. 12) or No. 6 Example (2
4S (Fig. 13), the power supply voltages VDD, , vss of the control voltage generation circuit 20 and the sense line precharge transistor N7. N.

power supply voltage V'DD, and bank gate voltage ratio v' b
s1ka'c Resole%J rr-1L Te death 12 Figure no VDD, VBBS, VDD.

VBBS Alui LL m 13 Figure no vI) D, vS
S, Vl) D, Vss.
O,= V in, , V(,2= V in2
Wire it so that On the 1t/W control side 12, the output node C becomes a low level potential during write input and sleep mode, and VOI=VDD, (Rashibe/+1 pressure), VO2=VSS□ (low level voltage ). On the other hand, when extracting the h element, the output node C has the same potential as the output Vc of the column decoder 2, and when Vc becomes a high level potential when selecting a column, the output node C becomes V. 1-Vss, ,VO
2-VDD. Once upon a time, when I took out the people, I used a pair of bins (BL) that were carefully selected.

All cells connected to BL are supplied with 2m
The power supply ratio σ) has a large level difference (1111), and the voltage is connected to one selected word gland whose potential is still at level ' voltage among the word glands WL to which those cells are connected. The pair of transfer transistors in the selected cell becomes the main element, and the large driving force of this selected cell "C bin F 7 BL
, ljL has low mastication pressure 11111
A pair of sense &amp;
! sL, l, and is further amplified by the sense amplifier 23 and output as a read signal. ◎In addition, in the above FIG. (Fig. 22), Fig. 26 σ) Vss1. VDDl, v′ss1
．． The R/W control circuit 22 is wired so that v'DD□ corresponds to "Cm 18". Output node C during power-on and sleep mode
becomes low level'k VOIoVDDt 5vQ
2'''Vs$1.On the other hand, when the read peak is reached and a column is selected, the output node C is still at level 4 voltage, and Vo+=V8S11VO2=VDD1. The operation is similar to that of the fifth and sixth embodiments.

Furthermore, in FIG. 26, in P1]ii, the cell connection relationship is that of the 11th embodiment (FIG. 20) or the 14th embodiment (FIG. 24), and the cells are shown in FIG. 6, respectively. When such a CN cell is used, it may be connected in the same manner as the power supply system and the open-side voltage system in the ninth or twelfth embodiment, respectively, which are respectively installed above.

In FIG. 27, a P-channel transistor P is used for bit selection, and P-channel transistors P7 and P are used for charging the P sense line, and column decoders 21' and 1 are used. A level logic type is used, and the output of the inverter C11 at the front stage of the control voltage generation circuit 20 is 1.
2 output V. , and the electrical rectangle of each part, lE, is expressed as R11<Vl)l)2゜vss2IV' DD2
, V' SS2 is also 0), so is c/), and so is the same as in FIG.

Now, in step 27, if the cell power supply connection relationship is that of the seventh embodiment (FIG. 15) or the eighth embodiment (step 1614), VDD2*■SS2+v' in FIG.
1JD2-”8S2 cut L sotlljlc, L
vBBD, ■ss, VBBt), VsS in Figure 15 or VDD, Vss, VD19. in Figure 16. Apply voltage 4k Qt 13 so that it becomes VsS, ■ox=Vmnt
, Vo, = V in2 . The above-mentioned 1st power control cycle 22' is 1st power Voa when the output node C is at the city level potential during cooling and in the rest mode.
= V SS2 (low level voltage) VO4=VDl
)2 (b level voltage). On the other hand, when extracting the FU, the output node C is the output of the column decoder 21'
c is at the same potential, and when vc is at a low level when selecting a column, Vos "" VDl)2, VO4-
It becomes VSS2.

Once upon a time, a samurai who was going to make an appointment had to select a column. , a pair of transfer transistors in one selected cell connected to one selected word line whose potential has become a low level voltage among the word lines WL to which those cells are connected are turned on, and the large Focus line HL with driving force,
Either one of BL is pulled to the iTh'rW voltage side, and the hit line' is connected to the transistor P5. P
6 and is transmitted to the sense lines SL, SL, and is amplified by the sense amplifier 23 V (-) and output as a signal 117r.

In addition, if you are located in the 27th Ward 1 and the cell power supply connection is the 1st example (Figure 19) or the 13th example (
271zlc') V
SS2. VDD2. V'5S21V'DD2 Kasoreso iii; J OL Te'720 lea ノVBBS, V
BBD, VSS, VIJD Aluiha 24th m VS
S, VDD, V'SS, V'DD Tona7,,) Yo'
It is good to wire K*mQt to 5.

Furthermore, in t11He FIG. 27, the cell 'passage/false ξ relationship is that of the 11th embodiment (FIG. 2()) or the 14th embodiment (X!24), and is shown in FIG. 7, respectively. When such a CP nacelle is used, connection misalignment can be avoided in the same way as in the power supply system and the control 'public pressure system in the eleventh or twelfth embodiments described above when mowing the land.

In addition, 1till in FIGS. 26 and 27 mentioned above
fill 'Gravity ratio generating circuit 20 is 0 to 108 circuits (114 circuits'), s'74<L k is enhancement type transistor; Of course, it may be of the '=?s configuration.

In addition, in each of the above embodiments, in addition to the power supply voltage ratios VDD and VSS, which are also used in peripheral circuits other than memory cells, *m voltages VBBD and VB used in memory cells are also used.
BS, V'DD, and V'SS may be supplied from outside the memory, or may be output from a substrate bias generating circuit as described below.

In Fig. 28, inverters 11 to 13
The output terminal of this A oscillator is connected to the inverter 14 and the VBIJS node in the column, and this node is connected to the diode D formed by +114 by the N channel fault circuit. Vsst source (ground point) via □ in the forward direction
A smoothing capacitor C2 is connected in parallel to this diode DI. Therefore, u of the oscillator
1 power is increased by 1 by inverter 4, and this output turns off capacitor C1 and performs a charge pump to the VBBS node.・The VSSSS voltage is increased by 1, and the negative voltage lower than the VSS voltage is smoothed by smoothing Rontin +C2.Thus, the 2' voltage source of the peripheral circuits from the memory cell onward is applied to the VBBS node. , VlIB81M, which is outside the voltage range of VSS, the source voltage is underestimated.

In FIG. 29, inverters 11' to 13' constitute a ring-on latrator, and the output terminal of this oscillator is connected to the voltage V via inverter L/ and capacitor C1 in series.
It is connected to the BBD node, and this node is connected to VDI) IN Git via a diode IJ2 formed by a P-channel transistor in the reverse direction, and a leveling capacitor C2 is connected in parallel to this diode D2. Therefore, the oscillator's m power is amplified by the inverter l/, whose output valves the capacitor C1 to charge pump to the VBBD node, where a voltage of 11 lower than the pressure at VDD' is applied to the diode 1.
)2, and the voltage difference between the VDD output and the output voltage is smoothed by smoothing Contin-9-02.

In this way, the VIIHD node has two sources of peripheral circuits other than memory cells, VDD and VSS, which are outside the voltage range.
HD power supply voltage is superior.

In FIG. 30, i N-channel transistors N
11 to N11 are connected in series, and each transistor "II to
Vss tt pressure is applied as the Nth bank gate paper pressure, and the DD power supply is connected to the drain of the upper i6+::F transistor NII. However, Tani Tokunjista N1. ~Nli performs a pentode operation, and the voltage V' from the source of the Nth transistor to the intermediate region between VDD and VSS increases because the drain voltage of the valley transistor N, -Nli is lowered by the threshold value 1alE with respect to the source voltage and voltage. DD
is obtained.

In Figure 531, j P-channel transistors PII to PlJ are connected in series, a seven-plane voltage is applied as a puncture gate voltage to each transistor pH to Ptj, and a VSS power supply is connected to the source of the transistor pH. There is. Therefore, each transistor PII~P+j
performs pentode operation, and the valley transistor 'II~p I
VS from the drain of transistor PIJ due to a threshold voltage increase of 2'' to the source voltage of the drain voltage of transistor PIJ.
An intermediate load voltage V'Ss between S and VDD is obtained.

In addition to the RAM of the above embodiment, the present invention also provides t(JM
0 [Effects of the Invention] In accordance with the above-mentioned points 7 and 5, the semiconductor memory device of the present invention has the advantage that when the potential difference between the two power supplies supplied to the static memory cell is determined, This makes it easier and more effective without the problems associated with methods of reducing the bit line gap or increasing the gate width of cell transistors. This can be done by shortening the overflow time.

That is, as a result of implementing the present invention, the read time can be shortened by 5 to 209b as compared to the conventional memory in which the potential difference between the two power supplies of the memory cell is not switched when the memory cell comes of age.

[Brief explanation of drawings]

Figures 1 to 3 are shown to provide a detailed explanation of the present invention. Figure 1 is a circuit diagram showing the h:/R type state ink cell, Ichigen's focus line and word line, and Figure 2 is a circuit diagram showing the focus line and word line. is a diagram showing the voltage and current characteristics of the drive transistor of the memory cell in FIG. 1, and FIG.
VB) Figure 4 fa) (b) to Figure 7 (a) and (b) show the first to fourth practical JM examples of the present invention. Figure (a) shows a simplified circuit diagram, Figure (b) shows a detailed circuit diagram, and Figures 8 to 11 show the magnitude of the voltage of the power source 'r in the first to fourth embodiments. 12 is a circuit diagram showing the fifth embodiment, FIG. 13 is a circuit diagram showing the sixth embodiment, the 14th factor is a diagram showing the power supply voltage relationship in FIG. 13, and FIG. A circuit diagram showing the seventh embodiment, FIG. 16 is a circuit diagram for the eighth embodiment, FIG. 17 is a diagram showing the power supply's pressure relationship in FIG. 16, and FIGS. 18 to 20 correspond to each other. FIG. 21 is a circuit diagram showing the ninth to eleventh embodiments, and FIG.
The diagrams illustrating power supply voltage relationships in FIGS. 20 to 20 and FIGS. 22 to 24 correspond to the 12th to 14th figures b (!
Figure 25 is a diagram showing the 1Ji source voltage relationship in Figures 22 to 24, and Figures 26 and 27 are control diagrams for the Tanihigashi example in Figures 12 to 25. The circuit diagrams shown in FIGS. 28 to 31 are shown in order to explain the voltage generation and supply system.
It is a circuit diagram that does not include a voltage generation circuit for electric voltages other than DD and VSS. T, , 11%, LL+,) A+, 1+I+,
1... Transfer transistor, Bl, , LIL ・,
Hin) 6J, Wl, 1. ,'7-t+lff1,V
D.D. Vss, VBBD, VBllS, vDtf, V
SS'-'rbi, Gen'kame LE, VXIIN, v
xap... Back gate power supply voltage, + N2
+ PI + P2...Power supply I7I dust transistor, N5 + NO+ p511'6... Bit error selection transistor, 20...1 to 1] Mitunta generation circuit, 2... Column Tecoder. Client representative Patent attorney Takehiko E Takehiko Ryo Figure 1 vB Figure 2 - μm 1v Figure 3 Figure 4 (a) (b) VX cell VSSC SSC Figure 6 (a) (b) Figure 8 Figure 9 Figure 12 Figure 13 Figure 14 Figure 15 Figure 18 Figure 19 Figure 20 Figure 21 Figure 1 VDD l vss □ VBBS Figure 22 Figure 23 Figure 24 Figure 25 r: Salmon NowFigure 26Figure 27Figure 28

Claims (1)

[Claims] fl) A plurality of state ink memory cells arranged in the row and column directions, and a pair of transfer iVi OS in each of the memory cells in the same column; The focus line, the word line commonly connected to the valley gate of the transistor in each of the memory cells in the same row, and the source 2 which should be supplied to the memory cell 1Jii+ of the memory cell. A half-unit body comprising a power supply switching means that switches to a third power supply when reading the memory cell, and makes the potential difference between the two power supplies of the memory cell larger than the potential difference during the sleep mode period of the memory by this switching. 1 Breathing device. (2) The third power source is different from a 2' power source used in peripheral circuits other than memory cells, and has a voltage outside the voltage range of this 2 W. 2. The semiconductor memory device according to claim 1. (3) The third power source is one of two circuits used in peripheral circuits other than memory cells. (4) The semiconductor memory device described in Patent No. (5) The above @40 power supply is different from the 2 power supply used in peripheral circuits other than memory cells, and this 17) 2 power supply is outside the voltage range of the 2 power supply. (6) The fourth power source is a peripheral circuit other than a memory cell, and the voltage is on a different side from that of the third power source. The patent ml is characterized in that the voltage is in the middle region of the 'voltage range of these two lines, unlike the two lines used in this patent.
Ice range: The semiconductor storage device according to item 4. (7) The third power source of A'tJ is supplied as a puncture gate power source to a semiconductor substrate or an impurity diffusion layer of a conductivity type opposite to that of the semiconductor substrate provided in the semiconductor substrate. A semiconductor memory device according to scope 1. (8) The semiconductor memory device according to claim 4, wherein the fourth power source is supplied as a puncture gate power source. (9) The third power supply is supplied from outside the memory or used in a peripheral circuit other than the memory cell.
The semiconductor memory device according to claim 1, characterized in that it is produced by a voltage generating circuit operated by a power source. (10) The fourth power source is generated by a voltage generating circuit operated by a 2' source supplied from outside the memory or used in a peripheral circuit other than the mesori cell. The semiconductor memory device according to scope 4. (11) The static memory cell is an E/R type mesememory cell, and all of the enhancement type transistors used therein are N-channel or P-channel type. semiconductor storage device. (12) The conductor arrangement device according to claim 1, wherein the front b vistatic memory cell is a CMO8 memory cell. (13) An open-side breakdown voltage for switching the power supply switching means is generated based on the column decoder output applied to the gate of the focus line selection transistor connected to the bit line in the front lobby. Claim 1. The semiconductor memory device described in LJt.