JP3102179B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit composed of fine MOS transistors, and more particularly to a circuit suitable for high-speed and low-power operation.

[0002]

[Background Art] 1989 International Symposium on VSI Technology, Systems and Applications, Proceedings of Technical Papers (1989
(May) Pages 188 to 192 (1989 International
Symposium on VLSI Technology, Systems and Applicat
ions, Proceedings of Technical Papers, pp.188-192
(May 1989)), as the MOS transistor is miniaturized, its breakdown voltage decreases, so that its operating voltage must be lowered.

In this case, in order to maintain the high-speed operation, it is necessary to lower the threshold voltage (V _T ) of the MOS transistor in accordance with the lowering of the operating voltage. This operating speed, the effective gate voltage of the MOS transistor, that is, ruled by a value obtained by subtracting the V _T from the operating voltage is because fast as this value is larger. However, when V _{T is set} to 0.
When the voltage is set to about 4 V or less, as described below, the sub-threshold characteristic (tailing characteristic) of the MOS transistor makes it impossible to completely turn off the transistor, and a phenomenon occurs in which a DC current flows.

A conventional CMOS inverter shown in FIG. 6 will be described. Ideally, when the input signal IN is at a low level (= V _SS ), the N-channel MOS transistor _MN is off, and when the input signal IN is at a high level (= V _CC ), the P-channel MOS transistor _MN is turned off.
The S transistor M _P is turned off, and no current flows in any case. However, the MOS transistor V
_{When T} decreases, the subthreshold characteristic cannot be ignored.

As shown in FIG. 7, the drain current I _DS in the subthreshold region is proportional to the exponential function of the gate-source voltage V _GS and is expressed by the following equation.

[0006]

(Equation 1)

[0007] However, W is the channel width of the MOS transistor, I _0, W ₀ is the current value and the channel width in defining the V _T, S is tailing factor (inverse of the slope of V _GS -log I _DS characteristics) is there. Therefore, even if V _GS = 0, the subthreshold current

[0008]

(Equation 2)

Flows. Since the transistor in the off state in the CMOS inverter of FIG. 6 has V _GS = 0, the above-mentioned current _IL flows from the high power supply voltage V _CC to the low power supply voltage V _SS which is the ground potential during non-operation. Become.

[0010] The sub-threshold current, as shown in FIG. 7, when lowered to V _T 'of the threshold voltage from V _T,
Exponentially increases in I _L 'from I _L.

As is clear from the above equation, in order to reduce the subthreshold current, it is only necessary to increase V _T or decrease S. However, the former causes a reduction in speed due to a reduction in the effective gate voltage. In particular, if the operating voltage is lowered along with the miniaturization from the viewpoint of the withstand voltage, the speed drop becomes remarkable, and the advantage of the miniaturization cannot be utilized, which is not preferable. The latter is difficult for the following reasons, as long as it is operated at room temperature.

The tailing coefficient S is expressed as follows by the capacitance C _OX of the gate insulating film and the capacitance C _D of the depletion layer below the gate.

[0013]

(Equation 3)

Here, k is Boltzmann's constant, T is absolute temperature, and q is elementary charge. As is clear from the above equation, C _OX
Irrespective of C and C _D , S ≧ kT ln 10 / q, and it is difficult to reduce the voltage to 60 mV or less at room temperature.

Due to the phenomenon described above, the substantial DC current of a semiconductor integrated circuit composed of a large number of MOS transistors significantly increases. Especially at the time of high temperature operation, V
This problem is exacerbated because _T is low and S is large. In the future era of downsizing of computers and the like where low power consumption is important, this increase in subthreshold current is an essential problem.

This problem will be further described with reference to a memory which is a typical semiconductor integrated circuit. As shown in FIG. 8, the memory has an X decoder (XDEC) and a word driver (W) for selecting and driving a row line (word line W) in order to select an arbitrary memory cell MC in the memory array MA.
D) and a sense amplifier (SA) for amplifying the signal of the column line (data line D), a sense amplifier driving circuit (SAD) for driving the sense amplifier, and a Y decoder (YDEC) for selecting the column line. Further, a peripheral circuit (PR) for controlling these circuits is built in. The main part of these circuits has a circuit configuration based on the CMOS logic circuit described above in order to reduce power consumption during operation, standby, or battery backup. However, the threshold voltage V _{T of the} transistor (hereinafter referred to as P
The absolute value of the MOS transistor and the NMOS transistor are equal, it is assumed that V _T. ) Decreases, the through current increases drastically for the above-mentioned reason. This is particularly noticeable in the decoder and driver or peripheral circuit section. This is because the number of circuits constituting these is overwhelmingly large and has special functions.

For example, in the case of a decoder or a driver, a small number of specific circuits are selected from a large number of circuits of the same type and driven by an address signal. If VT is sufficiently large, many non-selection circuits are completely selected and driven. In general, as the storage capacity of the memory increases, the number of decoders and drivers increases. However, as long as the through current does not flow through the non-selection circuit, the total current does not increase even if the storage capacity increases. However, this is only possible when the VT is large, and when the VT is low as described above, the through current increases sharply. Similarly, when the entire chip is not selected (standby state), conventionally, most of the circuits in the chip were turned off to reduce the power supply current as much as possible, but this is no longer possible. This problem is not limited to memories, but is common to all semiconductor integrated circuits based on CMOS logic circuits. In addition,
As a patent application relating to the conduction current, Japanese Patent Application Laid-Open No. 60-167
No. 523, JP-A-5-108194, JP-A-5-21
0976, JP-A-6-29834, JP-A-5-26
No. 8065, JP-A-5-291929, JP-A-5-3
No. 47550, JP-A-6-53496, JP-A-6-1
20439 and the like.

[0018]

SUMMARY OF THE INVENTION The object of the present invention is to provide an MO
To provide a high-speed and low-power semiconductor device even if the S transistor is miniaturized, and to reduce a through current of a word driver, a decoder, a sense amplifier driving circuit, etc., which is a problem particularly in a memory or a semiconductor device having a built-in memory is there.

[0019]

In order to achieve the above-mentioned object, a plurality of circuits of the same kind are constituted, and only a small number of circuits are selectively operated during operation, and the rest are kept in a non-selected state. In such a semiconductor integrated circuit, the large number of circuits are divided into a plurality of blocks, a power supply line is provided for each block, and this power supply line is connected to another power supply line via a switch, and the switch has a selection function. Give it. The selection function is realized by an address signal, a signal designating an operation mode such as active and standby, a signal designating a specific time zone in the active time zone, or a combination thereof.

[0020]

The through current flowing through the non-selected circuit can be minimized even if the threshold voltage of the transistor is low.

[0021]

FIG. 1 shows an example in which the present invention is applied to a word driver (WD in FIG. 8) of a dynamic random access memory (DRAM). Taking the state after the word line is selected as an example, in the conventional circuit (a), V _T
As long as is high enough, no through current will flow through all CMOS drivers. However, if V _T is low,
Through current flows through the word driver, and this capacity cannot be ignored with the increase in capacity (m · n large).
The total I _A of this through current is

[0022]

(Equation 4)

## EQU2 ## Here, V _T is the threshold voltage defined by the current value I ₀ as shown in FIG. 2, S is a tailing coefficient. Word driver power supply V _CH Since supplied by boosting the external power supply inside the chip, the current driving capability is limited, it can not be processed and I _A increases.

On the other hand, the hierarchical feeder system (b) of the present invention has the following two features. Hierarchical power supply line in which drivers are divided into blocks: m blocks each including n word drivers are provided, and power supply lines P _{1 to} P of each block are provided.
_m is connected to the power supply line P via the block selection transistors Q _{1 to} Q _m . Further, P is connected to a word voltage V _CH via a transistor Q for selecting an operation mode and a standby mode.
To the power supply line. Hierarchical gate width setting: The gate width (a · W) of the block selection transistor is selected to be sufficiently smaller than the total (n · W) of the gate widths of the word driver transistors in the block (a≪n). Further, the gate width (b · W) of Q is selected to be sufficiently smaller than the sum (m · a · W) of the gate widths of all the block transistors (b≪ma).

In operation, Q and Q ₁ are turned on to supply V _CH to the feeder line (P ₁ ) corresponding to the block (B ₁ ) including the selected word driver (# 1). Here, V _T of all transistors, assuming the same low value, this configuration each total through current of the unselected blocks (B ₂ ~B _m) is the corresponding block select transistors (Q ₂ to Q _m ) Equal to one subthreshold current. Because the sub-threshold current is proportional to the gate width of the transistor, even if a current of n · i tries to flow, the overall through current is eventually limited to the sub-threshold current (a · i) of the block selection transistor. That's because. Then, the voltage of the power supply line P ₂ to P _m of the non-selected block is down only remain ΔV nearly standby. This is because the sub-threshold current of Q ₂ to Q _m to charge the P ₂ to P _m is relatively small. Therefore, the total through current I _A is substantially as shown in Table 1 (n + m
A) It becomes i. In order to reduce the I _A is, n and (m
It is better to set a) to a similar value. Here, if a is set to about 4, the influence on the speed of the series transistor (Q, Q ₁ ) and the chip area can be reduced.

During standby, Q and Q _{1 to} Q _m are all turned off. The overall through current I _S is equal to the sub-threshold current of Q, and a / m · n
Can only be smaller. The voltage of the feed line of the block is mn
.DELTA.V determined by the ratio of W to aW and the tailing coefficient
Only drop from V _CH .

[0027]

[Table 1]

FIG. 3 is a schematic diagram of an operation waveform. Standby _{(Φ, Φ 1 ~Φ m:} V CH) , the the Q and Q ₁ to Q _m is turned almost off, P is V _CH lower than the voltage V _CH
−ΔV ′, and P _{1 to} P _m are voltages lower than that. All word lines are fixed at V _SS irrespective of the voltages P _{1 to} P _m . When the external clock signal / RAS (where "/" indicates a bar signal) is turned on, Q is first turned on by Φ, and the parasitic capacitance C of P is changed to t.
Charge for ₁ hour to V _CH . Then, Q ₁ in [Phi ₁ is turned on, to charge the parasitic capacitance C ₁ of the P ₁ t ₂ h V _CH. In this case, Q ₂ ~Q _m remains almost off. Thereafter, the word driver # 1 by X decoder output signal X ₁
Is selected, and the word line is driven. / RAS is turned off, Q and Q ₁ is turned off. When a long time elapses due to the mechanism described above, P and P ₁ are V _CH −Δ
V ′, V _CH −ΔV. Here, without impairing the access time can be charged feed line (P, P ₁₎ to V _CH.
This is because even if C is large, ΔV 'is as small as about several hundred mV, and a sufficient charge time (t ₁ ) of P can be obtained immediately after / RAS is turned on. In addition, since C ₁ is relatively small because of being divided into blocks, the charging time (t ₂ ) of P ₁ can be shortened.

By applying a hierarchical feed line to the decoder, the through current can be greatly reduced.

FIGS. 4 and 5 show the hierarchical feed line system applied to the sense amplifier drive circuit (SAD in FIG.
1 shows a main part of a memory array including a memory cell including one transistor and one capacitor. Well-known V _CC
Since the / 2 precharge method is used, this sense amplifier drive circuit operates around V _CC / 2. Therefore, a feature is that a hierarchical feeder is used for both V _CC and V _SS . Here, the PMOS transistors Q _P and NM
Conductance of the OS transistor Q _N are equal. The CMOS sense amplifier (SA) group in the sub-array is selectively driven by the corresponding sense amplifier drive circuit. At this time, the current I _A ′ flowing through the power supply lines V _CC and V _SS passes through a large number of unselected drive circuits. Dominated by current. For example, the transistor Q _P, V the gate of Q _N each _CC, 0 in FIG.
To the non-selected state, the sense amplifier drive lines CP,
Since CN is V _CC / 2, the subthreshold current is P ′ ₁
To P ″ ₁ . In order to prevent this, it is essential to apply to both sides. If, as mentioned above,
_{If the} hierarchical feed line is applied only to _{CC, a} new sub-threshold current of Q _N will flow from P _CC / 2 to P ″ ₁ , causing a decrease in the level of V _CC / 2. This is because the current driving capability of the V _CC / 2 supply circuit built in the chip is small.

FIG. 9 shows the effect of applying the present invention to a word driver, a decoder, and a sense amplifier driving circuit, assuming that the above-described through current does not flow through the peripheral circuit (PR in FIG. 8). As an example, a 16 gigabit DRAM is taken. The parameter used there was a gate width of 5μ.
m at a current 10nA threshold voltage V _T defined by the voltage flows -0.12V, tailing coefficient S is 97 mV / d
ec. , Junction temperature T is 75 ° C., and effective gate length L _eff is>
0.15 μm, gate oxide thickness T _OX is 4 nm, word voltage V _CH is 1.75 V, power supply voltage V _CC is 1 V, cycle time is 180 ns, refresh cycle number is 128 k,
The chip size is 23 mm × 45 mm, and the total capacity of data lines charged / discharged in one cycle is 17 nF. According to the present invention, the operating current can be reduced from about 1.05 A to 109 mA, which is about one tenth. This is because the through current can be significantly reduced from about 0.97 A in the related art to about 1/30 of 34 mA.

Although the present invention has been described with reference to the embodiment in which the present invention is applied to a word driver and a sense amplifier driving circuit, the present invention is not limited to the above-described embodiments unless departing from the gist of the present invention. Absent. Hereinafter, modified examples of the present invention will be described.

FIG. 10 shows an example of a hierarchical power supply system applied to a decoder. CM of NAND circuit and inverter
This is an example of an AND circuit composed of two stages of OS logic circuits. Even if it is not a circuit that operates around V _CC / 2 like a sense amplifier driving circuit, a hierarchical type circuit is provided on both sides of V _CC and V _SS. A feature is that a feeder line is used. The NAND circuits all output V _CC during standby and a few output 0 V during operation. Through current is determined by the NMOS transistors of the V _SS side, using a hierarchical power supply line V _SS side. Conversely, the inverters all output 0 V during standby and a few output V _CC during operation. Since the through current is determined by the PMOS transistor, a hierarchical power supply line is used on the V _CC side.

The present invention can be applied to any circuit group that outputs the same voltage during standby and operates in a small number during operation. At that time, not all circuits need to have the same transistor size, and may have different configurations.

FIG. 11 shows another embodiment in which the present invention is applied to a word driver.
An example is shown in which a plurality operates simultaneously. This is an example in which the power supply line in the embodiment shown in FIG. A block is composed of 512 word drivers, and 5
12 blocks (B _{1,1 to} B _1,256 , B _{2,1 to} B _2,256 )
It is provided eight sectors of (S ₁ ~S _8). Within each sector, two blocks (eg, B _1,1 and B _2,1 ) share a feeder (eg, P ₁ ). Power supply lines P _{1 to} P ₂₅₆
To ₁ through block select transistors Q _{1 to} Q _256.
By 28 present feed line P _L, is connected to the P _R. Feed lines P _L , P _R
Is common to eight sectors. Furthermore, P _L, the P _R transistor Q _L, via a Q _R, connected to the feed line of the V _CH.
Q the gate width of _one to Q _256, a word driver in two blocks, i.e. Prefer chosen sufficiently smaller than the sum of the gate widths of the transistors 1 km number of word drivers. Also, Q _L, the gate width of the Q _R, feeding line P _L, selected sufficiently smaller than the sum of the gate widths of the P _R, respectively the connected block selection transistor, namely (8 × 128) pieces of the block selection transistors Leave. In operation, the eight sectors perform the same operation. For example, Q _L, Q _R
And Q ₁ in each sector are turned on, and V _{CH is added to} two blocks (B _1,1 and B _2,1 ) including the selected word driver (# 1).
Supply. The through current was 2 in the embodiment shown in FIG.
It is the same as when 56, n is 4 kg. Thus, when a plurality of circuits operate simultaneously, a plurality of blocks may be selected at the same time. Also, by dividing the transistor that operates as a switch into a plurality
The influence of the wiring resistance can be reduced by shortening the power supply line, and the power supply line (P ₁ ) of the selected block can be charged in a short time.

FIG. 12 shows an embodiment in which the present invention is applied to an NMOS driver. A feature is that a hierarchical feed line is used on the drain side of the transistor. Each driver is a push-pull circuit composed of two NMOS transistors. Unselected drivers output 0V and selected drivers output V _CC -V _T. By using a hierarchical feed line on the drain side of the transistor, that is, on the V _CC side, the through current can be reduced as in the embodiment shown in FIG. 1 without changing the output of the unselected driver. For example, when the block select transistors Q ₂ to Q _m is off as shown in FIG. 12, even with a small influence of the drain voltage for sub-threshold current, greatly decreased the voltage of the P ₂ to P _m, the word driver transistor No current flows through Thus, the present invention can be applied to logic circuits other than CMOS.

In the above description, the connection of the substrate of the transistor is not mentioned, but in any of the embodiments,
It is desirable to connect to a power supply. In this case, the charge required for charging the power supply line is smaller and the charging time is shorter than when the substrate is also connected to the power supply line connecting the drain. For example, in the embodiment shown in FIG. 1, by connecting all the substrates of the PMOS transistors to V _CH , as described above, when the power supply line of the unselected block falls from V _CH by ΔV, the substrate bias effect is reduced. Accordingly, the threshold voltage of the PMOS transistor in the unselected block increases. Since the source has a lower voltage than the gate and the threshold voltage is higher, the same current reduction effect can be obtained with a smaller ΔV than when the substrate has the same voltage as the drain.

Although all the transistors have the same threshold voltage, the through current can be further reduced by making the threshold voltage of the transistor used as a switch higher than that of the other transistors. For example, Q in FIG.
And the threshold voltage of Q ₁ to Q _m higher than that of the transistor in the word driver, by selecting large a and b, while preventing the operating speed of deterioration due to the on resistance of the switch, further reducing the through current it can. This is because the sub-threshold current at the off-state has an exponential function, while the on-resistance has only a linear function. Even if the gate capacitance increases with the gate width, FIG.
If the charging times t ₁ and t ₂ can be secured, there is no problem in terms of operating speed. Also, there is no problem in layout area because the number is relatively small. In some cases, using a transistor having a high threshold voltage only for Q is effective in reducing the standby current.

In the timing diagram shown in FIG.
There in the active period in which a 0V is to remain lowered [Phi and [Phi _1, was kept on the Q and Q _1. this is,
/ RAS controls the [Phi by a signal for designating the operation mode of the standby at the time of activity that is generated by, it is achieved by controlling the [Phi ₁ by combining the signal of the signal and the address signal. Furthermore, after the word line is driven, Φ and Φ ₁ are set to V _CH and Q and Q ₁ are used by using a signal designating a period from the fall of / RAS to the end of driving of the word line.
It is also possible to turn off. Thereby a through current after the word line driving, even during active can be reduced to the same extent as standby current I _S. This effect is greater as the active period during which / RAS is 0 V is longer. However, in this case,
In order to rewrite the memory cell, it is necessary to lower Φ and Φ ₁ for a certain period from the rise of / RAS to turn on Q and Q ₁ . For example, in the embodiment applied to the decoder shown in FIG. 10, the through current after the output is determined can be further reduced.

The present invention can be applied not only to DRAMs but also to memories such as static random access memories (SRAMs) and read-only memories (ROMs) and logic LSIs with built-in memories. The present invention has a greater effect as the threshold voltage decreases, and the threshold voltage 0.2 V at which the through current becomes dominant in the operating current.
The effect is remarkable in an LSI of a degree or less. At an operating voltage of about 2 V or less, a threshold voltage of that level is required in terms of operating speed, or at a gate length of about 0.2 μm or less, such a threshold voltage is obtained according to a scaling rule, so that the effect is particularly large.

[0041]

As is clear from the embodiments described above,
According to the present invention, a through current can be reduced without impairing the operation speed, and a semiconductor device which operates at high speed with low power consumption can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment applied to a word driver.

FIG. 2 is a diagram showing operating points of PMOS transistors of a word driver.

FIG. 3 is an operation timing chart of the embodiment shown in FIG. 1;

FIG. 4 is a diagram showing an embodiment applied to a sense amplifier driving circuit.

FIG. 5 is a diagram illustrating a configuration example of a main part of a memory array.

FIG. 6 is a circuit diagram of a conventional CMOS inverter.

FIG. 7 is a diagram showing sub-threshold characteristics of a transistor.

FIG. 8 is a block diagram of a memory.

FIG. 9 is a diagram showing the effect of the present invention.

FIG. 10 is an embodiment applied to a decoder.

FIG. 11 is another embodiment applied to a word driver.

FIG. 12 is a diagram showing an embodiment applied to an NMOS driver.

[Explanation of symbols]

WD: word driver, W: word line, XDEC: X decoder, D: data line, SA: sense amplifier, YDEC
... Y decoder, SAD ... sense amplifier drive circuit, CN,
CP: sense amplifier drive line, MC: memory cell, MA:
Memory array, PR: Peripheral circuit, V _CH : Word voltage, V
_CC ... power supply voltage, V _SS ... ground voltage (0V), m, m ' ... block number, n ... number circuit in the _{block, B 1 ~B m, B'} 1 '
~ B '_m' ... block, P ₁ -P _m , P '_1' -P '_m' , P "
_{1 'to} P "_m' ... power supply lines of blocks, Q _{1 to} Q _m , Q '_1' to
Q '_m' , Q " _{1 '} -Q"_m' ... block selection transistor,
P, P ′, P ″: second power supply line, Q, Q ′, Q ″: transistors for selecting an operation mode and an atmospheric mode.

Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H03K 19/0948 G11C 17/00 633Z H03K 19/094 B (56) References JP-A-6-29834 (JP, A) JP-A-5-298 210976 (JP, A) JP-A-6-232348 (JP, A) JP-A-6-208790 (JP, A) Nikkei Microdevice (1993-3) 48-51 (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 11/4074

Claims (42)

(57) [Claims] A plurality of circuit blocks; a first node and a second node for supplying an operating voltage to the plurality of circuit blocks; and a connection between the first node and each of the plurality of circuit blocks. is equipped with a plurality of first current control means, also between the drain and the source under the conditions each circuit block gate and source voltages of the plurality of circuit blocks is equal to
A MOS transistor through which a threshold current flows, wherein the first current control means controls a current amount of a circuit block corresponding to the first current control means, and one circuit block included in the plurality of circuit blocks And another circuit block are connected to the sub-threshold by the first current control means corresponding to the one circuit block.
Wherein the other circuit block is controlled by the corresponding first current control means to allow the subthreshold current to flow when the threshold current is controlled to be limited. Integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein each of said plurality of circuit blocks is constituted by a CMOS logic circuit including an NMOS transistor and a PMOS transistor. 3. The semiconductor integrated circuit according to claim 1, wherein at least one of said first current control means is selected so that a first operating voltage is applied through said first current control means. Supplied to the block, the plurality of circuits
Each of the blocks is electrically connected to the second node.
And a second operating voltage is applied to each of the plurality of circuit blocks.
Supplied by the first current control means to which the one circuit block corresponds.
So that the stage limits its subthreshold current
Is controlled, the first conductive upper Symbol of the other circuit blocks are the corresponding
The subthreshold current flows by the current control means
During the period that is controlled to allow
The node that provides an input signal to one circuit block is
One of the first operating voltage and the second operating voltage is
Is selected and provides an input signal to the other circuit blocks.
The different nodes are the first operating voltage and the second operating voltage.
A semi-conductor characterized in that the pressure changes from one to the other
Body integrated circuit. 4. The semiconductor integrated circuit according to claim 3, further comprising : a third node; and second current control means provided between said first node and said third node. Supplying the first operating voltage to the first node through the second current control means and selecting at least one of the first current control means so that the first operating voltage is reduced to the first current. A semiconductor integrated circuit supplied to a corresponding circuit block through a control means. 5. The semiconductor integrated circuit according to claim 1, wherein said plurality of circuit blocks include a plurality of MOS transistors having the same connection relation to each other. circuit. 6. The semiconductor integrated circuit according to claim 1, wherein the circuit block selection signal for controlling said first current control means is generated according to at least a part of an address signal. A semiconductor integrated circuit characterized by the above-mentioned. 7. A plurality of first circuit blocks, a plurality of first switching elements, a first operating potential supply line commonly connected to the plurality of first switching elements, and the first operation A second switching element connected between a potential supply line and a first operating potential point; and each of the plurality of first nodes of the plurality of first circuit blocks is connected to the plurality of first switching elements. And a plurality of second nodes of the plurality of first circuit blocks are connected to a second operating potential supply line, and the plurality of Each circuit block of one circuit block has a source connected to the corresponding first node, a MOS transistor having a gate connected to the input terminal, and one end connected to a drain of the MOS transistor, And a end is connected to a corresponding said second node load, of each circuit block of the plurality of first circuit block MO
When the gate-source voltage is substantially zero, the S transistor causes a subthreshold current to flow through the source-drain path, and the leakage current when each of the plurality of first switching elements is turned off is reduced by the plurality of first circuits. The element constants of the plurality of first switching elements are set so as to be smaller than the sub-threshold current of the MOS transistor of the corresponding circuit block of the block. By turning off the plurality of first switching elements, the plurality of first switching elements are turned off. The current consumption of each circuit block of the first circuit block is limited to the value of the leakage current of the switching element corresponding to the plurality of first switching elements. So as to be smaller than the sum of the leak currents of the first switching element. A semiconductor element for setting a constant of an element of the second switching element, and as a result, limiting a total sum of current consumption of the plurality of first circuit blocks to a value of the leak current of the second switching element. Integrated circuit. 8. The semiconductor integrated circuit according to claim 7, wherein the MO of each of said plurality of first circuit blocks is
A semiconductor integrated circuit, wherein the S transistor is a p-channel MOS transistor, and a load of each of the plurality of first circuit blocks is an n-channel MOS transistor. 9. The semiconductor integrated circuit according to claim 7, wherein each of said plurality of first switching elements comprises a MOS transistor, and said second switching element comprises a MOS transistor. A semiconductor integrated circuit, wherein the absolute value of the constant current threshold voltage is larger than the absolute value of the constant current threshold voltage of the MOS transistor of each of the plurality of first switching elements. 10. The semiconductor integrated circuit according to claim 7, wherein each of said plurality of first switching elements comprises a MOS transistor, and a source-drain path thereof corresponds to said corresponding first switching element. A semiconductor integrated circuit, wherein a current path is formed between one node and the first operating potential point. 11. The semiconductor integrated circuit according to claim 7, further comprising: a memory array including a large number of memory cells, wherein said plurality of first circuit blocks include a plurality of said memory cells. A semiconductor integrated circuit, which is a word driver for driving a word line for selecting a desired memory cell. 12. The semiconductor integrated circuit according to claim 7, further comprising a memory cell array including a large number of memory cells, wherein said plurality of first circuit blocks include said large number of memory cells. A semiconductor integrated circuit, which is a decoder for decoding an address signal for selecting a desired memory cell. 13. When the voltage from the first voltage to the second voltage is applied to the gate, and when the second voltage is applied to the gate rather than when the first voltage is applied. In a semiconductor integrated circuit having a plurality of MOS transistors in which a drain current increases and a leakage current flows between the drain and the source when the gate voltage is the first voltage, the first operating voltage is applied. A first node, a second node to which a second operating voltage is applied, a third node having each circuit block thereof, a fourth node connected to the second node, A plurality of circuit blocks each having at least one MOS transistor having a source / drain path connected between the third node and the fourth node; A plurality of current limiting means having at least one MOS transistor having a source / drain path connected between a first node and the third node of a corresponding circuit block; and a plurality of current limiting means. And a control circuit for controlling each of the MOS transistors to the first state or the second state, wherein the gate width of the MOS transistor in the current limiting means is connected to the third node in the corresponding circuit block. Smaller than the sum of the gate widths of at least one or more MOS transistors, wherein each of the plurality of current limiting means limits the current flowing through the corresponding circuit block to a first absolute value when in the first state Each of the plurality of current control means, when in the second state, passes through a corresponding circuit block an absolute value larger than the first absolute value. The control circuit is capable of controlling at least one of the plurality of current limiting means to be in the first state and at least one of the other current limiting means to be in the second state. A semiconductor integrated circuit characterized by the above. 14. The semiconductor integrated circuit according to claim 13 , wherein a fifth node and at least one source / drain path connected between said first node and said fifth node are provided. M above
A common current limiting means having an OS transistor, wherein the gate width of the MOS transistor in the common current limiting means is equal to the gate width of the MOS transistor included in the plurality of current limiting means connected to the common current limiting means. A semiconductor integrated circuit characterized by being smaller than the sum of The semiconductor integrated circuit according to any one of 15. The method of claim 13 or 14, that are fixed to the substrate is a voltage of the MOS transistor leakage current included in each of said plurality of circuit blocks flows A semiconductor integrated circuit characterized by the above-mentioned. The semiconductor integrated circuit according to any one of claims 16] claims 13 to 15, the threshold voltage of the MOS transistor leakage current included in each of said plurality of circuit blocks flows, 0.
2V or less, and the above threshold voltage is such that the ratio of gate width to effective gate length is 5
And a constant current threshold voltage defined by a gate-source voltage at which a drain current of 10 nA flows when /0.15. The semiconductor integrated circuit according to any one of claims 17] claims 13 to 16, a gate oxide film thickness of the MOS transistor leakage current included in each of said plurality of circuit blocks flows, 4
a semiconductor integrated circuit having a diameter of not more than nm. The semiconductor integrated circuit according to any one of claims 18] claims 13 to 17, the gate length of the MOS transistor leakage current included in each of said plurality of circuit blocks flows, 0.2.mu.
m or less. The semiconductor integrated circuit according to any one of 19. The method of claim 13 or 18, when one of the plurality of current limiting means is in the first state described above, the above circuit block corresponding to said current limiting means The voltage of the third node is between the first operating voltage and the second operating voltage. The semiconductor integrated circuit according to any one of 20. The method of claim 13 or 19, when one of the plurality of current limiting means is said second state, said circuit block corresponding to said current limiting means A semiconductor integrated circuit, wherein a voltage of the third node is substantially the same as the first operating voltage. The semiconductor integrated circuit according to any one of claims 21] claims 13 to 20, a semiconductor integrated circuit, characterized by further comprising voltage generating means for generating the operating voltage. 22. The semiconductor integrated circuit according to claim 21 , wherein said voltage generating means is a booster circuit for boosting an externally applied voltage. 23. A semiconductor integrated circuit according to any one of claims 13 to 22, a semiconductor integrated circuit, wherein the absolute value of the operating voltage is 2 volts or less. The semiconductor integrated circuit according to any one of claims 24] claims 13 to 23, a semiconductor integrated circuit, wherein the absolute value of the power supply voltage applied from the outside is 2 volts or less. The semiconductor integrated circuit according to any one of claims 25] claims 13 to 24, the circuit block having at least one output node, voltage output to said output node, said current limiting means is the In the second state, the voltage is substantially the same as the voltage of the third node. 26. When a voltage from a first voltage to a second voltage is applied to the gate and the second voltage is applied to the gate more than when the first voltage is applied to the gate. In a semiconductor integrated circuit including a plurality of MOS transistors in which a drain current increases and a leakage current flows between the drain and the source when the gate voltage is the first voltage, a plurality of row lines; A plurality of column lines intersecting a row line; a plurality of memory cells arranged at intersections of the plurality of row lines and the plurality of column lines; a first node to which a first operating voltage is applied; A second node to which a second operating voltage is applied; a third node each; a fourth node connected to the second node; and a source / drain path connected to the third node. And the above fourth node A plurality of first circuit blocks each having at least one MOS transistor connected between the first node and the third node of the first circuit block corresponding to the first node. Provided a plurality of first
And a control circuit for controlling each of the plurality of first current limiting units to a first state or a second state, wherein the plurality of first circuit blocks include the row lines. A row selection and drive circuit group for selecting and driving at least one of the first current limiting means, and each of the plurality of first current limiting means flows through the corresponding first circuit block when in the first state. Limiting the current to a first absolute value, wherein each of the plurality of first current limiting means is greater than the first absolute value through the corresponding first circuit block when in the second state; The control circuit allows at least one of the plurality of first current limiting means to be in the first state, and at least one of the plurality of first current limiting means to be in the second state. Characterized by controllability Semiconductor integrated circuit. 27. The semiconductor integrated circuit according to claim 26 , further comprising: a fifth node; and common current limiting means provided between said first node and said fifth node. A semiconductor integrated circuit characterized by the above-mentioned. 28. A semiconductor integrated circuit according to claim 26 or 27, the semiconductor integrated circuit of the plurality of first current limiting means, characterized in that it is selected by the row address. 29. The semiconductor integrated circuit according to any one of claims 26 to 28, each of the plurality of first current limiting means, said first circuit block corresponding to said first node a 3. A semiconductor integrated circuit device having at least one MOS transistor whose source / drain path is connected to a third node. 30. The semiconductor integrated circuit according to any one of claims 26 to 29, each of the plurality of memory cells, a semiconductor integrated characterized in that it is composed of one transistor and one capacitor circuit. 31. A semiconductor integrated circuit according to any one of claims 26 to 30, the substrate of the MOS transistor leakage current included in each of the plurality of first circuit block flows is fixed at a certain voltage A semiconductor integrated circuit characterized in that: The semiconductor integrated circuit according to any one of claims 32] claims 26 to 31, the threshold voltage of the MOS transistor leakage current included in each of the plurality of first circuit block flows is 0. 2V or less, and the above threshold voltage is such that the ratio of gate width to effective gate length is 5
And a constant current threshold voltage defined by a gate-source voltage at which a drain current of 10 nA flows when /0.15. 33. A semiconductor integrated circuit according to any one of claims 26 to 32, a gate oxide film thickness of the MOS transistor leakage current included in each of the plurality of first circuit block flows is a 4nm A semiconductor integrated circuit, comprising: 34. A semiconductor integrated circuit according to any one of claims 26 to 33, the gate length of the MOS transistor leakage current included in each of the plurality of first circuit block flows,
A semiconductor integrated circuit having a thickness of 0.2 μm or less. 35. The semiconductor integrated circuit according to any one of claims 26 to 34, a semiconductor integrated circuit, characterized by further comprising voltage generating means for generating the operating voltage. 36. The semiconductor integrated circuit according to claim 35 , wherein said voltage generating means is a boosting circuit for boosting an externally applied voltage. 37. The semiconductor integrated circuit according to any one of claims 26 to 36, a semiconductor integrated circuit, wherein the absolute value of the power supply voltage applied from the outside is 2 volts or less. The semiconductor integrated circuit according to any one of claims 38] claims 26 to 37, each of the plurality of first circuit block has at least one output node, the voltage output to the output node Wherein the voltage of the third node is substantially the same as the voltage of the third node when the first current control means is in the second state. 39. A plurality of circuit blocks, a first node and a second node for supplying an operating voltage to the plurality of circuit blocks, and a current control means for controlling a sub-threshold current flowing through the plurality of circuit blocks. Wherein each of the plurality of circuit blocks includes a first MOS transistor in which a subthreshold current flows between a drain and a source even under a condition that a gate voltage and a source voltage are equal, and one circuit included in the plurality of circuit blocks The block and another circuit block may be configured such that when the one circuit block is controlled by the current control means so as to limit the sub-threshold current, the other circuit block has the sub-threshold current flowing therethrough. A semiconductor integrated circuit, which is controlled to be allowed. 40. The semiconductor integrated circuit according to claim 39, wherein when said other circuit block is controlled by said current control means to limit its sub-threshold current, said one circuit block is connected to its sub-threshold. A semiconductor integrated circuit controlled to allow a threshold current to flow. 41. The semiconductor integrated circuit according to claim 39, wherein said current control means includes a plurality of second MOS transistors provided corresponding to each of said plurality of circuit blocks. When the second MOS transistor is on, the corresponding circuit block is allowed to flow its subthreshold current. When the second MOS transistor is off, the corresponding circuit block has its subthreshold current flowing. A semiconductor integrated circuit characterized by being limited. 42. The semiconductor integrated circuit according to claim 39, wherein said current control means controls said one circuit block to limit its sub-threshold current,
During a period in which the other circuit block is controlled to allow the subthreshold current to flow, one of the first level and the second level is selected as the input signal of the one circuit block. A semiconductor integrated circuit, wherein the input signal of the other circuit block changes from the one of the first level and the second level to the other.