JPH04302897A - Dynamic semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a DRAM which has compatible characteristics of a high speed operation and a low power consumption. CONSTITUTION:A memory cell array 2 on which dynamic type memory cells are placed, core circuits 3 and 4 which include address decoders and sense amplifiers, a peripheral circuit 5 which performs data input and output control and a bias circuit 6, which generates bias potentials for each circuit section, are provided. The bias circuit 6 has at least the capability in which different base plate biases are supplied to MOS transistors used in the peripheral circuit 5 during an active period and a precharge period.

Description

[Detailed description of the invention]

[Purpose of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvements in dynamic semiconductor memory devices (DRAMs).

0002

BACKGROUND OF THE INVENTION Among semiconductor memory devices, DRAMs, which have the most increased capacity, are currently in the product development stage of 16 Mbit DRAM, and in the research and development stage of 64 Mbit DRAM. As DRAMs increase in capacity, higher speeds and lower power consumption are becoming increasingly important issues.

In a 16 Mbit DRAM, in order to achieve high-speed operation during active operation, the peripheral circuit section that requires particularly high-speed operation is not subjected to substrate bias during both active and standby periods. A substrate bias is applied to the memory cell array section both during active and standby periods in order to reduce bit line capacitance and prevent leakage between cells.

On the other hand, when looking at the current consumption during standby, in a 16 Mbit DRAM, most of it flows in the bias circuit section for generating the substrate potential and plate potential.
There is almost no contribution from the subthreshold current of transistors in the peripheral circuit section. Therefore 16 Mbit D
In a RAM, if sufficient attention is paid to the circuit design of the bias circuit section, it is possible to achieve both high-speed performance and low power consumption characteristics during standby.

[0005] As the capacity of DRAM continues to increase, for example, 1
When the G bit level is reached, the external power supply potential is expected to be lowered to 1.5V. In order to lower the external power supply potential to this extent and ensure high-speed performance, the MOS of each part must be
It is also necessary to lower the threshold voltage of the transistor to, for example, about 0.2V. However, when the threshold voltage is lowered in this way, the subthreshold current component of the MOS transistor becomes too large to be ignored.

This is because the S factor, which indicates the subthreshold characteristics of a MOS transistor, depends on the gate insulating film thickness T.
ox, which is determined only by the substrate impurity concentration NA,
The gate insulating film thickness is TDDB (Time Dependency
dent Dielectric Breakd
This is because it cannot be made too thin from the viewpoint of longevity.

[0007] Therefore, when the capacity is increased to 1 Gbit level, the subthreshold current that occupies the standby current becomes extremely large. This situation is shown in FIG. As shown in the figure, for 16M bits, the standby current was dominated by the current in the bias circuit, whereas
When it comes to G bits, subthreshold current becomes dominant.

In order to reduce the subthreshold current component, the threshold voltage of the MOS transistor can be increased by increasing the substrate impurity concentration NA, or by increasing the threshold voltage of the MOS transistor by applying a substrate bias. good. However, increasing the threshold voltage of the MOS transistor impairs high-speed performance.

[0009] Furthermore, DRAMs are expected to be increasingly used for low standby currents that can be backed up by batteries, and in this sense, it is desired to reduce subthreshold currents.

0010

[Problems to be Solved by the Invention] As described above, the conventional DRAM system has the problem that it becomes difficult to achieve both high-speed performance and low power consumption characteristics during standby when the capacity is further increased. .

In view of the above, an object of the present invention is to provide a DRAM that can achieve both high-speed performance and low power consumption characteristics even when the capacity is increased.

[Configuration of the invention]

[0013]

[Means for solving the problems] DRAM according to the present invention
The system includes a memory cell array in which dynamic memory cells are arranged, a core circuit including an address decoder and a sense amplifier, peripheral circuits that control data input/output, and a bias circuit that generates bias potentials for each circuit section. The circuit is at least an MO used for peripheral circuits.
It is characterized by having a function of applying different substrate biases to the S transistor when active and when precharging.

[0014]

[Operation] According to the present invention, the M
By varying the substrate bias of the OS transistor, the absolute value of the threshold voltage can be made larger during standby compared to when active. This ensures high-speed operation with a low threshold voltage when active, and reduces subthreshold current during standby to achieve low power consumption characteristics.

[0015]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a DRAM according to an embodiment of the present invention.
The chip configuration is shown below. As shown in the figure, the DRAM chip 1 includes a memory cell array 2, core circuit sections 3 and 4, a peripheral circuit section 5, a bias circuit section 6, and the like.

The memory cell array 2 has one transistor/
Dynamic memory cells each having one capacitor are arranged in a matrix. The core circuit units 3 and 4 include a sense amplifier, a row decoder, a column decoder, and the like. The peripheral circuit section 5 includes various circuits that control data input and output, such as an address buffer, an input/output buffer, and a clock generation circuit. The bias circuit section 6 is a section that generates substrate bias, plate potential, etc. of the MOS transistors forming each circuit.

The bias circuit 6 has a function of applying different substrate biases to at least the MOS transistors of the peripheral circuit section 5 during active and standby states.

FIG. 2 shows a cross-sectional structure of the main part of the DRAM of this embodiment. In this embodiment, an n-type semiconductor substrate 11 is used.

[0020] The core circuit parts 3 and 4 are CMOS configured using a p-type well 121 formed in the substrate 11 and an n-type well 131 formed in the p-type well 122.
It is a circuit. In the figure, one NM is placed in the p-type well 121.
An OS transistor Qn1 is shown, and one PMOS transistor Qp1 is shown in the n-type well 131.

Similarly, the peripheral circuit section 5 also has a p-type well 123.
and the n-type well 1 formed in the p-type well 124.
This is a CMOS circuit constructed using .32. In the figure, one NMOS transistor Q is placed in the p-type well 123.
n2, and one PMOS transistor Qp2 is shown in the n-type well 132.

The memory cell array 2 has a p-type well 125
is formed. Here again, N is applied to the p-type well 125.
One memory cell consisting of a MOS transistor QM and a capacitor CM is shown.

FIG. 3 shows the well potential applied from the bias circuit 6 to each circuit portion of such a well structure. Note that the external power supply potential is 1.5V.

In the core circuit sections 3 and 4, -0.1V is applied to the p-type well 121 throughout the active and standby periods.
, a boosted voltage of 2V is applied to the n-type well 131. Therefore, in the core circuit sections 3 and 4, both the NMOS transistor Qn1 and the PMOS transistor Qp1 always have a constant threshold voltage. The p-type well 122 is always at -0.5V.

Different well potentials are applied to the peripheral circuit section 5 during active and standby states. When active, 0V to p-type well 123, n-type well 132
1.5V, which is the same as the power supply potential, is applied to . At this time, N
MOS transistor Qn2, PMOS transistor Qo
No substrate bias is applied to both. During standby,
-0.5V to p-type well 123, n-type well 132
A boosted potential of 2.0V is applied to. This allows N.M.O.
A substrate bias of 0.5 V is applied to both the S transistor Qn2 and the PMOS transistor Qp2 in the direction in which the absolute value of the threshold value increases. Note that the p-type well 124 is always at -0.5V.

P-type well 125 in memory cell array section 2
is -0.5 throughout active and standby
V constant bias is applied.

FIG. 4 shows the characteristics of the MOS transistor in the peripheral circuit section 5 when it is active (a) and when it is in standby (b).
). Gate-source voltage VGS
, drain current IDS and threshold voltage Vth0,
Since Vth1 is shown for both PMOS and NMOS, it is expressed as an absolute value. These are positive for NMOS transistors and negative for PMOS. By controlling the well potential as described above, the threshold voltage Vth during active
0, the threshold voltage Vth1 during standby is higher. As a result, the subthreshold current in the peripheral circuit section 5 during standby decreases more greatly as the order changes.

FIG. 5 shows the standby current of the DRAM of this embodiment, corresponding to FIG. 7 of the prior art. By reducing subthreshold current, 1Gbit D
Even with RAM, the current consumption during standby is 16M
It is possible to suppress the current value to approximately the same value (approximately 1 mA) as that of a bit DRAM.

In this manner, according to this embodiment, by controlling the well potential of the peripheral circuit section, the subthreshold current during standby is reduced while maintaining high-speed performance during active, resulting in low power consumption characteristics. can be realized.

In the above embodiment, the threshold values of the MOS transistors in the memory cell array section and the core circuit section are kept constant throughout the active and standby periods. This is because the subthreshold current of the MOS transistor mainly flows in the peripheral circuit section. However, 4G,
As the capacity of DRAM increases further to 16G, the increase in subthreshold current in the core circuit section cannot be ignored. In that case, it is preferable to perform well potential control on the core circuit section as well as on the peripheral circuit section.

FIG. 6 shows the well potentials of various parts in such an embodiment, corresponding to FIG. Well potential control of the peripheral circuit section 5 is the same as in FIG. The p-type well 121 of the core circuit sections 3 and 4 is not kept at a constant voltage of -0.5V, but is lowered to -0.8V during standby. Furthermore, the n-type wells 131 of the core circuit sections 3 and 4 are not kept at a constant 2.0V, but are increased to 2.3V during standby.

[0032] As a result, even in the core circuit parts 3 and 4, the MO
The threshold of the S transistor is controlled to reduce the subthreshold current during standby.

[0033]

As described above, according to the present invention, by controlling the substrate bias of MOS transistors in the peripheral circuit section, it is possible to obtain a large-capacity DRAM that achieves both high-speed operation during active operation and low power consumption during standby. be able to.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a chip configuration of a DRAM according to an embodiment of the present invention.

FIG. 2 is a diagram showing a cross-sectional structure of a main part of the DRAM of the same embodiment.

FIG. 3 is a diagram showing changes in well potential at various parts of the DRAM of the same example.

FIG. 4 is a diagram showing MOS transistor characteristics of the peripheral circuit section of the same embodiment.

FIG. 5 is a diagram showing the relationship between standby current and degree of integration of the DRAM of the same embodiment.

FIG. 6 is a diagram showing changes in well potential at various parts of a DRAM according to another embodiment.

FIG. 7 is a diagram showing the relationship between standby current and degree of integration of a conventional DRAM.

[Explanation of symbols]

1...DRAM chip, 2...Memory cell array, 3, 4...core circuit section, 5...peripheral circuit section, 6...bias circuit section, 11...n-type semiconductor substrate, 121-125...p-type well, 131, 132...n-type well.

Claims (1)

[Claims] 1. A memory cell array in which dynamic memory cells are arranged, a core circuit including an address decoder and a sense amplifier, a peripheral circuit for controlling data input/output, and a bias potential for each circuit section, and at least A dynamic semiconductor memory device comprising: a bias circuit that applies different substrate biases to a MOS transistor used in the peripheral circuit during active and precharge times.