JPH07254685A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To realize both high performance and low power consumption at the time of stand-by by setting the substrate/well potential of an MIS transistor at different levels at the time of stand-by and active. CONSTITUTION:When a reference potential generating circuit 2 in a semiconductor memory is in stand-by state, Vbbs is applied as the substrate/well potential of an Nch transistor 7 to be cut off at the time of active whereas Vbbd, deeper than Vbbs, is applied at the time of stand-by. Vbbs is applied as the substrate/ well potential of an Nch transistor 9, being turned ON under the stand-by state, at the time of active and stand-by. Consequently, the threshold voltage Vth of the transistor 7 at the time of stand-by is set higher than the threshold voltage Vt1 at the time of active. This constitution enhances high speed operation at the time of active and suppresses the threshold leak current of the transistor 7 effectively at the time of stand-by.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which realizes high speed and low power consumption at the same time.

[0002]

2. Description of the Related Art The functions required of an information processing apparatus are becoming more sophisticated year by year, and accordingly, the semiconductor memory device is also required to have a higher function than ever before. In order to meet such demands, semiconductor memory devices have been increased in speed and capacity. In particular, DRAM, which can be most highly integrated among memory devices, has steadily increased its capacity at a rate of 4 times in 3 years, and 16 Mbits are currently mass-produced. One of the factors that made it possible to continuously increase the capacity as represented by DRAM is the miniaturization of the process,
It is considered that the next-generation gigabit large-capacity DRAM will use transistors whose gate length is reduced to 0.1 to 0.15 μm.

At present, regarding transistors having a gate length of 0.1 to 0.15 μm, Nch / Pch transistors which realize either high-speed performance or low leakage current are actively announced at academic conferences. FIG. 14A is a conceptual diagram of peripheral circuits of these conventional semiconductor memory devices. Here, four transistors 101 are used as a typical example of the peripheral circuit.
2 shows a two-stage inverter consisting of Also,
As shown in FIG. 14B, each inverter has a constant internal power supply voltage Int. It is connected to Vcc and the common potential Vss, and each transistor has a constant substrate / well potential Vsub.
Is given. The functions of the above-mentioned conventionally announced transistor can be effectively used if the application is limited. For example, a transistor that emphasizes high-speed performance may be sufficiently applicable as long as it is a high-speed SRAM or logic IC that does not require a low leak current.

However, in recent DRAMs, it is necessary to further speed up not only random access time but also serial access time as in the case of synchronous DRAM or RAMBUS DRAM, and it is low for applications such as portable equipment and hard disk replacement. Standby current is also needed. In other words, there is a problem in that the transistor which has achieved only high speed performance or low leakage current, which has been announced at present, cannot meet the specifications required for a gigabit DRAM.

Here, the above 0.1 to 0.15 μ
A leak current that becomes a problem in a transistor having a fine m will be described. The main problematic leakage current is shown in Fig. 1.
As shown by taking the two-stage inverter circuit of No. 5 as an example, (i)
There are three possible subthreshold leak currents I _SL , (ii) gate leak current I _G , and (iii) band-to-band tunnel leak current I _BBTIDC . The band-to-band tunnel leak current I _BBTIDC flows through the transistor in which the subthreshold leak current I _SL is generated. The gate leakage current I _G is generated in almost all transistors.

Since these leak currents are very small compared to the drain currents of the transistors in the ON state, in principle, in a large capacity DRAM in which there is no floating except for the memory cell portion, this leak current leads to malfunction. There is no. However, there is a problem that these leak currents contribute to an increase in the standby current of the DRAM.

FIG. 16 shows a trend of the total channel width W contributing to the standby current of the subthreshold leakage current I _SL of the transistor in the large capacity DRAM. 1G / 4Gbit DRAM has a total channel width of 1
It exceeds 0m. For both Nch and Pch, S = 100 mV /
Assuming a decade one, 1G / 4G bit D
In order to keep the sum of the subthreshold leakage currents of the RAM transistors at 1 μA, from equation (1), | V _t |
Must be set to ≧ 0.6V.

│V _t │ ≧ 100 mV / decade × log (1
0 × 10 ⁶ μ / 10 μ) = 0.6 V (1) However, since it is assumed that the power supply voltage V _DD can be reduced to about 1.5 V at the 4 G level, V
_{When t} is increased to 0.6 V to suppress the total sum of subthreshold leakage currents, on the other hand, the drain current flowing through the transistor during active (active) decreases, making it difficult to achieve high-speed performance. There is.

Further, in order to realize high-speed performance of the transistor, the gate insulating film needs to be thinned to about 3 nm at the 4G level. As a result, at the 4 G level, the electric field applied to the gate insulating film is close to 5 MV / cm, and the band-to-band tunnel leak current cannot be ignored. Band-to-band tunnel leakage current occurs in transistors where subthreshold leakage occurs.
At the G level, the total channel width where leakage occurs exceeds 10 m. Therefore, the contribution of the band-to-band tunnel leak current to the leak current during standby is also a problem.

Further, when the electric field is 4 to 5 MV / cm, not only the band-to-band tunnel leak current of the transistor but also the gate current becomes a problem. Since the gate leak current flows in almost all transistors in the chip,
The total W of the transistors through which the gate leakage current flows is
The entire chip is close to 100m. As a result, even if the gate leak current can be reduced to about 10 fA / μm ² , there is a problem that the gate leak current reaches the level of μA.

As described above, in the conventional gigabit level DRAM, the subthreshold leakage of the transistor, the gate leakage, and the band-to-band tunnel leakage current contribute greatly to the standby current, so that the high speed performance is improved. However, there is a problem in that the low leakage current characteristics during standby cannot be achieved at the same time.

[0012]

As described above, according to the conventional technique, it is impossible to achieve both high speed performance and low power consumption during standby (particularly reduction of transistor leakage current) in a gigabit level DRAM. It was

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a semiconductor memory device that simultaneously realizes high-speed performance and low power consumption during standby.

[0014]

In a semiconductor memory device according to the present invention (claim 1), a plurality of memory cells for storing data given from the outside and a MIS transistor are used, and the memory cell is On the other hand, a circuit for reading and writing the data and a substrate potential applied to the MIS transistor which is in a cutoff state in the standby state are controlled to control the threshold voltage of the MIS transistor in the standby state. Substrate potential control means for controlling the absolute value to be larger than the absolute value of the threshold voltage in the active state.

In the semiconductor memory device according to the present invention (claim 2), a plurality of memory cells for storing externally applied data and MIS transistors are used, and the data is stored in the memory cells. Circuit for reading and writing the MIS, and the MIS when in the active state
The internal power supply voltage applied directly to the current path of the transistor
And an internal power supply voltage control means for making the voltage higher than the internal power supply voltage applied in the standby state.

[0016]

According to the present invention (claim 1), the substrate / well potential of the MIS transistor can be set to different values during standby and during activation by the substrate potential control means. As a result, the absolute value of the threshold voltage of the MIS transistor that cuts off in the standby mode, that is, the transistor in which the subthreshold leakage occurs is made sufficiently high only in the standby mode. Since the absolute value of the threshold voltage can be set low, high-speed performance of circuit operation can be improved.

Therefore, even a large-capacity semiconductor memory device can simultaneously realize high-speed performance and low power consumption during standby.

Further, in the present invention (claim 2), the internal power supply voltage control means can set the internal power supply voltage to a different value in the standby state and the active state. As a result, by setting the internal power supply voltage to a sufficiently low value during standby, the electric field applied to the gate insulating film can be relaxed, and gate leakage current and band-to-band tunnel leakage current can be significantly reduced. The voltage can be increased to speed up the circuit.

Therefore, even a large-capacity semiconductor memory device can simultaneously realize high-speed performance and low power consumption during standby.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the essential parts of an embodiment of the present invention. The embodiment shown in FIG. 1 is a DRAM of 4 Gbit or more.
Suitable for a large-capacity semiconductor memory device such as a peripheral circuit or a core circuit (two-stage inverter circuit), a substrate / well potential generating circuit (referred to as a substrate potential generating circuit) 2,
And an internal power supply voltage control circuit (hereinafter referred to as Vcc converter) 4. In the present embodiment, as an example of peripheral circuits, a first PchMIS transistor 6, a first NchMIS transistor 7, and a second PchMIS are provided.
The description will be given using a two-stage inverter circuit including the transistor 8 and the second Nch MIS transistor 9, but it is of course applicable to any other circuit. The substrate potential generating circuit 2, which is the first feature of the present invention, comprises a Pch transistor substrate potential generating circuit and an Nch transistor substrate potential generating circuit. Since the same operation is performed at the substrate / well potential of the Pch transistor and the substrate / well potential of the Nch transistor, in this embodiment, Nch is used.
Only the substrate / well potential of the transistor will be described.

As shown in FIG. 2, the substrate potential generating circuit 2 is an Nch that is in a cut-off state when in a standby state.
As the substrate / well potential of the transistor 7, Vbbs when active and Vbbd deeper than Vbbs during standby
In addition, Vbbs is applied as the substrate / well potential of the Nch transistor 9 which is turned on in the standby state in both the active state and the standby state.

As a result, as shown in FIG. 2, the threshold voltage Vth of the transistor 7 in the standby state is set to a value larger than Vtl which is the threshold voltage of the active state. On the other hand, the threshold voltage of the transistor 9 is always Vtl.

The same control is also applied to the Pch transistors 6 and 8. However, the sign of the voltage is the above Nc
It goes without saying that the reverse is true for the h transistors 7 and 9.

By the control by the substrate potential generation circuit 2 described above, it is possible to secure a high-speed operation at the time of active and to effectively reduce the subthreshold leak current at the time of standby of the transistor 7.

The Vcc converter 4, which is the second feature of the present invention, uses the external power supply voltage Ext. Vcc is the internal power supply voltage In
t. In addition to being a circuit for converting to Vcc, it gives a high internal power supply voltage Vcch + Δ when active as shown in FIG.
During standby, a low internal power supply voltage Vcch-Δ 'is applied.

As a result, it is possible to effectively reduce the gate leak current and the band-to-band tunnel leak current when the transistor 7 is in the standby state while ensuring a high-speed operation at the active time.

FIG. 3 shows the relationship between the internal power supply voltage and the propagation delay time in the standby state and the active state of the inverter circuit of this embodiment, and also shows the characteristics of the conventional inverter circuit for comparison. There is.

Here, the substrate potential generating circuit 2 is an Nch in which a subthreshold leak flows in the standby mode in order to prevent a subthreshold leakage current in the standby mode.
The substrate potential Vsub of the transistor 7 is set to V when active.
The threshold voltage is raised from 0.29V when active to 0.6V by deepening bbs from -0.1V to -1.5V. Similarly, the substrate potential of the Pch transistor 8 in which subthreshold leakage flows at the time of standby is set to 0.1V.
To 1.5 V, the threshold voltage is lowered from -0.29 V when active to -0.6 V (the absolute value is increased).

On the other hand, the Vcc converter 4 reduces the gate leak current and the band-to-band tunnel leak during standby, so that the Int. Vcc
1.0V (V which is lower than 1.25V (value determined by gate leakage current and band-band tunnel current) of the conventional technique
(value close to ccMIN) to achieve high-speed performance when active, Int. Vcc is raised to 1.5V determined by the hot electron effect.

By such control, a higher-speed operation is realized as shown in FIG. 3, and the leakage current during standby is greatly reduced as described above.

That is, by the substrate potential control means 2,
MI that cuts off only during standby or during standby
Since the absolute values of the threshold voltages of the S transistors 7 and 8 (transistors in which subthreshold leakage occurs) are set sufficiently high by O, the subthreshold leakage current can be significantly reduced and the absolute threshold voltage can be reduced when active. Since the value can be set low, high-speed performance of circuit operation can be improved.

Further, by the internal power supply voltage control means 4,
During standby, the internal power supply voltage Int. By setting Vcc sufficiently low, the electric field applied to the gate insulating film can be relaxed, and the gate leak current and band-to-band tunnel leak current can be greatly reduced. It can speed up.

As described above, according to this embodiment, it is possible to realize high-speed performance and low power consumption at the same time even in a large capacity semiconductor memory device.

Here, the substrate potential generating circuit 2 and V
The cc converter 4 can obtain the corresponding effect even if only one of them is provided. 4 and 5,
Substrate / well potential Vsub of transistors 7 and 9 when only substrate potential generating circuit 2 or Vcc converter 4 is provided
And threshold voltage and internal power supply voltage Int. The changes in Vcc are shown respectively. The description of the transistors 6 and 8 is omitted.

Next, a specific example of the substrate potential generating circuit will be described.

FIG. 6 shows an example of the substrate potential generation circuit (a circuit for switching the substrate well potential between active and standby) 2 and FIG. 7 shows an example of the switching control signal generation circuit used in the circuit 2 of FIG. 8 shows operation timing charts of the circuit of FIG.

As shown in FIG. 6, the substrate potential generating circuit 2 has P
A circuit for controlling the substrate / well potential of the ch transistor, that is, the input external power supply voltage Ext. A first substrate potential generation circuit 11 for converting Vcc to a first substrate potential Vbbs, a capacitor 12 connected between its output terminal and a common potential Vss, and a first substrate potential generator 11 for transmitting the output of the first substrate potential generator 11. 1, the transmission gate 13, the input external power supply voltage Ex
t. A second substrate potential generator 14 for converting Vcc to a second substrate potential Vbbd, a capacitor 15 connected between its output terminal and the common potential Vss, and an output of this second substrate potential generator. The circuit includes a second transmission gate 16 and a circuit (not shown) for controlling the substrate / well potential of the Pch transistor.

The conduction of the first transmission gate 13 and the second transmission gate 16 is controlled by the first switching control signal φ1 and the second switching control signal φ2, respectively. The signals φ1 and φ2 are anti-phase signals generated from the ACT-bar signal indicating “Low” in the active state,
For example, as shown in FIG. 7, the signal φ1 and the signal φ2 are generated from the inversion circuits 17, 18 and 19 of the first stage and the second stage, respectively.

The output of the first substrate potential generator 11 is AC
It is applied to the substrate of transistor 9 regardless of the T-bar signal.

On the other hand, the ACT is formed on the substrate of the transistor 7.
Depending on the logic state of -bar, the first substrate potential generator 1
The output of either the first or second substrate potential generator 12 is applied. That is, as shown in FIG. 8, ACT-bar
Is "L" (active state), the output Vbbs of the first substrate potential generator 11 is applied, and when ACT-bar is "H" (standby state), the output of the second substrate potential generator 14 is Vbbd is applied.

Here, as the first substrate potential generating circuit 11 and the second substrate potential generating circuit 14, a known circuit having a function of converting a voltage value and outputting it may be used.

Next, a specific example of the Vcc converter 4 will be described.

FIG. 9 shows an example of the Vcc converter 4 shown in FIG.
0 shows the operation timing chart. Here, Vcc
The converter 4 includes a Pch transistor 20, an Nch transistor 24, operational amplifiers 21 and 25, and a transmission gate 2.
2, 23, 26, 27. The voltage input to each of the transmission gates 22, 23, 26, 27 is supplied by the external power supply voltage Ext. It is generated from Vcc.

The operation of this Vcc converter 4 is as follows.

At the time of active operation, the ATCD is activated and the reference voltage of the amplifiers 21 and 25 is set to Vcch + Δ. At that time, Int. When the level of Vcc is lower than Vcch + Δ, the transistor 20 is turned on and the transistor 2 is turned on.
4 is turned off, and Int. Vcc is charged to Vcch + Δ. If Int. If the level of Vcc is higher than Vcch + Δ, the transistor 20 is turned off and the transistor 24 is turned on, and Int. Vcc is Vcch +
It is discharged to Δ.

On the other hand, during standby, ACTD-bar
(Logical negation of ACTD) is activated and the amplifiers 21 and 2 are activated.
5 is lower than Vth + Vtl + 0.1, the transistor 20 is turned on, the transistor 24 is turned off, and Int. Vcc is charged to Vth + Vtl + 0.1. If Int. The level of Vcc is Vth + Vtl + 0.1
On the contrary, if it is too high, the transistor 20 is turned off.
F, the transistor 24 is turned on, and Int. Vcc is V
It is discharged to th + Vtl + 0.1.

When the substrate potential generating circuit 2 is provided, when switching from the active state to the standby state as shown in FIG. 10, after switching the substrate / well potential Vsub2, the internal power supply voltage Int. It is better to change the potential of Vcc.

Next, FIG. 11 shows a specific pattern example when the present invention is applied to a two-stage inverter as in this embodiment. 28 and 29 are trench element isolation regions, 40
Is an active layer, 41 is a polycrystalline silicon layer, 42 is a metal wiring layer, 43 ₁ , 43 ₂ and 46 are contact holes, 4
4, 45 are power lines, 31, 32 are P-type wells, 33, 3
4 is an N-type well. 6 is the first Pch in FIG.
Transistor, 7 for the first Nch transistor, 8
Corresponds to the second Pch transistor, and 9 corresponds to the second Nch transistor.

As shown in FIG. 11, when well isolation between wells whose potential is deepened and wells whose potential is not changed during standby is used, trench isolation whose width can be reduced to a design rule is used to maximize the increase in chip area. It is preferable because it can be suppressed to the limit.

FIG. 12 shows an example of a well structure when the present invention is applied.

Reference numeral 35 represents a well region forming a memory cell. The memory cells are, for example, DRAM memory cells, where 47 is a word line and 48 is a stack.
A capacitor, 49 is a gate oxide film, and 50 is an N ⁺ layer connected to the bit line.

Reference numerals 31 to 34 represent well regions forming cores and peripheral circuits. As described with reference to FIG. 11, the wells (31, 32, 33) of the same conductivity type in the core and the peripheral circuit are used.
Trench isolations 28 and 29 are used for the inter-well isolation in (34) and (34).

Reference numeral 36 represents a well region forming the substrate potential generation circuit 2, the Vcc converter 4, the Vbb generation circuits 11 and 14, the Vcell generation circuit, and the Vplate generation circuit. Thus, the plate potential Vplat used for the memory cell is
e and the cell well potential Vcell are the internal power supply voltage Int.
Ex, which is the power supply voltage outside the chip, not from Vcc
t. When configured using Vcc, the internal power supply voltage Int. V
It is preferable because the influence of the switching of cc does not affect the memory cell.

FIG. 13 shows the effect when the present invention is applied to a 4 Gb DRAM.

In the case of a semiconductor memory device formed by using a transistor having a gate length of 0.1 μm and a gate oxide film thickness of 3 nm, leakage current during standby (subthreshold leak, gate leak, band-to-band tunnel leak) is conventionally 1 μA per chip can be greatly reduced. Also, the delay time when active is 42
%, And high-speed performance can be realized. Moreover,
Int. Since Vcc can be set to a value higher than that of the conventional technique, the amount of charge stored in the memory cell can be increased by 20% as compared with the conventional technique, and stable operation can be realized.

The embodiment of the present invention has been described above.
The present invention can be applied to any semiconductor memory device other than DRAM. Further, the present invention can be applied to fluctuations regardless of whether the applied MIS transistor is formed in the well region or the substrate region.

The present invention is not limited to the above-mentioned embodiments, but can be modified in various ways without departing from the scope of the invention.

[0059]

According to the present invention (Claim 1), the absolute value of the threshold voltage of the MIS transistor that is cut off during standby is sufficiently increased, so that the subthreshold leakage current can be greatly reduced and at the time of activation. Since the absolute value of the threshold voltage can be set low, high-speed performance of circuit operation can be improved.

Therefore, even a large-capacity semiconductor memory device can simultaneously realize high-speed performance and low power consumption during standby.

According to the present invention (Claim 2), the internal power supply voltage can be set sufficiently low during standby to significantly reduce the gate leak current and the band-to-band tunnel leak current. The voltage can be increased to speed up the circuit.

Therefore, even a large-capacity semiconductor memory device can simultaneously realize high-speed performance and low power consumption during standby.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of a semiconductor memory device to which a Vcc converter and a substrate / well potential generating circuit according to an embodiment of the present invention are applied.

2 is a diagram showing changes in substrate potential, internal power supply voltage, and threshold voltage of each transistor in the circuit of FIG.

FIG. 3 shows a relationship between an internal power supply voltage and a propagation delay time in a standby state and an active state of the inverter circuit according to the example.

FIG. 4 is a diagram showing changes in a substrate potential, an internal power supply voltage, and a threshold voltage of each transistor in a modified example of the same embodiment.

FIG. 5 is a diagram showing changes in substrate potential, internal power supply voltage, and threshold voltage of each transistor in another modification of the same embodiment.

FIG. 6 is a diagram showing a substrate / well potential generation circuit according to an embodiment of the present invention.

FIG. 7 is a diagram showing a switching signal generation circuit according to the embodiment.

FIG. 8 is a diagram showing operation timing of the circuit of FIG.

FIG. 9 is a diagram showing a Vcc converter according to the same embodiment.

FIG. 10 is a diagram showing operation timing of the circuit of FIG.

FIG. 11 is a diagram showing an example of a mask pattern of a two-stage inverter to which the present invention is applied.

FIG. 12 is a diagram showing an example of a well configuration of a semiconductor memory device to which the present invention is applied.

FIG. 13 is a diagram for explaining an effect when the present invention is applied to a 4 Gbit DRAM.

FIG. 14 is a conceptual diagram showing a conventional technique.

FIG. 15 is a diagram for explaining a leak current path of a two-stage inverter.

FIG. 16 is a diagram showing a trend of the total channel width W of a transistor that contributes to subthreshold leakage during standby in a large capacity DRAM.

[Explanation of symbols]

2 ... Substrate / well potential generation circuit, 4 ... Internal power supply voltage control circuit, 6 ... First Pch transistor, 7 ... First Nc
h transistor, 8 ... second Pch transistor, 9 ...
Second Nch transistor, 10 ... Internal circuit, 11 ... First substrate potential generating circuit, 12, 15 ... Capacitor, 1
3, 16, 22, 23, 26, 27 ... Transmission gate, 14
... second substrate potential generating circuit, 17, 18, 19 ... inverting circuit, 20 ... Pch transistor, 21, 25 ... operational amplifier, 24 ... Nch transistor, 28, 29 ... trench element isolation region, 30, 31, 32, 35 ... P-type well,
33, 34, 36 ... N-type well, 40 ... Active layer, 41 ...
Polycrystalline silicon layer, 42 ... Metal wiring layer, 43 ₁ , 4
3 ₂ , 46 ... Contact holes, 44, 45 ... Power lines, 47 ... Word lines, 48 ... Stack capacitors, 4
9 ... Gate oxide film, 50 ... N ⁺ layer

Claims (2)

[Claims] 1. A plurality of memory cells for storing externally applied data, a circuit configured to use MIS transistors, for reading and writing the data from and to the memory cells, and in a standby state Control for controlling the substrate potential applied to the MIS transistor that is in the cutoff state so that the absolute value of the threshold voltage in the standby state of the MIS transistor is larger than the absolute value of the threshold voltage in the active state. A semiconductor memory device comprising: a substrate potential control means for performing the above. 2. A plurality of memory cells for storing data given from the outside, a circuit configured to use MIS transistors, for reading and writing the data from and to the memory cells, and an active state. The semiconductor memory device according to claim 1, further comprising: internal power supply voltage control means for increasing the internal power supply voltage directly applied to the current path of the MIS transistor to be higher than the internal power supply voltage applied in the standby state.