JP2003086706A - Semiconductor device and manufacturing method thereof, static random access memory device, and portable electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device including a dynamic threshold transistor that can reduce the leak current caused by the gate current. SOLUTION: A complimentary circuit is composed of an n-channel dynamic threshold transistor 4, and a p-channel dynamic threshold transistor 5. The gate electrode 152 is formed via a gate insulating film 151 on a p-type shallow well region 123 and an n-type shallow well region 124. In the p-type shallow well region 123, a p-type layer 127 having small impurity concentration and a p-type layer 125 having dense impurity concentration are formed successively from the surface side. In the n-type shallow well region 124, an n-type layer 128 having small impurity concentration, and an n-type layer 126 having large impurity concentration are formed successively from the surface side. The p-type layer 127 having small impurity concentration, and n-type layer 128 having small impurity concentration are as thick as 40 nm or less.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a manufacturing method thereof, a static random access memory device, and a portable electronic device. More specifically, the present invention relates to a semiconductor device including a dynamic threshold transistor, a method of manufacturing the semiconductor device, a static random access memory device including the semiconductor device, and a portable electronic device.

[0002]

2. Description of the Related Art MOSFET (Metal Oxide Semiconducer)
In order to reduce power consumption in a CMOS (complementary MOS) circuit using a tor field effect transistor, it is most effective to lower the power supply voltage. However, if the power supply voltage is simply lowered, the driving current of the MOSFET is lowered, and the operation speed of the circuit becomes slow. It is known that this phenomenon becomes remarkable when the power supply voltage becomes three times or less the threshold value of the transistor. In order to prevent this phenomenon, the threshold value may be lowered, but this causes a problem that the leak current when the MOSFET is off increases. Therefore, the lower limit of the threshold value is defined within the range where the above problem does not occur. Since the lower limit of the threshold value corresponds to the lower limit of the power supply voltage, the lower limit of power consumption is defined.

Conventionally, in order to alleviate the above problems, a dynamic threshold operating transistor (hereinafter referred to as DTM) using a bulk substrate.
It is called OS. ) Have been proposed (JP-A-10-224).
No. 62 publication, Novel Bulk Threshold Voltage MOSFET (B-
DTMOS) with Advanced Isolation (SITOS) and Gate to
Shallow Well Contact (SSS-C) Processes for UltraLow
Power Dual Gate CMOS, H. Kotaki et al., IEDM Tech.
Dig., P459, 1996). The DTMOS has a characteristic that a high driving current can be obtained with a low power supply voltage because the effective threshold value is lowered when it is turned on. The effective threshold of the DTMOS decreases when it is turned on because the gate electrode and the well region are electrically short-circuited.

The operating principle of the N-type DTMOS will be described below. The P-type DTMOS operates in the same manner by reversing the polarity. In the N-type MOSFET, when the potential of the gate electrode is at the low level (when off), the potential of the P-type well region is also at the low level, and the effective threshold value is the same as that of the normal MOSFET.
Therefore, the off current value (off leak) is
It is the same as in the case of FET.

On the other hand, when the potential of the gate electrode is at the high level (when it is on), the potential of the P-type well region also becomes at the high level, the effective threshold value is lowered by the substrate bias effect, and the drive current is normal. It is increased as compared with the case of MOSFET. Therefore, a large drive current can be obtained while maintaining a low leak current with a low power supply voltage. Therefore,
A CMOS circuit that is driven at low voltage and consumes low power is realized.

[0006]

However, the above-mentioned conventional DTMOS has a problem peculiar to DTMOS that a gate current flows when it is turned on because the gate electrode and the well region are electrically connected. there were.

The influence of the gate current will be considered with reference to FIGS. 10 and 11. FIG. 10 shows an N-channel DTMOS
It is a figure which shows the characteristic of drain current (Id) and gate current (Ig) vs. gate voltage (Vg). It can be seen that the gate current Ig increases exponentially as the gate voltage Vg increases. In the example of the N-channel type DTMOS shown in FIG. 10, the gate current Ig when the gate voltage Vg is 0.5V is comparable to the off current (Id at Vg = 0V).

FIG. 11 is a circuit diagram of a CMOS circuit including two stages of inverter circuits. Inverter circuits 1 and 2 are connected between the power supply line (VDD) and the ground line (GND). Each of the inverter circuits 1 and 2 includes an N-channel type DTMOS 11 and 13 and a P-channel type DTMOS, respectively.
It is composed of 12 and 14. The input of the inverter circuit 1 is provided with an input terminal IN, the output of the inverter circuit 1 is connected to the input of the inverter circuit 2, and the output of the inverter circuit 2 is provided with an output terminal OUT.

Now, consider the case where a low level is applied to the input terminal IN. At this time, the intermediate node MID
Is at a high level, and a low level is output to the output terminal OUT. At this time, the P-channel type DTMOS 12 and the N-channel type DTMOS 13 are turned on, and the N-channel type DTMOS 11 and the P-channel type DTMOS 1 are turned on.
4 is in the off state. In the N-channel DTMOS 11 in the off state, the off current of the level indicated by A in the graph of FIG. 10 flows through the path indicated by the arrow 22 in FIG. On the other hand, the N-channel DTM in the ON state
In the OS 13, the gate current of the level indicated by B in the graph of FIG. 10 flows in the route from the gate electrode to the source electrode as indicated by the arrow 23 in FIG. Here, the power supply voltage is assumed to be 0.6V. Off current A
And the gate current B from the power supply line VDD is a P-channel type DTM which is in an ON state as indicated by an arrow 21 in FIG.
It becomes a leak current flowing to the ground line GND through the OS 12. In the example of FIG. 10, when the power supply voltage is 0.6V,
The level B of the gate current is 1 compared to the level A of the off current.
Digit larger. Similar to the case of the N-channel type DTMOS described above, the OFF current and the gate current also flow in the P-channel type DTMOS, so that the same leak current occurs.

The source of the gate current is the forward junction current between the well region and the source region, which is proportional to the junction area. From the viewpoint of designing MOS transistors,
It is difficult to significantly reduce the gate current by reducing the junction area. Therefore, low power consumption CMO
In the S circuit, reducing the leak current when the circuit is in a static state has been a major issue. Especially in the CMOS circuit including the DTMOS, the reduction of the leak current caused by the gate current is peculiar to the DTMOS. Had been a problem.

Therefore, an object of the present invention is to provide a semiconductor device including a dynamic threshold transistor, which can reduce a leak current caused by a gate current. Another object of the present invention is to provide a semiconductor device manufacturing method capable of manufacturing such a semiconductor device, and a static random access memory device and a portable electronic device equipped with such a semiconductor device.

[0012]

In order to solve the above problems, in the semiconductor device of the first invention, the well region divided into each element by the element isolation region and the gate electrode are electrically connected. It has a complementary circuit consisting of a plurality of characteristic dynamic threshold transistors, the complementary circuit,
The complementary circuit has at least two modes: an active mode for operating the complementary circuit at a high speed and a standby mode for operating the complementary circuit at a low speed or stopping the operation. When in the bi-mode, a power supply voltage lower than that in the complementary mode is supplied to the complementary circuit.

According to the semiconductor device of the first aspect of the present invention, the complementary circuit including the dynamic threshold transistor has at least two operation modes of the active mode and the standby mode. In the active mode, a sufficiently high power supply voltage is supplied, so that the circuit can operate at high speed. On the other hand, when the circuit is in a dormant state or is operated at a low speed, a standby power supply mode is applied and a low power supply voltage can be applied to remarkably suppress the gate current which is the main cause of the leakage current. Therefore, it is possible to reduce the power consumption of the semiconductor device including the complementary circuit including the dynamic threshold transistor while keeping the operating speed high.

In the semiconductor device according to one embodiment, when the complementary circuit is in the standby mode, the gate current value of the dynamic threshold transistor forming the complementary circuit is equal to that of the dynamic threshold transistor. It is characterized in that it is less than the off current value.

According to the semiconductor device of this embodiment, the leak current of the complementary circuit can be sufficiently reduced to a magnitude defined by the off current of the dynamic threshold transistor. That is, the effect of the semiconductor device of the first invention can be maximized.

In the semiconductor device of one embodiment, the complementary circuit is divided into a plurality of basic circuit blocks, and each of the basic circuit blocks can be independently set to an active mode or a standby mode. Semiconductor device.

According to the semiconductor device of this embodiment, the complementary circuit formed of the dynamic threshold transistor can be divided into a plurality of basic circuit blocks, and each of them can be independently set to the active mode or the standby mode. .
Therefore, it is possible to reduce the leak current by setting only the basic circuit blocks that need to operate at high speed to the active mode and setting the other basic circuit blocks to the standby mode. Therefore, the power consumption can be further reduced while keeping the operating speed of the circuit high.

A semiconductor device according to a second aspect of the present invention is a semiconductor substrate, an element isolation region, deep well regions of the first conductivity type and the second conductivity type formed in the semiconductor substrate, and the first conductivity type. -Type and second-conductivity-type deep well regions respectively formed in the second-conductivity-type and first-conductivity-type shallow well regions, and a gate on the second-conductivity-type and first-conductivity-type shallow well regions. A plurality of gate electrodes formed through an insulating film, and the plurality of gate electrodes are electrically connected to the second-conductivity-type or first-conductivity-type shallow well regions, respectively. A first-conductivity-type and a second-conductivity-type dynamic threshold transistor, wherein the second-conductivity-type and first-conductivity-type shallow well regions are electrically isolated by an element isolation region for each of the dynamic-threshold transistors. The second conductivity type shallow In the well region, a layer of a second conductivity type having a low impurity concentration and a layer of a second conductivity type having a high impurity concentration are formed in order from the interface side with the gate insulating film in the depth direction. In the shallow well region of the first conductivity type, a layer having a low impurity concentration of the first conductivity type and a layer having a high impurity concentration of the first conductivity type are sequentially arranged in the depth direction from the interface side with the gate insulating film. Is formed, the thickness of the thin layer of the second conductivity type and the first conductivity type having a low impurity concentration is 40 nm or less, and a complementary circuit is formed by the dynamic threshold transistors of the first conductivity type and the second conductivity type. It is characterized by being configured.

According to the semiconductor device of the second aspect of the present invention, the first conductivity type and the second conductivity type dynamic threshold transistors form a complementary circuit. And the first
In the shallow well region of the second conductivity type (first conductivity type) of the conductivity type (second conductivity type) dynamic threshold transistor, the second conductivity is sequentially arranged from the interface side with the gate insulating film in the depth direction. A layer having a low impurity concentration of the first conductivity type (first conductivity type) and a layer having a high impurity concentration of the second conductivity type (first conductivity type) are formed, and the impurity concentration of the second conductivity type (first conductivity type) is formed. The thin layer has a thickness of 40 nm or less. Therefore, the layer having a high impurity concentration suppresses the extension of the depletion layer formed on the shallow well region side from the gate insulating film. As a result, the substrate bias effect is increased, so that the threshold value of the dynamic threshold transistor can be increased to reduce the off current. Therefore, it is possible to reduce the power consumption of the semiconductor device including the complementary circuit including the dynamic threshold transistor while keeping the operating speed high.

A method of manufacturing a semiconductor device according to a third aspect of the present invention is a method of manufacturing the semiconductor device according to the second aspect of the present invention, wherein the semiconductor device is formed on the semiconductor substrate at least after the step of forming the element isolation region. A step of forming a region having a high impurity concentration of the second conductivity type and the first conductivity type in the uppermost layer portion of the active region defined as a region where the element isolation region does not exist, and a step of depositing a semiconductor film on the entire surface, A step of performing the polycrystal semiconductor on the single crystal semiconductor film under the condition that the single crystal semiconductor film is selectively epitaxially grown on the active region and the polycrystal semiconductor film is grown on the region other than the active region; And selectively removing it.

According to the method of manufacturing a semiconductor device of the third invention, a region having a high impurity concentration is formed in advance in the uppermost layer of the active region, and then the single crystal semiconductor film is epitaxially grown. . Therefore, for the first-conductivity-type (second-conductivity-type) dynamic threshold transistor, the second-conductivity-type (first-conductivity-type) layer having a low impurity concentration and the It is possible to form a two-conductivity type (first conductivity type) layer having a high impurity concentration so as to have a steep profile that is difficult to achieve by ion implantation. In addition, since the film grown on the active region is a single crystal semiconductor film that inherits the orientation of the substrate crystal, a thermal process for recrystallizing is unnecessary, and a steep profile can be maintained.

Further, a polycrystalline semiconductor film that can be selectively etched with respect to the single crystal semiconductor film is formed on a region other than the active region, for example, on the element isolation region. Therefore, in order to separate the elements and the source / drain regions from each other, it is only necessary to remove the polycrystalline semiconductor film by isotropic etching.

Therefore, the semiconductor device of the second invention can be manufactured by a relatively simple process.

A semiconductor device manufacturing method according to a fourth aspect of the present invention is the method for manufacturing the semiconductor device according to the second aspect of the present invention, wherein the semiconductor device is formed on the semiconductor substrate at least after the step of forming the element isolation region. Forming a region having a high impurity concentration of the second conductivity type and the first conductivity type in the uppermost layer portion of the active region defined as a region where the element isolation region does not exist, and forming a single crystal semiconductor film only in the active region. And a step of selectively performing epitaxial growth.

According to the method for manufacturing a semiconductor device of the fourth invention, a region having a high impurity concentration is formed in advance in the uppermost layer of the active region, and then the single crystal semiconductor film is epitaxially grown. . Therefore, for the first-conductivity-type (second-conductivity-type) dynamic threshold transistor, the second-conductivity-type (first-conductivity-type) layer having a low impurity concentration and the It is possible to form a two-conductivity type (first conductivity type) layer having a high impurity concentration so as to have a steep profile that is difficult to achieve by ion implantation. In addition, since the film grown on the active region is a single crystal semiconductor film that inherits the orientation of the substrate crystal, a thermal process for recrystallizing is unnecessary, and a steep profile can be maintained.

Further, the single crystal semiconductor film is selectively epitaxially grown only on the active region. Therefore, isotropic etching or the like for isolating elements and source / drain regions on regions other than the active region is not necessary.

Therefore, the semiconductor device of the second invention can be manufactured by a simpler process.

A semiconductor device according to a fifth aspect of the present invention is a semiconductor substrate, an element isolation region, first and second conductivity type deep well regions formed in the semiconductor substrate, and the first conductivity type. And a second conductive type and first conductive type shallow well region formed in the second conductive type deep well region, and a gate insulating film on the second conductive type and first conductive type shallow well region, respectively. And a plurality of gate electrodes formed via the second gate electrode,
Electrically connected to the conductivity type or the first conductivity type shallow well region to respectively form a first conductivity type and a second conductivity type dynamic threshold transistor, and the second conductivity type and the first conductivity type are formed. The shallow well region is electrically isolated by the element isolation region for each of the dynamic threshold transistors.
On the shallow well region of conductivity type, a layer of low impurity concentration of the first conductivity type and a layer of high impurity concentration of the first conductivity type are formed in order from the interface side with the gate insulating film in the depth direction. Then, on the shallow well region of the first conductivity type, a layer of a second conductivity type having a low impurity concentration and a second conductivity type of the impurity concentration are sequentially formed in the depth direction from the interface side with the gate insulating film. A semiconductor device in which a dark layer is formed, and a complementary circuit is configured by the dynamic threshold transistors of the first conductivity type and the second conductivity type.

According to the semiconductor device of the fifth aspect of the present invention, a complementary type circuit is constituted by the first and second conductivity type dynamic threshold transistors. And the first
On the shallow well region of the second conductivity type (first conductivity type) of the conductivity type (second conductivity type) dynamic threshold transistor, the first conductivity is sequentially arranged from the interface side with the gate insulating film in the depth direction. A layer having a low impurity concentration of the type (second conductivity type) and a layer having a high impurity concentration of the first conductivity type (second conductivity type) are formed. Also with such a so-called counter-doped structure, the extension of the depletion layer can be suppressed similarly to the semiconductor device of the second invention. Moreover, the degree of the suppression is larger than that of the semiconductor device of the second invention. As a result, the substrate bias effect is further increased, and the threshold value of the dynamic threshold transistor can be further increased to reduce the off current. Therefore, it is possible to further reduce the power consumption of the semiconductor device including the complementary circuit including the dynamic threshold transistor while keeping the operating speed high.

The semiconductor device of the sixth invention comprises a plurality of dynamic threshold transistors characterized in that the well region divided for each element by the element isolation region and the gate electrode are electrically connected. It has a complementary circuit, and the substrate bias effect factor γ of the plurality of dynamic threshold transistors is 0.3 or more.

According to the semiconductor device of the sixth invention, it is possible to obtain a sufficiently large substrate bias effect as compared with the dynamic threshold transistor according to the prior art. Therefore, it is possible to reduce the power consumption of the semiconductor device including the complementary circuit including the dynamic threshold transistor while keeping the operating speed high.

The semiconductor device of the seventh invention is the semiconductor device of the first invention and the semiconductor device of any one of the second, fifth, and sixth inventions.

According to the semiconductor device of the seventh aspect of the invention, the off-leakage can be made extremely small by assembling the complementary circuit by using the dynamic threshold having a large substrate bias effect, and the circuit is placed in the standby state. At some times the gate current can be very small. Therefore, it is possible to significantly reduce the power consumption of the semiconductor device including the complementary circuit including the dynamic threshold transistor while keeping the operating speed high.

The static random access memory device of the eighth invention is characterized by including the semiconductor device of any one of the first, second, fifth and sixth inventions.

According to the static random access memory device of the eighth aspect of the present invention, the first, second, fifth
Since the semiconductor device according to any one of the sixth aspects is provided, the leakage current during standby can be reduced. Therefore, it is possible to reduce the power consumption while keeping the operating speed of the static random access memory high.

The portable electronic equipment of the ninth invention is characterized by including the semiconductor device or the static random access memory device of the above invention.

According to the portable electronic device of the ninth invention,
Since the semiconductor device is provided, the power consumption of the LSI (Large Scale Integrated Circuit) portion and the like is significantly reduced, and the battery life can be significantly extended.

[0038]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail below with reference to the embodiments shown in the drawings.

The semiconductor substrate that can be used in the present invention is not particularly limited, but a silicon substrate is preferable. Further, the semiconductor substrate may have a P-type or N-type conductivity.

(Embodiment 1) This embodiment is a DTM.
In a CMOS circuit including an OS, the power supply voltage is changed between when the circuit is in the active state and when the circuit is in the standby state, so that the leakage current caused by the gate current in the standby state is maintained while maintaining the operation speed of the circuit. The present invention relates to a semiconductor device that reduces Here, the active state means that the circuit is in an active mode in which the circuit operates at high speed, and the standby state means that the circuit is in a standby mode in which the circuit operates at low speed or is in a stopped state. The semiconductor device according to the first embodiment is shown in FIGS.
This will be described with reference to FIG.

FIG. 1 is a graph showing the characteristics of drain current (Id) and gate current (Ig) vs. gate voltage (Vg) in an example of N-channel type DTMOS. Figure 2
7 is a similar graph of an example of a P-channel DTMOS.
Note that Id and Ig are standardized to a current value per unit gate width.

From the viewpoint of the operating speed of the circuit, the larger the drain current, the faster the operating speed.
It is better to increase the power supply voltage within the range where the gate current does not increase significantly. In the example of FIG. 1, for example, the power supply voltage is 0.6V.
Can be However, when the circuit is substantially in the idle state (standby state), the gate current occupies most of the power consumption. As a method of reducing the current consumption due to the gate current, there is a method of cutting off the power supply to the circuit. As a result, the current consumption of the circuit can be reduced to zero. However, when the power supplied to the circuit is cut off, the state (information) at each node of the circuit is lost. To prevent this,
A non-volatile memory may be provided and the state may be stored in this memory before the power is turned off.

Another method of reducing the consumption current due to the gate current without providing a non-volatile memory for storing the above state is to lower the power supply voltage when the circuit is in the standby state. Since the gate current decreases exponentially when the power supply voltage is reduced, the current consumption of the circuit in the standby state can be significantly reduced. Moreover, since the state at each node of the circuit is retained, it is not necessary to provide a separate non-volatile memory. Further, it is not necessary to write the state of the circuit in the non-volatile memory or, conversely, read it from the non-volatile memory.

It is more preferable that the power supply voltage during standby is such that the gate current is equal to or less than off-leakage.
In the example of FIG. 1, the off-leakage is about 10 ⁻¹² A / μm, and the gate current becomes equal to that when the gate voltage is 0.4V. Further, in FIG. 2, the P-channel type DTMOS also has substantially the same characteristics except that the sign of the gate voltage is reversed. Therefore,
In the example of FIG. 1, it is more preferable to set the power supply voltage to 0.4 V or less when the circuit is in the standby state. Of course,
Since the off-leakage greatly changes depending on the threshold value of the device, the power supply voltage during standby may be appropriately determined so that the gate current is equal to or less than the off-leakage.

FIG. 3 is a diagram showing the configuration of the semiconductor device of this embodiment. Power is supplied from the power supply 3 to the basic circuit block 31 composed of the CMOS circuit by the DTMOS through the power supply line 33, the voltage adjusting circuit 32, and the power supply line 34. The voltage adjusting circuit 32 supplies a different voltage depending on whether the corresponding basic circuit block 31 is in the active state or the standby state.
Supply to. DTMO forming the basic circuit block 31
When S has the characteristics of FIG. 1 and FIG. 2, respectively, for example, 0.6 when the basic circuit block 31 is in the active state.
V is supplied with a voltage of 0.4 V in the standby state.

There may be a plurality of basic circuit blocks 31, as shown in FIG. In this case, the leak current can be suppressed by lowering only the power supply voltage supplied to the basic circuit block which should be in the standby state. Therefore,
When operating only a part of the circuits, it is possible to appropriately divide the circuit to be in the standby state and the circuit to be in the active state, and to reduce the power consumption while keeping the operating speed of the circuit high. .

The transistors constituting the basic circuit block 31 do not have to be composed of only DTMOS, and a part thereof may be a normal MOSFET.

According to the semiconductor device of this embodiment, the DT
The power supply voltage can be changed between when the basic circuit block composed of the CMOS circuit using MOS is in the active state and when it is in the standby state, and the power supply voltage can be lowered in the standby state. Therefore, when the circuit is in the standby state, the gate current, which accounts for most of the leak current of the CMOS circuit including DTMOS, can be significantly reduced. On the other hand, when the circuit is in the active state, a sufficiently large drain current is obtained, so that the circuit can be operated at high speed. Therefore, DTM
A semiconductor device including a CMOS circuit using an OS can have low power consumption while maintaining a high operating speed.

(Second Embodiment) A semiconductor device according to the second embodiment is a CMOS circuit composed of DTMOS.
By increasing the substrate bias effect of the TMOS, the threshold value for obtaining a desired drain current is raised, and as a result, the off current is reduced. The semiconductor device according to the second embodiment will be described with reference to FIGS.

FIG. 4 is a schematic cross-sectional view of the semiconductor device according to the second embodiment, in which an N-channel type DTMOS 4 and a P-channel type DTMOS 5 are drawn, respectively. Semiconductor substrate 1
An N-type deep well region 121 and a P-type deep well region 122 are formed on 11. Further, on the N type deep well region 121, a P type shallow well region 123 is formed.
However, N-type shallow well regions 124 are formed on the P-type deep well regions 122, respectively.

On the P-type shallow well region 123, an N-type source region 161 and an N-type drain region 162 are formed so as to be separated from each other, and a gate insulating film 151 is provided on the region between them. An electrode 152 is formed, and a gate sidewall insulating film 153 is formed on the sidewall of the gate electrode 152. Although not shown, the gate electrode 152 and P
The shallow well region 123 of the mold is electrically connected to form an N-channel type DTMOS 4. On the other hand, a P-type source region 163 and a P-type drain region 164 are formed on the N-type shallow well region 124 so as to be separated from each other, and a gate electrode is formed on the region between them via the gate insulating film 151. 152 is formed, and a gate sidewall insulating film 153 is further formed on the sidewall of the gate electrode 152. Although not shown, the gate electrode 152 and the N-type shallow well region 124
And are electrically connected to each other to form a P-channel type DTMOS 5.

In order to separate each element, an element isolation region 1
31, 132 are provided. Element isolation region 131,
132 is a shallow well region 123, 12 of each DTMOS
It has a sufficient depth to electrically isolate the four from each other. Thereby, even if the potentials of the shallow well regions 123 and 124 electrically connected to the gate electrode 152 are independently changed for each element, it is possible to prevent interference between the elements.

Immediately below the gate insulating film 151 of the N-channel type DTMOS 4, a region 127 having a low P-type impurity concentration is formed.
Is formed, and a region 125 having a high concentration of P-type impurities is formed further thereunder. On the other hand, P-channel type DT
A region 128 having a low N-type impurity concentration is formed immediately below the gate insulating film 151 of the MOS 5, and a region 126 having a high N-type impurity concentration is formed below the region 128.
The thickness of the region 127 having a low P-type impurity concentration and the region 128 having a low N-type impurity concentration can be, for example, 5 nm to 40 nm, and the impurity concentration thereof is, for example, 1 × 10 5.
^{It can be set to 17} cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ . The impurity concentrations of the regions 127 and 128 having a low impurity concentration may be determined so that the DTMOS has a desired threshold value. The thickness of the P-type impurity-rich region 125 and the N-type impurity-rich region 126 is, for example, 5 nm to 50 nm.
nm, and the impurity concentration thereof can be, for example, 2 × 10 ¹⁹ cm ^{−3 to} 5 × 10 ²⁰ cm ⁻³ . It is desirable that the lower ends of the regions 125 and 126 having a high impurity concentration be shallower than the lower surfaces of the source / drain regions 161-164. This is because the regions 125 and 126 having a high impurity concentration and the source / drain regions 161 to 16 are formed.
This is because the width of the depletion layer becomes very narrow at the junction with 4 and a large capacitance is added, so it is preferable to make the junction area as small as possible.

Consider the substrate bias effect of DTMOS. Here, the N-channel type DTMOS will be considered, but the same applies to the P-channel type DTMOS except that the signs are different. The substrate bias effect is an effect of increasing the drain current by lowering the threshold value of the transistor when a bias is applied to the shallow well region. It is convenient to use the substrate bias effect factor γ as an amount representing the magnitude of the substrate bias effect. γ = | ΔVt / Vb | (1)

Here, Vb is a voltage applied to the shallow well region with reference to the potential of the source region, and ΔVt is a threshold shift amount (negative value) due to the application of the voltage Vb to the shallow well region. is there. It should be noted that the threshold value here is a threshold value when the voltage Vb is constantly applied to the shallow well region, and is different from the threshold actually measured by the DTMOS in which the voltage of the shallow well region varies. DTMOS
In the above, γ is obtained from ΔVt when Vb is the power supply voltage Vdd.

From the equation (1), when a constant voltage Vb is applied to the shallow well region, the threshold shift amount ΔV increases as γ increases.
It can be seen that t increases and a large drive current flows.

The threshold shift amount ΔVt is inversely proportional to the width Xd of the depletion layer extending from the gate oxide film to the substrate side. ΔVt∝ToxVd / Xd (2)

Here, Tox is the gate insulating film thickness.
Therefore, in order to increase the substrate bias effect from the formula (2), it is effective to suppress the width Xd of the depletion layer extending from the gate insulating film to the substrate side.

The semiconductor device shown in FIG. 4 has a depletion layer width Xd.
It has a structure that suppresses Gate insulating film 151,1
The depletion layer extending from the interface between 51 and the regions 127 and 128 having a low impurity concentration to the substrate side is a region 12 having a high impurity concentration.
Almost no intrusion into 5,126. That is,
The regions 125 and 126 having a high impurity concentration function as a depletion layer stopper. Therefore, the thickness of the regions 127 and 128 having a low impurity concentration must be smaller than the thickness of the depletion layer in the case where the regions 125 and 126 having a high impurity concentration are not present. The thickness of the depletion layer when the inversion layer is formed is about 50 nm at an impurity concentration of 5 × 10 ¹⁷ cm ⁻³ when the regions 125 and 126 having a high impurity concentration are not provided. Therefore, the regions 125, 12 having a high impurity concentration
In order for 6 to fully fulfill the role of a depletion layer stopper, it is preferable that the regions 127 and 128 having a low impurity concentration have a thickness of 40 nm or less.

Here, the effect when γ is increased will be estimated. For example, in a well-structured DTMOS, γ is about 0.2. On the other hand, in the semiconductor device shown in FIG. 4, γ can be set to about 0.5. Vb =
Assuming that 0.6V, from the equation (1), when γ = 0.2, Δ
Vt = −0.12V, and when γ = 0.5, ΔVt =
It becomes −0.30V. That is, γ is 0.2 to 0.5
The absolute value of the shift amount of the threshold value increases by 0.18 V when the value increases. Therefore, if the same threshold value (the threshold value here is the threshold value when the substrate bias is 0), the drive current increases as γ increases. Further, if the drive current is the same, the threshold value increases when γ increases (the threshold value here is
The threshold value when the substrate bias is 0 can be increased. For example, when γ is increased from 0.2 to 0.5, the same drain current can be obtained even if the threshold value (the threshold value here is the threshold value when the substrate bias is 0) is increased by 0.18V ( Actually, the drain current becomes larger because the substrate concentration increases and the depletion layer width shrinks.) According to the subthreshold characteristic of DTMOS at room temperature, the drain current increases by one digit for every 0.06V gate voltage.
If the threshold value (the threshold value here is the threshold value when the substrate bias is 0) increases by 0.18 V, the off-current decreases by three digits. Thus, the off current can be reduced by increasing γ.

Similarly, γ = 0.3 and Vb = 0.6V
Then, ΔVt = −0.18V. Therefore,
If the drive current is the same, γ increases from 0.2 to 0.3, and the off-current decreases by one digit. In the semiconductor device shown in FIG. 4, the regions 127 and 128 having a low impurity concentration and the region 1 having a high impurity concentration are used.
Γ changes depending on the impurity concentrations of 25 and 126. Since DTMOS having a normal well structure has a γ of about 0.2, it is desirable that γ be 0.3 or more from the above results.

The γ of DTMOS can be estimated by the following method. The drive current in a normal MOS (MOSFET in which the gate electrode and the shallow well region are not connected) having the same well impurity profile as DTMOS is Icv. Here, the drive current is a drain current when 0 V is applied to the source region and a power supply voltage Vdd is applied to the gate electrode and the drain electrode in the case of the N-channel MOSFET. On the other hand, the drive current of DTMOS is set to Id
t. These are expressed by the following formula: Icv = WμCox (Vdd-Vtc) ² / 2L (3) Idt = WμCox (Vdd-Vtc-ΔVt) ² / 2L (4) γ = -ΔVt / Vdd (5) It Here, W is the gate width, μ is the mobility, Cox is the capacitance of the gate insulating film, and Vtc is usually M.
This is the threshold of the OS. From equations (3) to (5), Idt / Icv = (1-Vtc / Vdd + γ) ² / (1-Vtc / Vdd) ² (6), and other than γ are directly measurable amounts, ( 6)
Γ can be obtained from the equation.

Next, the procedure for forming the semiconductor device of the second embodiment will be described with reference to FIGS.

First, as shown in FIG. 5A, element isolation regions 131 and 132 are formed on the semiconductor substrate 111. The element isolation regions 131 and 132 are formed, for example, by STI.
(Shallow Trench Isolation) method can be used. By using the STI method, it is easy to simultaneously form element isolation regions of various widths. The depths of the element isolation regions 131 and 132 are set such that the shallow well regions 123 and 124 of the adjacent elements are electrically isolated from each other and the deep well regions 121 and 122 are not electrically isolated from each other. The depth of the element isolation regions 131 and 132 is preferably 0.2 μm to 2 μm, for example.

Next, an N type deep well region 121 and a P type deep well region 122 are formed in the semiconductor substrate 111. ³¹ P ⁺ is mentioned as an impurity ion which gives N type. For example, when ³¹ P ⁺ is used as the impurity ions, the implantation energy is 240 KeV to 15
00 KeV, injection amount 5 × 10 ¹¹ cm ⁻² to 1 ×
The condition may be 10 ¹⁴ cm ⁻² . ¹¹ B ⁺ is mentioned as an impurity ion which gives a P type. For example, when ¹¹ B ⁺ ions are used as the impurity ions, the implantation energy is 100 KeV to 1000 Ke.
V, as an injection amount 5 × 10 ¹¹ cm ⁻² to 1 × 10 ¹⁴
The condition may be cm ⁻² .

Next, on the deep well regions 121 and 122,
The P-type shallow well region 123 and the N-type shallow well region.
Forming a region 124. As an impurity ion giving N type
Is^{Three 1}P⁺Is mentioned. For example, with impurity ions
hand³¹P⁺When using, the injection energy is 13
0 KeV to 900 KeV, 5 × 10 as injection amount¹¹c
m^-2~ 1 x 10¹⁴cm^-2Can be formed under the conditions
it can. The impurity ions that give P-type are¹¹B⁺But
Can be mentioned. For example, as impurity ions¹¹B ⁺Io
If the energy used is 60 KeV
500 KeV, injection amount 5 × 10¹¹cm^-2~ 1
× 10¹⁴cm^-2Can be formed under the following conditions.

The order of the impurity implantation for forming the well region is not limited to the above, and the order may be exchanged.

The shallow well regions 123 and 124
The depth of the junction between the deep well regions 121 and 122 and the deep well regions 121 and 122 is determined by the conditions for implanting impurities into the shallow well regions 123 and 124, the conditions for implanting impurities into the deep well regions 121 and 122, and a thermal process performed thereafter. Determined by The depths of the element isolation regions 131 and 132 are set so that the shallow well regions 123 and 124 of the adjacent devices are electrically isolated and the deep well regions 121 and 122 are not electrically isolated.

Next, as shown in FIG. 5A, an impurity of the same conductivity type as that of the shallow well regions 123, 124 is implanted into the uppermost layers of the shallow well regions 123, 124 to obtain a P-type impurity concentration. Regions 125 and regions 126 having a high N-type impurity concentration are formed. ⁷⁵ As ⁺ may be mentioned as an impurity ion giving N type. For example, when ⁷⁵ As ⁺ is used as the impurity ion, the implantation energy is 3
KeV to 15 KeV, as an injection amount of 1 × 10 ¹² cm
It can be formed under the condition of ⁻² to 1 × 10 ¹³ cm ⁻² . ¹¹⁵ In ⁺ can be given as an example of the impurity ion that imparts P-type conductivity. For example, when ¹¹⁵ In ⁺ ions are used as the impurity ions, the implantation energy is 5 KeV to 20.
KeV, as injection amount 1 × 10 ¹² cm ⁻² to 1 × 10
¹³ cm ^- can be formed in ^two conditions.

Incidentally, as the impurity ions for forming the heavily doped regions 125 and 126, the ⁷⁵ As ⁺ ions and ¹¹⁵ In described above are used.
Besides ⁺ ion, ³¹ P ⁺ ion, ¹²² Sb ⁺ ion, ¹¹ B
⁺ Ion, ⁴⁹ BF ₂ ⁺ ion, decaborane ion and the like can also be used.

Next, as shown in FIG. 5B, the single crystal silicon film 141 inheriting the plane orientation of the silicon substrate is selectively epitaxially grown only in the exposed active region of the silicon substrate, and the other regions are formed. Is a polysilicon film 1
Grow 42. That is, the single crystal silicon film 141 is formed on the active region, and the element isolation regions 131 and 13 are formed.
A polysilicon film 142 is formed on the surface 2. The thickness of the single crystal silicon film 141 can be set to 8 nm to 50 nm, for example. The selective epitaxial growth can be performed by the following method. After cleaning the surface of the silicon substrate by HF (hydrofluoric acid) treatment, for example, 580 ° C. to 68 ° C. by LPCVD (Low Pressure Chemical Vapor Deposition) method.
0 Pa, Si ₂ H ₆ or SiH ₄ gas is 20 Pa to 1
If a silicon film is deposited under the condition of 00 Pa, a single crystal silicon film can be formed on the active region and a polysilicon film can be formed on the other regions. At the time of forming the silicon film, it is most desirable not to introduce a gas containing impurities that give the conductivity type.

Next, as shown in FIG. 5C, the polysilicon film 1 is formed by a mixed solution of hydrofluoric acid, nitric acid and acetic acid.
42 is selectively etched. As described above, the method of forming a single crystal silicon film on the active region and a polysilicon film on the other regions and etching only the polysilicon has the effect of preventing the remaining silicon on the element isolation region. It has the advantage of being large.

The step of forming a single crystal silicon film on the active region, the step of forming a polysilicon film on the other area, and the step of selectively etching the polysilicon film are different steps. It can be replaced. That is,
By selectively epitaxially growing the single crystal silicon film only on the active region in the state of FIG. 5A, the state of FIG. 5C can be directly obtained without etching. According to this method, the single crystal silicon film can be formed only on the active region with fewer steps.

Next, as shown in FIG. 6D, a gate insulating film 151 and a gate electrode 152 are formed on the single crystal silicon film 141. By the heat treatment at this time, the single crystal silicon film 141 has regions 125, 1 having a high impurity concentration.
Impurities diffuse from 26 to form a region 127 having a low P-type impurity concentration and a region 128 having a low N-type impurity concentration, respectively.

Next, as shown in FIG. 6E, source regions 161, 163 and drain regions 162, 164 are formed. At this time, by using the gate sidewall insulating film 153,
An LDD (Lightly Doped Drain) region may be formed by a known method.

A method of connecting a gate electrode and a shallow well region, which is essential for forming a DTMOS, is disclosed in Japanese Patent Laid-Open No. 10-22462.

After that, impurity activation annealing is performed.
The activation annealing is performed under the condition that the impurities are sufficiently activated and the impurities do not excessively diffuse. For example, 8
The annealing can be performed at 00 ° C. to 1000 ° C. for 10 to 100 seconds.

After that, a semiconductor device can be formed by forming a wiring and the like to form a CMOS circuit by a known method.

In addition to the DTMOS, the M of the normal structure is used.
OSFETs may be mixed. In this case, in an element that should be a normal MOSFET, the gate electrode and the shallow well region are not connected and the potential of the shallow well region may be fixed.

According to the above manufacturing method, a region having a high impurity concentration is formed in advance in the uppermost layer of the shallow well region, and then the single crystal silicon film is epitaxially grown. Therefore, from the surface side in the depth direction,
The regions 127 and 128 having a low impurity concentration and the regions 125 and 126 having a high impurity concentration can be formed so as to have a steep profile which is difficult by ion implantation.
In addition, since the film grown on the active region is single crystal silicon that inherits the orientation of the substrate crystal, a thermal process for recrystallizing is unnecessary, and a steep profile can be formed. Therefore, it is possible to form a CMOS circuit composed of DTMOS having a remarkable substrate bias effect.

According to the semiconductor device of this embodiment, the DTMOS
Regions 127 and 128 having a low impurity concentration are formed immediately below the gate insulating films 151 and 151 of 4 and 5, and regions 125 and 126 having a high impurity concentration are further formed thereunder. The regions 127 and 128 having a low impurity concentration are
DTMOS whose thickness has a normal impurity profile
Since it is thinner than the width of the gate depletion layer formed in, the width of the depletion layer extending from the gate insulating film to the shallow well region side is suppressed. Therefore, since the substrate bias effect is increased, DT
The off-current can be reduced by increasing the threshold value of the MOS. Therefore, it is possible to reduce the power consumption of the semiconductor device including the CMOS circuit using the DTMOS while keeping the operating speed high.

(Third Embodiment) A semiconductor device according to the third embodiment has a CMOS circuit including a DTMOS.
Another method of increasing the threshold value for obtaining a desired drain current by increasing the substrate bias effect of TMOS and consequently reducing the off current is shown. The semiconductor device according to the third embodiment will be described with reference to FIG.

The semiconductor device of the third embodiment differs from the semiconductor device of the second embodiment only in the impurity profile immediately below the gate insulating film. That is, in the third embodiment, in the channel region immediately below the gate insulating film,
A so-called counter-doped structure is adopted in which impurities of a conductivity type different from the conductivity type of the well region are doped.

Immediately below the gate insulating film 151 of the N-channel type DTMOS 6, a region 173 having a low N-type impurity concentration is formed.
And a region 171 having a high N-type impurity concentration is formed therebelow. On the other hand, P-channel type DT
A region 174 having a low P-type impurity concentration is formed immediately below the gate insulating film 151 of the MOS 7, and a region 172 having a high P-type impurity concentration is formed below the region 174.
The thickness of the regions 173 and 174 having a low impurity concentration is, for example, 5 nm to 10 nm, and the impurity concentration is 5 × 10 ^16.
It can be set to cm ^{−3 to} 2 × 10 ¹⁷ cm ⁻³ .
Further, the thickness of the regions 171 and 172 having a high impurity concentration is
For example, the impurity concentration is 1 × 10 5 nm to 15 nm.
^{It can be set to 17} cm ^{−3 to} 2 × 10 ¹⁸ cm ⁻³ .

The width of the gate depletion layer can also be suppressed by the semiconductor device of this embodiment. Moreover, since γ can be increased to about 0.8 to 1.0, the substrate bias effect can be further increased as compared with the semiconductor device of the second embodiment. Therefore, a CM based on DTMOS that can operate at high speed with lower power consumption
A semiconductor device including an OS circuit is provided.

(Embodiment 4) By combining the advantages of the semiconductor device of the first embodiment and the semiconductor device of the second or third embodiment, the C by DTMOS, which has lower power consumption, can be obtained.
A semiconductor device including a MOS circuit is provided.

In the semiconductor device of the first embodiment, the gate voltage is reduced by lowering the power supply voltage during standby. However, for example, in the example of FIG. 1, in the region where the power supply voltage is 0.4 V or less, the contribution to the leak current is dominated by the off current. Therefore, in order to further reduce the leak current, it is sufficient to raise the threshold value, but if this is done, the drive current will decrease and the operating speed of the circuit will decrease.

Therefore, if the semiconductor device of the second or third embodiment is used, the DTM is increased due to the increase of the substrate bias effect.
Since the threshold value can be increased while maintaining the OS drive current, off-leakage can be reduced. When the circuit is in standby, it is effective to further reduce the power supply voltage to reduce the gate current. Therefore,
A semiconductor device including a CMOS circuit using DTMOS
The power consumption can be further reduced while keeping the operating speed high.

(Embodiment 5) The semiconductor device according to any one of Embodiments 1 to 4 can be used for a static random access memory (SRAM). Although the SRAM can operate at high speed, since it is a volatile memory, the leakage current during standby has been a problem.

FIG. 8 is a circuit diagram of the SRAM according to the fifth embodiment. N1, N2, ST1 and ST2 are N-channel type DTMOSs, and P1 and P2 are P-channel type DTMs.
OS. WD is a word line, BIT1 is a first bit line, BIT2 is a second bit line, VDD is a power supply line, and G is a power line.
ND is a ground line.

N1 and P1, N2 and P2 are paired to form a complementary inverter circuit, and two inverter circuits form a flip-flop circuit. Also, ST
1 and ST2 are selection transistors. SRAM
In the case where DTMOS is formed by using the semiconductor device according to any one of the first to fourth embodiments, it is possible to reduce the leak current during standby. Therefore, it is possible to reduce the power consumption while keeping the operating speed of the static random access memory high.

(Embodiment 6) The semiconductor device according to any one of Embodiments 1 to 5 can be used for a battery-driven portable electronic device, particularly a portable information terminal. Examples of mobile electronic devices include personal digital assistants, mobile phones, and game devices.

FIG. 9 shows an example of a mobile phone. The semiconductor device of the present invention is incorporated in the control circuit 211. The control circuit 211 may be composed of an LSI (large scale integrated circuit) in which a logic circuit including the semiconductor device of the present invention and a memory are mounted together. 212 is a battery, 2
13 is an RF (radio frequency) circuit unit, 214 is a display unit, 2
Reference numeral 15 is an antenna portion, 216 is a signal line, and 217 is a power supply line.

By using the semiconductor device of the present invention in a mobile electronic device, it is possible to significantly reduce the power consumption of the LSI part while maintaining the function and operating speed of the mobile electronic device. This makes it possible to significantly extend the battery life.

[0095]

As is apparent from the above, according to the semiconductor device of the first invention, the complementary circuit including the dynamic threshold transistor has at least two operation modes of the active mode and the standby mode. In the active mode, a sufficiently high power supply voltage is supplied, so that the circuit can operate at high speed. On the other hand, when the circuit is in a dormant state or is operated at a low speed, a standby power supply mode is applied and a low power supply voltage can be applied to remarkably suppress the gate current which is the main cause of the leakage current. Therefore, it is possible to reduce the power consumption of the semiconductor device including the complementary circuit including the dynamic threshold transistor while keeping the operating speed high.

According to the semiconductor device of one embodiment, the leak current of the complementary circuit can be sufficiently reduced to the magnitude defined by the off current of the dynamic threshold transistor. That is, the effect of the semiconductor device of the first invention can be maximized.

According to the semiconductor device of one embodiment, the complementary circuit composed of the dynamic threshold transistor can be divided into a plurality of basic circuit blocks, and each of them can be independently set to the active mode or the standby mode. . Therefore, it is possible to reduce the leak current by setting only the basic circuit blocks that need to operate at high speed to the active mode and setting the other basic circuit blocks to the standby mode. Therefore, the power consumption can be further reduced while keeping the operating speed of the circuit high.

According to the semiconductor device of the second invention,
A complementary circuit is formed by the first conductivity type and the second conductivity type dynamic threshold transistors. Then, in the shallow well region of the second conductivity type (first conductivity type) of the dynamic threshold transistor of the first conductivity type (second conductivity type), in the depth direction from the interface side with the gate insulating film. A second conductive type (first conductive type) layer having a low impurity concentration and a second conductive type (first conductive type) layer having a high impurity concentration are sequentially formed, and the second conductive type (first conductive type) layer is formed. The thickness of the layer having a low impurity concentration of (type) is 40 nm or less. Therefore, the layer having a high impurity concentration suppresses the extension of the depletion layer formed on the shallow well region side from the gate insulating film. As a result, the substrate bias effect is increased, so that the threshold value of the dynamic threshold transistor can be increased to reduce the off current. Therefore, it is possible to reduce the power consumption of the semiconductor device including the complementary circuit including the dynamic threshold transistor while keeping the operating speed high.

According to the method for manufacturing a semiconductor device of the third invention, a region having a high impurity concentration is formed in advance in the uppermost layer of the active region, and then a single crystal semiconductor film is epitaxially grown. There is. Therefore, for the first-conductivity-type (second-conductivity-type) dynamic threshold transistor, the second-conductivity-type (first-conductivity-type) layer having a low impurity concentration and the It is possible to form a two-conductivity type (first conductivity type) layer having a high impurity concentration so as to have a steep profile that is difficult to achieve by ion implantation. In addition, since the film grown on the active region is a single crystal semiconductor film that inherits the orientation of the substrate crystal, a thermal process for recrystallizing is unnecessary, and a steep profile can be maintained.

Further, a polycrystalline semiconductor film which can be selectively etched with respect to the single crystal semiconductor film is formed on a region other than the active region, for example, on the element isolation region. Therefore, in order to separate the elements and the source / drain regions from each other, it is only necessary to remove the polycrystalline semiconductor film by isotropic etching.

Therefore, the high performance semiconductor device of the second invention can be manufactured by a relatively simple process.

According to the method of manufacturing a semiconductor device of the fourth invention, a region having a high impurity concentration is formed in advance in the uppermost layer of the active region, and then a single crystal semiconductor film is epitaxially grown. There is. Therefore, for the first-conductivity-type (second-conductivity-type) dynamic threshold transistor, the second-conductivity-type (first-conductivity-type) layer having a low impurity concentration and the It is possible to form a two-conductivity type (first conductivity type) layer having a high impurity concentration so as to have a steep profile that is difficult to achieve by ion implantation. In addition, since the film grown on the active region is a single crystal semiconductor film that inherits the orientation of the substrate crystal, a thermal process for recrystallizing is unnecessary, and a steep profile can be maintained.

Further, the single crystal semiconductor film is selectively epitaxially grown only on the active region. Therefore, isotropic etching or the like for isolating elements and source / drain regions on regions other than the active region is not necessary.

Therefore, the semiconductor device of the second invention can be manufactured by further simple steps.

According to the semiconductor device of the fifth invention,
A complementary circuit is formed by the first conductivity type and the second conductivity type dynamic threshold transistors. Then, on the shallow well region of the second conductivity type (first conductivity type) of the dynamic threshold transistor of the first conductivity type (second conductivity type), in the depth direction from the interface side with the gate insulating film. In this order, a layer having a low impurity concentration of the first conductivity type (second conductivity type) and a layer having a high impurity concentration of the first conductivity type (second conductivity type) are formed. Also with such a so-called counter-doped structure, the extension of the depletion layer can be suppressed similarly to the semiconductor device of the second invention. Moreover, the degree of the suppression is larger than that of the semiconductor device of the second invention. As a result, the substrate bias effect is further increased, and the threshold value of the dynamic threshold transistor can be further increased to reduce the off current. Therefore, it is possible to further reduce the power consumption of the semiconductor device including the complementary circuit including the dynamic threshold transistor while keeping the operating speed high.

Further, in the semiconductor device of the sixth invention, since the substrate bias effect factor γ of the above-mentioned dynamic threshold transistor forming a complementary circuit is 0.3 or more, it is In comparison, a sufficiently large substrate bias effect can be obtained. Therefore, it is possible to reduce the power consumption of the semiconductor device including the complementary circuit including the dynamic threshold transistor while keeping the operating speed high.

According to the semiconductor device of the seventh invention,
Off-leakage can be made very small by assembling a complementary circuit using a dynamic threshold having a large substrate bias effect, and the gate current can be made very small when the circuit is in a standby state. Therefore,
A semiconductor device including a complementary circuit including a dynamic threshold transistor can be remarkably reduced in power consumption while maintaining a high operation speed.

The static random access memory device of the eighth invention is the first, second, fifth and sixth inventions.
Since the semiconductor device according to any one of the present inventions is provided, the leak current during standby can be reduced. Therefore, it is possible to reduce the power consumption while keeping the operating speed of the static random access memory high.

Since the portable electronic equipment of the ninth invention comprises the semiconductor device of the invention described above, the power consumption of the LSI (Large Scale Integrated Circuit) etc. is greatly reduced and the battery life is greatly extended. be able to.

[Brief description of drawings]

FIG. 1 is a graph showing a gate voltage dependency of a drain current and a gate current of an N-channel type DTMOS included in a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a graph showing the gate voltage dependence of the drain current and the gate current of the P-channel type DTMOS which constitutes the semiconductor device of the first embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 4 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing a procedure for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a procedure for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram of a static random access memory device according to a fifth embodiment of the present invention.

FIG. 9 is a diagram showing a configuration of a mobile electronic device according to a sixth embodiment of the present invention.

FIG. 10 is a graph showing the gate voltage dependence of the drain current and the gate current of the N-channel type DTMOS, and is a diagram for explaining the problems of the conventional technique.

FIG. 11 is a circuit diagram of an inverter circuit configured by using DTMOS, and is a diagram for explaining the problems of the conventional technology.

[Explanation of symbols]

4,6 N-channel DTMOS 5,7 P-channel DTMOS 121 N-type deep well region 122 P-type deep well region 123 P-type shallow well region 124 N-type shallow well region 125,172 P-type high impurity concentration region 126,171 N-type high impurity concentration region 127,174 P-type low impurity concentration region 128,173 N-type low impurity concentration region 151 gate insulating film 152 gate electrode 161 N type source region 162 N-type drain region 163 P type source region 164 P-type drain region

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Seizo Kakimoto             22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka             Inside the company F-term (reference) 5F048 AA07 AB01 AC03 BA02 BB05                       BB14 BC06 BD04 BD09 BE01                       BE02 BE03 BE07 BG14                 5F083 BS02 BS14 BS26 GA06 NA01                       PR25

Claims (11)

[Claims] 1. A complementary circuit comprising a plurality of dynamic threshold transistors, characterized in that a well region divided for each element by an element isolation region and a gate electrode are electrically connected. The complementary circuit has at least two modes, an active mode for operating the complementary circuit at high speed and a standby mode for operating the complementary circuit at low speed or stopping the operation, When the complementary circuit is in the standby mode, a power supply voltage lower than that when the complementary circuit is in the active mode is supplied to the complementary circuit. . 2. The semiconductor device according to claim 1, wherein when the complementary circuit is in the standby mode, the gate current value of the dynamic threshold transistor forming the complementary circuit is the dynamic A semiconductor device having an off-state current value of the threshold transistor or less. 3. The semiconductor device according to claim 1, wherein the complementary circuit is divided into a plurality of basic circuit blocks, and each of the basic circuit blocks is independently set to an active mode or a standby mode. A semiconductor device characterized in that it can. 4. A semiconductor substrate, an element isolation region, a first-conductivity-type and second-conductivity-type deep well region formed in the semiconductor substrate, and a first-conductivity-type and second-conductivity-type deep well region. Second conductivity type and first conductivity type shallow well regions respectively formed in the well region, and a plurality of plural wells formed on the second conductivity type and first conductivity type shallow well regions through a gate insulating film. A plurality of gate electrodes, the plurality of gate electrodes being electrically connected to the second conductive type shallow well regions or the first conductive type shallow well regions, respectively, and having a first conductive type and a second conductive type, respectively. A dynamic threshold transistor, wherein the second conductivity type and first conductivity type shallow well regions are
Each of the dynamic threshold transistors is electrically isolated by an element isolation region, and in the shallow well region of the second conductivity type, a second conductivity type transistor is sequentially formed in the depth direction from an interface side with the gate insulating film. A layer having a low impurity concentration and a layer having a high impurity concentration of the second conductivity type are formed, and in the shallow well region of the first conductivity type, in order from the interface side with the gate insulating film in the depth direction, A layer having a low impurity concentration of the first conductivity type and a layer having a high impurity concentration of the first conductivity type are formed, and the thickness of the layer having a low impurity concentration of the second conductivity type and the first conductivity type is 40 nm or less. A semiconductor device, wherein a complementary circuit is configured by the first-conductivity-type and second-conductivity-type dynamic threshold transistors. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the element isolation region is defined as a region not present on the semiconductor substrate after at least the step of forming the element isolation region. The step of forming a region of high impurity concentration of the second conductivity type and the first conductivity type in the uppermost layer of the active region and the process of depositing a semiconductor film on the entire surface are selectively performed on the active region. Is epitaxially grown, and the polycrystalline semiconductor film is grown on a region other than the active region, and a step of selectively removing the polycrystalline semiconductor with respect to the single crystal semiconductor film is included. A method for manufacturing a characteristic semiconductor device. 6. The method of manufacturing a semiconductor device according to claim 4, wherein the element isolation region is defined as a region where the element isolation region does not exist on the semiconductor substrate after at least the step of forming the element isolation region. A step of forming a region of high impurity concentration of the second conductivity type and the first conductivity type in the uppermost layer portion of the active region; and a step of selectively epitaxially growing the single crystal semiconductor film only in the active region. A method for manufacturing a characteristic semiconductor device. 7. A semiconductor substrate, an element isolation region, a first-conductivity-type and second-conductivity-type deep well region formed in the semiconductor substrate, and a first-conductivity-type and second-conductivity-type deep well region. Second conductive type and first conductive type shallow well regions formed therein, and a plurality of gates formed on the second conductive type and first conductive type shallow well regions with a gate insulating film interposed therebetween. An electrode, and the plurality of gate electrodes are electrically connected to the second conductivity type or first conductivity type shallow well regions, respectively, and are respectively of a first conductivity type and a second conductivity type. A threshold transistor is formed, and the shallow well regions of the second conductivity type and the first conductivity type are
Each of the dynamic threshold transistors is electrically isolated by an element isolation region, and is formed on the shallow well region of the second conductivity type in the depth direction from the interface side with the gate insulating film in order. A layer having a low impurity concentration and a layer having a high impurity concentration of the first conductivity type are formed, and on the shallow well region of the first conductivity type, in order from the interface side with the gate insulating film in the depth direction, A layer of the second conductivity type having a low impurity concentration and a layer of the second conductivity type having a high impurity concentration are formed, and a complementary circuit is constituted by the first conductivity type and the second conductivity type dynamic threshold transistors. A semiconductor device characterized in that. 8. A complementary circuit comprising a plurality of dynamic threshold transistors, characterized in that a well region divided for each element by an element isolation region and a gate electrode are electrically connected. A semiconductor device, wherein the substrate bias effect factor γ of the plurality of dynamic threshold transistors is 0.3 or more. 9. A semiconductor device according to claim 4, which is the semiconductor device according to claim 1. Description: 10. A static random access memory device comprising the semiconductor device according to any one of claims 1 to 4, 7, 8, and 9. 11. A portable electronic device comprising the semiconductor device according to any one of claims 1 to 4, 7, 8 and 9 or the static random access memory device according to claim 10.