JPH10229165A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the amount of change of a desired threshold voltage at a small voltage and to reconcile a high-speed operation at a low voltage and a low standby leakage current, by a method wherein an operating mode signal is generated to control the change-over operations of first to fourth switches. SOLUTION: A CMOS inverter circuit has a first operating mode in operation and a second operating mode in standby and an operating mode change-over signal generator generates an operating mode change-over signal at an H level in the first operating mode to output the signal to each control terminal of switches SW1 to SW4, while the generator generates an operating mode change- over signal at an L level in the second operating mode to output the signal to each control terminal of the switches SW1 to SW4. The switches SW1 to SW4 are respectively changed over to the sides of contacts (a) in the first operating mode and to the sides of contacts (b) in the second operating mode. Accordingly, the amount of a charge of the substrate-source voltage of a P-channel MOS FET 1 and the amount of change of the substrate-source voltage on an N-channel MOS FET 2 are increased and a semiconductor integrated circuit device can obtain the amount of change of a desired threshold voltage at a low voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PMOSFET and an NMOS FE connected between a high-voltage power supply line having a voltage Vdd and a low-voltage power supply line having a voltage Vss.
The present invention relates to a semiconductor integrated circuit device including a CMOS circuit having T.

[0002]

2. Description of the Related Art In order to achieve low power while maintaining the speed of a semiconductor integrated circuit, a technique of lowering both a power supply voltage and a threshold voltage has been used. When the threshold voltage is lowered, there is a problem that the standby leak current becomes large.
"Tadahiro Kuroda et al." Cut power consumption by up to one digit by changing threshold voltage, "Nikkei Microdevices, 96
August, pp. 57-66 ", the prior art literature 2" Tetsuya Fujita ^{addition, "A 0.9V 150MHz 10mW 4mm 2} 2-D Discrete C
osine Transform Core Processor with Variable Thres
hold-Voltage (VT) Scheme ”, IEICE Technical Report, ED96-49, SDM96-32, ICD96-
52, June 1996 "and JP-A-6-53496.

In these prior arts, MOSFETs
In order to variably control the threshold voltage, the substrate-source voltage Vbs generated by controlling either the substrate voltage or the source voltage has been used. In this case, the voltage of the power supply line that does not control the voltage is fixed.

FIG. 5 shows a specific example in which the conventional VT system is applied to a CMOS inverter circuit. The VT method controls the threshold voltage by the substrate voltage.
The voltage of each source of the MOSFET and the PMOSFET is fixed at OV and 0.9V, respectively. Also, NM
The substrate voltage Vbn of the OSFET is -0.5 during circuit operation.
V during standby, and -3.3 V during standby.
The substrate voltage Vbp of the MOSFET is 1.4 during circuit operation.
V during standby and 4.2 V during standby.
Both the FET and the PMOSFET are set to 0.
In the standby state, a voltage Vbs between the substrate and the source in the reverse direction of 5 V and 3.3 V is applied. By the way, N
The absolute value of the threshold voltage of the MOSFET and the PMOSFET is 0.1 V during circuit operation and 0.5 V during standby, ensuring high-speed operation at low power supply voltage and suppressing leakage current during standby. Is possible.
Further, the value of the substrate voltage is subjected to feedback control by a threshold voltage fluctuation detection circuit called a leak current monitor and a substrate voltage control circuit, and is devised so that variations in the threshold voltage can be suppressed. I have.

[0005]

FIG. 6 shows an actual NMO.
The relationship between the substrate voltage Vbn (positive for forward bias and negative for reverse bias) and the threshold voltage Vtn in the SFET is shown. The source voltage is fixed at 0V,
The drain voltage is fixed at 0.1V. Generally, NM
The relationship between the substrate-source voltage Vbs and the threshold voltage Vt in the OSFET is expressed by the following equation (1).

[0006]

Vt = a + b · √ (c−Vbs)

Here, a, b and c are parameters depending on the device structure and the manufacturing process. In an NMOSFET using a silicon material, the value of c is in the range of about 0 to 1.2V. As is clear from FIG. 6 and Equation 1, when the threshold voltage Vt is controlled by changing the substrate-source voltage Vbs, the ratio ΔVt / ΔVbs of the change amount of Vt to the change amount of the substrate-source voltage Vbs. Becomes smaller as the absolute value of the reverse bias voltage is increased. Therefore, when only the reverse substrate-source voltage Vbs is used as in the prior art documents 1 and 2, a large Vbs difference is required to obtain a desired threshold voltage change amount. Furthermore, when only the reverse substrate-source voltage Vbs is used, it is necessary to lower the threshold voltage of the original MOSFET. In general, low threshold voltage MO
To form an SFET, a method of reducing the substrate concentration is known. However, when the substrate concentration is low, the substrate bias effect is reduced, and in order to obtain a desired threshold voltage change, a larger substrate / source is required. An inter-voltage Vbs is required. Further, when the substrate concentration is low, the short channel effect increases, and there is a problem that miniaturization of the element becomes difficult.

When a forward substrate-source voltage Vbs is also used as in the above-mentioned Japanese Patent Application Laid-Open No. 6-53496, the change amount ΔVbs for obtaining a desired change amount of the threshold voltage is as follows. Although it may be smaller than the case where only the reverse substrate-source voltage Vbs is used as in the prior art documents 1 and 2, a certain voltage is required only by controlling one of the substrate voltage and the source voltage. There is no change.

In this case, the gate oxide film withstand voltage of the MOSFET must be large, and it is necessary to take measures such as increasing the thickness of the gate oxide film. However, to increase the driving capability, a gate oxide film as thin as possible is used. Therefore, such a device structure is disadvantageous for high-speed operation at a low power supply voltage. In addition, the withstand voltage between wells must be large, and the advantage that the withstand voltage between wells can be reduced in correspondence with a low power supply voltage and the chip area can be reduced cannot be effectively utilized. In addition, for example, a charge pumping circuit is used to generate a voltage higher than the power supply voltage or a negative voltage. However, a charge pumping circuit having a high capability is required. In the example of the conventional VT system, the power supply voltage of the circuit is 0.9 V, but the gate oxide breakdown voltage of the MOSFET is 4.2 V.
There is a problem that a withstand voltage between wells is required to be 7.5 V, and a charge pumping circuit for generating ± 3.3 V with respect to the power supply voltage of the circuit is required.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, to obtain a desired amount of change in threshold voltage with a smaller voltage, and to achieve both high-speed operation at a low voltage and low standby leak current. It is to provide a device.

[0011]

According to a first aspect of the present invention, a semiconductor integrated circuit device is connected between a high voltage side power supply line having a voltage Vdd and a low voltage side power supply line having a voltage Vss. Further, in a semiconductor integrated circuit device including a CMOS circuit having a PMOSFET and an NMOSFET, a high-voltage side in a first operation mode supplied from a power supply circuit in accordance with an operation mode signal of the semiconductor integrated circuit device. First switching means for selectively switching between the power supply line voltage Vdd1 and the high voltage side power supply line voltage Vdd2 in the second operation mode to set the high voltage side power supply line voltage Vdd; Corresponding to the PMOSF in the first operation mode supplied from the power supply circuit.
Second switching means for selectively switching between the substrate voltage or the well voltage Vbp1 of the ET and the substrate voltage or the well voltage Vbp2 of the PMOSFET in the second operation mode to set the substrate voltage or the well voltage Vbp of the PMOSFET; , The NMOS FE in the first operation mode supplied from the power supply circuit in accordance with the operation mode signal.
Third switching means for selectively switching between the substrate voltage or well voltage Vbn1 of T and the substrate voltage or well voltage Vbn2 of the NMOSFET in the second operation mode to set the substrate voltage or well voltage Vbn of the NMOSFET; A low-side power supply line voltage Vss1 in the first operation mode and a low-side power supply line voltage Vss2 in the second operation mode, respectively, supplied from the power supply circuit in response to the operation mode signal. And the fourth switching means for selectively switching the first and second switching means to set the low-voltage side power supply line voltage Vss, and the switching operation of the first, second, third and fourth switching means by generating the operation mode signal. It is characterized by comprising control means for controlling.

Further, according to a second aspect of the present invention, there is provided a semiconductor integrated circuit device according to the first aspect, wherein Vd
d1>Vdd2>Vss2> Vss1, Vbp2> Vb
p1 and Vbn1> Vbn2.

Further, according to a third aspect of the present invention, there is provided a semiconductor integrated circuit device according to the first aspect.
dd1 = Vbp1, Vss1 = Vbn1, Vdd2 <V
bp2 and Vss2> Vbn2.

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit device according to the first aspect, wherein Vd
d1> Vbp1, Vbn1> Vss1, Vbp2> Vd
d2 and Vss2> Vbn2.

Further, the semiconductor integrated circuit device according to claim 5 is a semiconductor integrated circuit device according to claim 4,
dd1 = Vbp2, Vdd2 = Vbp1, Vss2 = V
bn1 and Vss1 = Vbn2.

Further, according to a sixth aspect of the present invention, in the semiconductor integrated circuit device according to the third aspect, the power supply circuit includes a voltage V supplied from a first power supply.
first applying means for applying dd1 = Vbp1 to the first and second switching means; and stepping down the voltage Vdd1 = Vbp1 supplied from the first power supply to a voltage Vdd2 to the first switching means. A first step-down means for supplying, and a voltage Vdd1 = Vbp1 supplied from the first power supply to a voltage Vb
a first booster which boosts the voltage to p2 and supplies the same to the second switching means, and a voltage Vbn1 = V supplied from a second power supply
second applying means for applying ss1 to the third and fourth switching means, and a voltage Vbn1 supplied from the second power supply.
= Vsn1 is reduced to a voltage Vbn2 and supplied to the third switching means, and the voltage Vbn1 = Vss1 supplied from the second power supply is raised to a voltage Vss2 and the fourth switching is performed. And a second boosting means for supplying the pressure to the means.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment> FIG. 1 is a circuit diagram showing a CMOS inverter circuit according to a first embodiment of the present invention and its power supply circuit. As shown in FIG. 1, the CMOS inverter circuit according to the present embodiment includes a PMOSFET 1 and an NMOS FET connected between a high-voltage power supply line having a voltage Vdd and a low-voltage power supply line having a voltage Vss.
A CMOS inverter circuit including ET2, which has a first operation mode when the circuit is operating and a second operation mode when the circuit is on standby. The operation mode switching signal generator 10 generates an H-level operation mode switching signal in the first operation mode to generate the switch SW1,
While output to each control terminal of SW2, SW3, SW4,
In the second operation mode, an L-level operation mode switching signal is generated to generate switches SW1, SW2, SW3, SW
4 to each control terminal.

In FIG. 1, the input signal is PMOSFE
Applied to each gate of T1 and NMOSFET2, PM
The source of the OSFET1 is connected to the high-voltage side power supply line having the voltage Vdd and the common terminal of the switch SW1, while the source of the NMOSFET2 is connected to the voltage Vss (<Vdd
d) and the common terminal of the switch SW4. The substrate voltage Vbp is applied to the semiconductor substrate of the PMOSFET 1 from the common terminal of the switch SW2, while the substrate voltage Vbn is applied to the semiconductor substrate of the NMOSFET 2 from the common terminal of the switch SW3. The drains of the PMOSFET 1 and the NMOSFET 2 are connected together, and an output signal is output from the drain.

Switches SW1, SW2, SW3, SW4
Are switched to the a-contact side in response to the H-level operation mode switching signal in the first operation mode, while b is switched in response to the L-level operation mode switching signal in the second operation mode. It is switched to the contact side. Therefore,
The switch SW1 responds to the operation mode switching signal, and supplies a high-voltage side power supply line voltage Vdd1 in the first operation mode, which is supplied from a power supply circuit formed inside the chip of the CMOS inverter circuit, and 2 is selectively switched between the high-voltage power supply line voltage Vdd2 and the high-voltage power supply line voltage Vdd. The switch SW2 responds to the operation mode switching signal by supplying the substrate voltage Vbp1 of the PMOSFET 1 in the first operation mode and the substrate voltage of the PMOSFET 1 in the second operation mode, respectively, supplied from the power supply circuit. Vbp2 is selectively switched to set the substrate voltage of PMOSFET1. Further, in response to the operation mode switching signal, the switch SW3 switches the first switch supplied from the power supply circuit to the first switch.
Substrate voltage Vbn of NMOSFET in the operation mode of
1 and the substrate voltage Vbn2 of the NMOSFET in the second operation mode are selectively switched to set the substrate voltage Vbn of the NMOSFET. Furthermore, the switch SW
Reference numeral 4 denotes a low-voltage power supply line voltage Vss1 in the first operation mode and a low-voltage power supply line in the second operation mode, which are supplied from the power supply circuit in response to the operation mode switching signal. The voltage Vss2 is selectively switched to set the low-voltage side power supply line voltage Vss.

In the first embodiment, for example, as is apparent from FIG.
In order for the S inverter circuit to operate at high speed (high-speed mode), Vdd1 = 3V, Vss1 = 0V, Vbp1 = 3.
5V, Vbn1 = -0.5V. At this time, PMO
Substrate-source voltage Vbsp1 of SFET1 = Vbp1
−Vdd1 = 0.5 V, and the substrate-source voltage Vbsn1 of NMOSFET2 = Vbn1−Vss1 = −
0.5V. PMOSFET 1 and NM at this time
OSFET2 threshold voltages Vthp1, Vthn1
By controlling the manufacturing process, Vthp1 =
Vthn1 was set to be 0.4V.

In the second operation mode, for example, Vdd2 = 2V, Vss2 = 1V, and Vbp2 = so that the standby leak current becomes small (standby mode).
4.5 V and Vbn2 = -1.5 V. At this time, P
MOSFET-substrate-source voltage Vbsp2 = Vb
p2-Vdd2 = 2.5V, and the substrate-source voltage Vbsn2 of NMOSFET2 = Vbn2-Vss2 =
−2.5V. PMOSFE at this time
T1 and threshold voltage Vthp2 of NMOSFET2
Vthn2 is controlled by controlling the manufacturing process.
It was set so that thp2 = Vthn2 = 0.7V.

In the present embodiment, the threshold voltage is changed by 0.3 V at a voltage change ΔVbs between the substrate and the source of 2 V. In order to obtain the substrate-source voltage change amount ΔVbs of 2V, when only the substrate voltage is changed, the substrate voltage change amounts ΔVbp and ΔVbn each require 2V. Since the power supply line voltage Vdd and the low-voltage side power supply line voltage Vss are also changed, the substrate voltage change amounts ΔVbp and ΔVbn may be 1 V, respectively.
Therefore, the gate oxide film breakdown voltage and the well breakdown voltage of the PMOSFET 1 and the NMOSFET 2 may be small. In this case, PMOSFET1 and NMOSFET2
Has a withstand voltage of 3.5 V and a withstand voltage between wells of 6 V.

In the above first embodiment, the PMOS
Each voltage applied to FET1 and NMOSFET2 is
The power is supplied from the power supply circuit formed inside the chip of the CMOS inverter circuit. However, the present invention is not limited to this. The power may be supplied from the outside of the chip. For example, a step-down circuit formed inside the chip shown in FIG. The power may be supplied using a circuit or a booster circuit.

In the first embodiment, Vdd1> V
dd2> Vss1 <Vss2, Vbp1 <Vbp2, V
This is realized by setting the relationship of bn1> Vbn2. That is, in the prior art, the high-voltage-side power line voltage Vdd and the low-voltage-side power line voltage Vss are fixed voltages, or the substrate voltage Vb
While p and the substrate voltage Vbn of the NMOSFET 2 are fixed voltages, in the present embodiment, the high-voltage power line voltage Vdd, the low-voltage power line voltage Vss,
Substrate voltage Vbp of PMOSFET 1 and NMOSFET
2 are all variable. Here, the first
When changing from the operation mode to the second operation mode,
The high voltage side power line voltage Vdd changes from the higher voltage Vdd1 to the lower voltage Vdd2 (Vdd1> Vdd2), and the low voltage side power line voltage Vss changes to the lower voltage Vss1.
To the higher voltage Vss2 (Vss1 <Vss2), and the substrate voltage Vbp of the PMOSFET 1 changes from the lower voltage Vbp1 to the higher voltage Vbp2 (Vbp1 <Vs2).
bp2), and the substrate voltage Vbn of the NMOSFET 2 changes from the higher voltage Vbn1 to the lower voltage Vbn2 (V
bn1> Vbn2). Therefore, PMOSFET
1 and the amount of change in the substrate-source voltage Vbsp of the PMOSFET 1 determined by the relative relationship between the substrate voltage Vbp and the high voltage side power supply line voltage Vdd, and the relative amount of the substrate voltage Vbn and the low voltage side power supply voltage Vss of the NMOSFET 2 Of the voltage Vbsn between the substrate and the source of the NMOSFET 2 determined by the dynamic relation becomes larger than the case where the same voltage change as in the conventional example is performed, that is, the change of the desired threshold voltage with a small voltage. You can get the quantity.

<Second Embodiment> FIG. 2 is a circuit diagram showing a CMOS inverter circuit and a power supply circuit thereof according to a second embodiment of the present invention. In FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals. Switches SW11, SW12, SW13, and SW14 are respectively
It has the same configuration as the switches SW1, SW2, SW3, and SW4 in FIG.
The respective a contacts of W12 are connected together and connected to a power supply of 3V, and the respective a contacts of the switches SW13 and SW14 are connected together and connected to a power supply of 0V (ground potential).

In the second embodiment, in the first operation mode of the CMOS inverter circuit, Vdd1 = 3V, so that the circuit operates at high speed (high-speed mode).
Vss1 = 0 V, Vbp1 = 3 V, and Vbn1 = 0 V. At this time, both the substrate-source voltage Vbsp1 of the PMOSFET 1 and the substrate-source voltage Vbsn1 of the NMOSFET 2 are 0 V, and no substrate-source voltage is generated. At this time, the PMOSFET 1 and the NMO
The threshold voltages Vthp1 and Vthn1 of SFET2 are
It was set so that Vthp1 = Vthn1 = 0.3V. On the other hand, in the second operation mode, Vdd2 = 2 so that the power consumption becomes small (low-speed / low-power mode).
V, Vss2 = 1V, Vbp2 = 4V, Vbn2 = −1
V. At this time, the substrate-source voltage Vbsp2 of PMOSFET1 = Vbp2-Vdd2 = 2V,
NMOSFET1 substrate-source voltage Vbsn2 = V
bn2−Vss2 = −2V. PMOS at this time
Threshold voltage Vthp of FET1 and NMOSFET2
2, Vthn2 was set so that Vthp2 = Vthn2 = 0.6 V by controlling the manufacturing process. In this case, PMOSFET1 and NMOSFE
The withstand voltage of the gate oxide film of T2 is 3V, and the withstand voltage between wells is 5V. In the second embodiment, in the first operation mode, Vdd1 = Vbp1 = 3V, Vss1 = V
Since bn1 is set to 0 V, the supplied voltage may be smaller than that in the first embodiment. The switching of each voltage is performed based on the operation mode switching signal generated by the operation mode switching signal generator 10 as in the first embodiment.

In the second embodiment, in the first operation mode of the circuit, Vdd1 = Vbp1, Vs1
Since s1 = Vbn1, a voltage between the substrate and the source is not generated, and a PMO having a relatively low threshold voltage is generated.
By using SFET1 and NMOSFET2,
The manufacturing process can be set similarly to the conventional CMOS inverter circuit, and the manufacturing cost can be reduced. On the other hand, in the second operation mode of the circuit,
By setting Vdd2 <Vbp2 and Vss2> Vbn2 and applying a reverse substrate-source voltage, the PMOSFET 1 and the NMOSFET 2 have relatively high threshold voltages, so that the leakage current can be reduced. is there. Also in this case, the high-voltage-side power line voltage Vdd and the substrate voltage Vbp change, and the low-voltage-side power line voltage Vss and the substrate voltage Vbn change in opposite directions, and attention is paid to either the voltage change of the power line or the substrate voltage. In this case, a larger change in the substrate-source voltage Vbsp or Vbsn can be obtained with the same voltage change as that of the conventional technique, and conversely, a desired change in the threshold voltage can be obtained with a small voltage. be able to.

In the second embodiment described above, the PMOS
Each voltage applied to FET1 and NMOSFET2 is
The power is supplied from a power supply circuit formed inside the chip of the CMOS inverter circuit. However, the present invention is not limited to this. The power may be supplied from outside the chip. For example, as shown in FIG. The voltage may be supplied from a step-down circuit or a step-up circuit.

In the modified example of FIG.
The voltage of V is applied to the respective a contacts of the switches SW11 and SW12, is reduced to 2V by the step-down circuit 11, and is applied to the contact b of the switch SW11. Is applied to the contact b. The voltage of 0 V (contact potential) from the power supply circuit is applied to each of the switches SW13 and SW14.
The voltage is applied to the contact and -1 V
And applied to the contact b of the switch SW13, while being boosted to 1V by the booster circuit 14 and
14 is applied to the contact b.

<Third Embodiment> FIG. 3 is a circuit diagram showing a CMOS inverter circuit and a power supply circuit thereof according to a third embodiment of the present invention. 3, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals.
In the present embodiment, the switches SW21, SW22,
SW23 and SW24 are switches SW of FIG.
1, SW2, SW3, SW4 and the switch SW1 of FIG.
1, SW12, SW13, and SW14,
Here, the voltage of 3 V from the power supply circuit is connected to the switch SW2
1 and the contact b of the switch SW22.
The voltage of 2.5 V from the power supply circuit is applied to the contact b of the switch SW21 and the contact a of the switch SW22, and the voltage of 0.5 V from the power supply circuit is applied to the contact a of the switch SW23 and the contact b of the switch SW24. The voltage of 0 V (ground potential) from the power supply circuit is applied to the contact b of the switch SW23 and the contact a of the switch SW24.

In the third embodiment, in the first operation mode of the CMOS inverter circuit, Vdd1 = 3V, so that the circuit operates at high speed (high-speed mode).
Vss1 = 0V, Vbp1 = 2.5V, Vbn1 = 0.
5V. Substrate-source voltage Vbsp1, Vbsn
1 is Vbsp1 = −0.5V, Vbsn1 = 0.5V
Becomes a forward bias. PMOSFET 1 at this time
And the threshold voltage Vthp1, Vt of NMOSFET2
hn1 was set so that Vthp1 = Vthn1 = 0.1V. On the other hand, in the second operation mode of the circuit, Vdd2 = 2.5 V, Vss2 = 0.5 V, Vb2 so that the power consumption becomes small (low-speed / low-power mode).
p2 = 3V and Vbn2 = 0V. The substrate-source voltages Vbsp2 and Vbsn2 are Vbsp2 = 0.5V,
Reverse bias occurs when Vbsn2 = -0.5V. At this time, the threshold voltages Vthp2 and Vthn2 of the PMOSFET1 and the NMOSFET2 are Vthp2 = Vth
n2 was set to 0.4 V. In this case, the PMOS
The gate oxide film breakdown voltage of the FET1 and the NMOSFET 2 may be 2.5V, and the breakdown voltage between wells may be 3V.

In the third embodiment, although the amounts of change .DELTA.Vbsp and .DELTA.Vbsn of the voltage between the substrate and the source are as small as 1 V (2 V in the second embodiment), the amount of change in the threshold voltage is the second. As in the embodiment, ΔVth = 0.
3V was obtained. In the third embodiment, Vdd1 = Vb
p2 = 3V, Vss1 = Vbn2 = 0V, Vdd2 = V
Since bp1 = 2.5V and Vss2 = Vbn1 = 0.5V, the supplied voltage may be smaller than in the second embodiment.

In the third embodiment, in order to obtain a desired amount of change in threshold voltage with a smaller voltage, in the first operation mode of the circuit, Vdd1> Vbp
1. By setting Vbn1> Vss1, it can be realized by using a forward substrate-source voltage.
When the forward substrate-source voltage Vbs is also used,
This is because ΔVbs for obtaining a desired threshold voltage change amount may be smaller than the case where only the reverse substrate-source voltage Vbs is used. On the other hand, in the second operation mode of the circuit, preferably, Vbp2> Vdd
2 and Vss2> Vbn2.

Further, Vdd1 = Vbp2, Vdd2 =
Vbp1, Vss2 = Vbn1, and Vss1 = Vbn
By setting to 2, the circuit configuration of the semiconductor integrated circuit device provided with the CMOS inverter circuit becomes extremely simple.

In the above third embodiment, the PMOS
Each voltage applied to FET1 and NMOSFET2 is
The power is supplied from the power supply circuit formed inside the chip of the CMOS inverter circuit. However, the present invention is not limited to this. The power may be supplied from the outside of the chip. For example, a step-down circuit formed inside the chip shown in FIG. The power may be supplied using a circuit or a booster circuit.

In the first to third embodiments described above,
Each substrate voltage V of PMOSFET1 and NMOSFET2
bp and Vbn to change the PMOSFET 1 and NMO
Although the threshold voltage of the SFET 2 is changed, the present invention is not limited to this, and the PMOSFET 1 and the NMOSFET
2 and the PMOSFET 1 and the NM
The threshold voltage of the OSFET 2 may be changed.

[0038]

As described above in detail, according to the semiconductor integrated circuit device of the first aspect of the present invention, the high voltage side power supply line having the voltage Vdd and the low voltage side power supply line having the voltage Vss are provided. PMOSFET and NMOSF connected between
In a semiconductor integrated circuit device including a CMOS circuit provided with an ET, a high-voltage side power supply line voltage Vdd1 in a first operation mode is supplied from a power supply circuit in accordance with an operation mode signal of the semiconductor integrated circuit device. And first switching means for selectively switching between the high-voltage-side power supply line voltage Vdd2 in the second operation mode to set the high-voltage-side power supply line voltage Vdd; and A substrate voltage or a well voltage Vbp1 of the PMOSFET in the first operation mode supplied from the power supply circuit;
By selectively switching the substrate voltage of the PMOSFET or the well voltage Vbp2 in the second operation mode, the PMOS
Second setting of the FET substrate voltage or well voltage Vbp
And N in the first operation mode supplied from the power supply circuit in accordance with the operation mode signal.
By selectively switching between the substrate voltage or well voltage Vbn1 of the MOSFET and the substrate voltage or well voltage Vbn2 of the NMOSFET in the second operation mode, the NMOS transistor
A third switching means for setting the substrate voltage or the well voltage Vbn of the ET, and a low-voltage-side power supply line voltage Vss1 in the first operation mode, respectively, supplied from the power supply circuit in accordance with the operation mode signal. Fourth switching means for selectively switching between the low-voltage-side power supply line voltage Vss2 in the second operation mode and setting the low-voltage-side power supply line voltage Vss;
And control means for generating the operation mode signal and controlling the switching operation of the first, second, third and fourth switching means. Therefore, the voltage of the power supply line of the CMOS circuit and the MOS
The substrate voltage of the FET can be set independently of each other and can be variably set in accordance with the operation mode of the circuit. Since both the power supply line and the substrate voltage are changed, a smaller voltage is required as compared with the conventional example. , The amount of change in the threshold voltage can be obtained, and high-speed operation at a relatively low voltage and low standby leak current can be achieved at the same time.

According to a second aspect of the present invention, in the semiconductor integrated circuit device of the first aspect, Vdd1>Vdd2>Vss2> Vss1, Vbp
2> Vbp1 and Vbn1> Vbn2. Therefore, a desired amount of change in threshold voltage can be obtained with a smaller voltage than in the conventional example, and both high-speed operation at a relatively low voltage and low standby leak current can be achieved.

Further, in the semiconductor integrated circuit device according to the third aspect, in the semiconductor integrated circuit device according to the first aspect, Vdd1 = Vbp1, Vss1 = Vbn1, Vd1
d2 <Vbp2 and Vss2> Vbn2. Therefore, in the first operation mode of the circuit, since Vdd1 = Vbp1 and Vss1 = Vbn1, the voltage between the substrate and the source is not generated, and the normal C
It is possible to set the same manufacturing process as the MOS circuit,
Manufacturing costs can be reduced.

According to a fourth aspect of the present invention, there is provided the semiconductor integrated circuit device according to the first aspect, wherein Vdd1> Vbp1, Vbn1> Vss1, Vbp.
2> Vdd2 and Vss2> Vbn2. Therefore, in the first operation mode of the circuit,
Since Vdd1> Vbp1 and Vbn1> Vss1 are set and a forward substrate-source voltage is used, a desired threshold voltage change can be obtained with a smaller voltage.

Further, in the semiconductor integrated circuit device according to the fifth aspect, in the semiconductor integrated circuit device according to the fourth aspect, Vdd1 = Vbp2, Vdd2 = Vbp1, Vs1
It is set so that s2 = Vbn1 and Vss1 = Vbn2. Therefore, the configuration of the circuit can be further simplified.

Further, in the semiconductor integrated circuit device according to a sixth aspect, in the semiconductor integrated circuit device according to the third aspect, the power supply circuit adjusts the voltage Vdd1 = Vbp1 supplied from the first power supply to the first power supply. And first applying means for applying the voltage to the second switching means, and first voltage reducing means for reducing the voltage Vdd1 = Vbp1 supplied from the first power supply to a voltage Vdd2 and supplying the voltage to the first switching means. A first booster that boosts the voltage Vdd1 = Vbp1 supplied from the first power supply to a voltage Vbp2 and supplies the same to the second switching means; and a voltage Vbn supplied from the second power supply.
1 = Vss1 to the third and fourth switching means, a second applying means, and a voltage V supplied from the second power supply.
bn1 = Vsn1 to a voltage Vbn2, a second step-down means for supplying the voltage to the third switching means, and a voltage Vbn1 = Vss1 supplied from the second power supply to a voltage Vss2.
And a second booster for supplying the boosted voltage to the fourth switch. Therefore, the configuration of the circuit can be further simplified.

[Brief description of the drawings]

FIG. 1 shows a CMOS according to a first embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating an inverter circuit and a power supply circuit thereof.

FIG. 2 shows a CMOS according to a second embodiment of the present invention;
FIG. 3 is a circuit diagram illustrating an inverter circuit and a power supply circuit thereof.

FIG. 3 is a CMOS according to a third embodiment of the present invention;
FIG. 3 is a circuit diagram illustrating an inverter circuit and a power supply circuit thereof.

FIG. 4 is a CMO that is a modification of the second embodiment of FIG. 2;
FIG. 3 is a circuit diagram showing an S inverter circuit and a power supply circuit thereof.

FIG. 5 is a circuit diagram showing a conventional CMOS inverter circuit and its power supply circuit.

FIG. 6 is a graph showing a relationship between a substrate voltage Vbn and a threshold voltage Vtn in an NMOSFET used in the CMOS inverter circuits of FIGS. 1 to 4;

[Explanation of symbols]

1 ... PMOSFET, 2 ... NMOSFET, 10 ... operation mode switching signal generator, 11, 13 ... step-down circuit, 12, 14 ... step-up circuit, SW1, SW2, SW3, SW4. SW11, SW1
2, SW13, SW14, SW21, SW22, SW2
3, SW24: switch, Vbp: substrate voltage of PMOSFET1, Vbn: substrate voltage of NMOSFET2, Vdd: high-voltage side power supply line voltage, Vss: low-voltage side power supply line voltage.

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI H03K 17/687 H03K 19/00 101F 19/0175 19/094 B 19/0948

Claims (6)

[Claims] A high-voltage side power supply line having a voltage Vdd;
CMOS with PMOSFET and NMOSFET connected between low-voltage side power supply line having voltage Vss
In a semiconductor integrated circuit device including a circuit, a high-voltage-side power supply line voltage Vdd1 in a first operation mode, which is supplied from a power supply circuit in accordance with an operation mode signal of the semiconductor integrated circuit device, First switching means for selectively switching between the high-voltage-side power supply line voltage Vdd2 in the operation mode to set the high-voltage-side power supply line voltage Vdd; The substrate voltage or well voltage Vbp1 of the PMOSFET in the first operation mode and the substrate voltage or well voltage Vb1 of the PMOSFET in the second operation mode
a second switching means for selectively switching between p2 and p2 to set a substrate voltage or a well voltage Vbp of the PMOSFET, and a first switching mode supplied from a power supply circuit in response to the operation mode signal. NMOSFET substrate voltage or well voltage Vbn1 and NMOSFET substrate voltage or well voltage Vb in the second operation mode
a third switching means for selectively switching n2 to set the substrate voltage or the well voltage Vbn of the NMOSFET; and a third switching means for supplying the power supply circuit in response to the operation mode signal. Fourth switching means for selectively switching between the low-voltage power line voltage Vss1 and the low-voltage power line voltage Vss2 in the second operation mode to set the low-voltage power line voltage Vss; A semiconductor integrated circuit device comprising control means for generating a mode signal to control the switching operation of the first, second, third, and fourth switching means. 2. Vdd1>Vdd2>Vss2> Vss
2. The semiconductor integrated circuit device according to claim 1, wherein: Vbp2> Vbp1 and Vbn1> Vbn2 are set. 3. Vdd1 = Vbp1, Vss1 = Vbn
2. The semiconductor integrated circuit device according to claim 1, wherein Vdd2 <Vbp2 and Vss2> Vbn2. 4. Vdd1> Vbp1, Vbn1> Vss
2. The semiconductor integrated circuit device according to claim 1, wherein Vbp2> Vdd2 and Vss2> Vbn2 are set. 5. Vdd1 = Vbp2, Vdd2 = Vbp
5. The semiconductor integrated circuit device according to claim 4, wherein Vss2 = Vbn1 and Vss1 = Vbn2. 6. The power supply circuit includes: first application means for applying a voltage Vdd1 = Vbp1 supplied from a first power supply to the first and second switching means; and a power supply circuit supplied from the first power supply. Voltage Vdd1 = Vbp1
Step-down means for stepping down the voltage to a voltage Vdd2 and supplying the same to the first switching means; and voltage Vdd1 = Vbp1 supplied from the first power supply.
To a voltage Vbp2 to supply the voltage to the second switching means, and a second voltage applying the voltage Vbn1 = Vss1 supplied from the second power supply to the third and fourth switching means. And a voltage Vbn1 = Vss1 supplied from the second power supply.
To a voltage Vbn2 and supplying the same to the third switching means, and a voltage Vbn1 = Vss1 supplied from the second power supply.
And a second booster for boosting the voltage to a voltage Vss2 and supplying the boosted voltage to the fourth switch.
13. The semiconductor integrated circuit device according to claim 1.