KR100250928B1 - Sub row decoder circuit - Google Patents

Abstract

PURPOSE: A sub row decoder circuit is provided to prevent a standby current from being increased although metal lines are shorted as making the potential of a pull-up signal and a pull-down signal identical in a standby state by connecting the source of a pull-down transistor disabling a word line to a pull-up signal, not a ground voltage. CONSTITUTION: The circuit includes a bootstrap transistor(MN4), a pull-up transistor(MN5), a switching device(MN6) and a pull-down transistor(MN7). The bootstrap transistor is connected between a pull-up signal input node and a bootstrap node. A potential signal is applied to the gate of the bootstrap transistor. The pull-up transistor the gate of which is connected to the bootstrap node is connected between a word line boosting signal line and a word line. The switching device is connected between the pull-up signal input node and the first node. A signal which the pull-up signal is inverted is applied to the gate of the switching device. The pull-down transistor is a diode structure in which the source of the pull-down transistor is connected to one end of the switching device and the drain to the word line.

Description

Sub row decoder circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a sub-row decoder circuit of a semiconductor memory device having a pull-up transistor for transmitting a word line boosting signal to a word line and a pull-down transistor for transmitting a ground voltage to the word line. By connecting the source of the transistor to the pull-up signal rather than the ground voltage, the pull-up and pull-down signals are at the same potential in the standby state, eliminating the increase in standby current even if the metal lines are shorted to each other. It is related to a sub row decoder circuit.

A row decoder is used to control word lines in a semiconductor memory device. However, due to the high integration of memory devices, there is not enough space to lay out one decoder per word line. Therefore, at present, a plurality of hierarchical word line driving circuits are unique to an output of a single loo decoder, and a hierarchical word line driving circuit is used to distinguish them by a sub row decoder (pxi generator).

In general, a hierarchical word line structure is used to mitigate the strict metal design rules that occur in metal strapping of word lines. Metal strapping is a method of arranging metal lines on top of a cell array with a word line pitch and connecting them to a poly-silicon word line to reduce the resistance of word lines made of poly-silicon. This reduces the resistance of the word line, resulting in faster drive times. (Pitch here refers to the sum of Line Width + Space in regularly arranged lines.) This metal strapping method decreases the word line pitch as the density of memory elements increases. Therefore, the failure rate of the metal process increases, and yield is reduced. Therefore, the hierarchical word line structure has been applied to 64M DRAM products.

The conventional lower word line driving circuit used in the hierarchical word line structure is generally composed of three NMOS transistors, and the voltage level of the lower word line is boosted through a double bootstrapping process. Drive at high potential (Vpp).

1 is a detailed circuit diagram of a conventional sub row decoder circuit for driving a word line WLi, which is connected between an input signal line N1 and a second node N2 and has a potential signal Vx applied to a gate thereof. A second NMOS transistor MN2 connected between a first NMOS transistor MN1, a word line boosting signal px + 0 line, and a word line SWL0 and having a gate connected to the second node N2; The third NMOS transistor MN3 is connected between the word line SWL0 and the ground voltage Vss and applied with an inverted signal of the input signal to the gate.

The pull-up transistor MN2, which is the second NMOS transistor, pulls up the word line WL to Vpp level, and the pull-down transistor MN3, which is the third NMOS transistor, is pulled to 'OV' (ground). -It performs the role of down. The bootstrap transistor MN1, which is the first NMOS transistor, serves as a switch to maintain the potential after precharging and bootstrapping the second node N2. That is, in most cases, Vx = Vcc and after precharging the second node N2 with Vx = Vt (Vt is a threshold voltage), the word line boosting signal px is delayed after a predetermined time Td is delayed. As the second node N2 is bootstrapped to a voltage of Vpp + Vt or more as it is activated to the high potential Vpp ', the voltage' Vpp 'of the wordline boosting signal px is pull-up transistor MN1. The data is transferred to the word line WL0 as it is.

In DRAM, polycrystalline silicon is generally used as a gate of a cell transistor. However, due to the large resistance of polycrystalline silicon, signal propagation to cells far away from the row decoder is slowed down. In order to compensate for this drawback, a metal strapping method is used. As the integration becomes higher, the space between the metal and the metal becomes narrower, which makes it difficult to proceed with the process. Using the sub row decoder method reduces the number of metal lines to half or less, thereby facilitating the process. Conventional sub-loo decoders include a method of using CMOS and a method of using NMOS. With CMOS, the metal lines are reduced to one quarter, making the metal process easier, and even if the metal lines are short to each other, the standby current increases because the metal lines are held at the same potential in the standby state. There is an advantage not to do this, but the use of PMOS requires a separate N-well, thus occupying a large area. The use of NMOS has the advantage that the area can be reduced because no separate wells are required, but when the metal lines are shorted to each other because the metal lines are placed at different potentials in the standby state, There was a problem that the value of the product is lost even if the current is increased, even if the repair (repair).

Therefore, in the present invention, by connecting the source of the pull-down transistor for disabling the word line to the pull-up signal, not the ground voltage, so that the pull-up signal and the pull-down signal become the same potential in the standby state, the metal line It is an object of the present invention to provide a sub row decoder circuit that eliminates an increase in quiescent current even if they are shorted to each other.

In order to achieve the above object, a sub row decoder circuit according to an embodiment of the present invention includes a bootstrap transistor in a semiconductor memory device, which is connected between a pull-up signal input node and a bootstrap node and a potential signal is applied to a gate; A pull-up transistor connected between the word line boosting signal line and the word line and having a gate connected to the boot strap node, and connected between the pull-up signal input node and the first node to gate the pull-up signal. And a switching element to which a generated signal is applied, and a pull-down transistor of a diode structure whose source is connected to one end of the switching element and its drain is connected to the word line.

1 is a circuit diagram of a sub row decoder using a conventional N-MOS transistor.

2 is a circuit diagram of a sub row decoder according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: metal line MN6: switching element

MN1 to MN4: Bootstrap Transistors

MN2 ~ MN5: Pull-up Transistors

MN3-MN7: Pull-Down Transistors

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a circuit diagram of a sub row decoder according to an embodiment of the present invention, in which a bootstrap transistor is connected between a pull-up signal input node N3 and a bootstrap node N4 and a potential signal Vx is applied to a gate. A pull-up transistor MN5 connected between the MN4, a word line boosting signal px + 0 line, and a word line WL0, a gate of which is connected to the bootstrap node N4, and the pull-up signal; A sixth NMOS transistor MN6 connected between an input node N3 and a fifth node N5 and to which a signal obtained by inverting the pull-up signal is applied to a gate; the fifth node N5 and the word line; And a pull-down transistor MN7 connected in a diode structure between (WL0).

Looking at the process of the word line is selected and the high potential (Vpp) is transferred, first, the output node (N3) of the main row decoder selected by the input address signal becomes the power supply potential (Vcc), the gate of the bootstrap transistor (MN4) When the potential is the power source potential Vcc, a potential of Vcc-Vtn (the threshold potential of the bootstrap transistor MN4) is transferred to the bootstrap node N4.

Subsequently, if px + 0 is selected by the high potential transfer decoder (not shown) in the case where the potential Vpp to enable the word line is transmitted to one of the high potential transfer signals PX + i of the decoder. , between the high potential transfer node (px + 0) of the pull-up transistor (MN5) and the gate node (N4) as the potential of px + 0 transitions from the ground potential (Vss) to the word line enable potential (Vpp). Due to the capacitance present, the potential of the node N4, which was in the Vcc-Vtn potential, rises to a potential higher than the high potential (Vpp), thereby increasing the high potential (Vpp) of the high potential transfer node (pxi). Transfer to word line WL0.

On the other hand, when the main decoder is not selected, since the bootstrap node N4 is the ground potential Vss, the capacitance produced by the pull-up transistor MN5 of the decoder is small so that the bootstrap phenomenon does not occur. Even when the decoder is selected, when the high potential node pxi maintains the ground potential, the pull-up transistor MN5 is turned off so that the word line is not enabled. At this time, since the input signal node N3 is a case in which the main decoder is not selected, the input signal node N3 is 'logic low' to turn off the pull-up transistor MN5, but the inversion signal of the input signal is applied to the gate. The 6NMOS transistor MN6 is turned off so that the potential signal of the third node N3 as the pull-up signal and the potential signal of the fifth node N5 as the pull-down signal are the same. On the other hand, when the pull-up signal is 'logic high', the sixth NMOS transistor MN6 is turned off so that the pull-down signal of the fifth node N5 and the pull-down signal of the third node N3 are turned off. Are separated. In this case, a voltage lower than the substrate potential Vbb or the threshold potential −Vtn is applied to the pull-up signal to maintain the word line at a sufficiently low potential. In addition, when one word line is selected using an NMOS diode as the pull-down transistor MN7, the pull-down transistors connected to the other three word lines are turned off when the potential becomes a high voltage. Independent of each other, the other word lines remain 'logic low'.

The pull-up signal referred to in the present invention is a control signal of a pull-up and pull-down transistor for driving a word line and is an output signal of a row decoder circuit.

As described above, in the sub-loor decoder circuit of the present invention, a pull-up signal and a pull-down signal are generated in a standby state by connecting a source of a pull-down transistor, which is conventionally connected to a ground voltage, to a pull-up signal. By having the same potential as each other, even when the metal lines are shorted to each other, an increase in the standby current does not occur, and thus the yield can be improved since the operation normally occurs after a repair. In addition, since the sub-lode decoder circuit of the present invention is driven only by the NMOS, an additional well is not required and there is almost no increase in area.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

Claims (4)

A semiconductor memory device, comprising: a bootstrap transistor connected between a pull-up signal input node and a bootstrap node, and having a potential signal applied to a gate; a bootstrap transistor connected between a wordline boosting signal line and a wordline, and a gate of the bootstrap node; A switching device connected between the pull-up transistor connected to the pull-up signal input node and the first node, and a signal for inverting the pull-up signal to a gate applied thereto; And a pull-down transistor having a diode structure connected to the drain and its drain connected to the word line. 2. The sub row decoder circuit according to claim 1, wherein the bootstrap transistor, switching element, pull-up and pull-down transistors are N-MOS transistors. 2. The sub row decoder circuit according to claim 1, wherein the voltage is a substrate potential when the pull-up signal is 'logic low'. 2. The sub row decoder circuit of claim 1, wherein the voltage is less than a threshold potential when the pull-up signal is 'logic low'.