KR100486257B1 - Subword line drive signal generation circuit and method using the same - Google Patents

Abstract

A subword line drive signal generation circuit capable of reducing negative voltage fluctuations in a negatively biased word line structure and reducing noise caused by the negative voltage fluctuations is provided. A subword line driving signal generation circuit for providing a subword line driving signal to a corresponding sub word line driving circuit includes an input terminal for receiving a decoded signal; An output terminal for outputting the subword line driving signal; And a pull-down connected to the output terminal for pulling down the output terminal to a first voltage in response to the decoding signal or for pulling down the output terminal to a second voltage in response to a control signal and the decoding signal. And a control circuit is activated when the output terminal is pulled down to the first voltage. The first voltage is higher than the second voltage, the first voltage is a ground voltage, and the second voltage is a negative voltage.

Description

Subword line drive signal generation circuit and method using the same}

The present invention relates to a semiconductor memory device, and more particularly, to a subword line driving signal generation circuit and a subword line driving signal providing method for providing a subword line driving signal to a corresponding sub word line driving circuit.

1 shows a memory cell of a conventional DRAM device. The refresh time of the memory cell is reduced by two major leakage currents: junction leakage current I1 and sub-threshold current I2. Junction leakage current I1 is generated by defects in the junction boundary of transistor M1. The sub-threshold current I2 is a channel leakage current generated by the sub-threshold current I2 flowing through the transistor M1.

The junction leakage current I1 can be reduced by decreasing the ion concentration of the channel, but this causes the increase in the sub-threshold current I2. Similarly, the sub-threshold current I2 can be reduced by increasing the threshold voltage of the transistor M1, but this causes the junction leakage current I1 to increase.

The negatively biased wordline structure is designed to simultaneously reduce the junction leakage current (I1) and the sub-threshold current (I2). The memory device applying the negative word line structure supplies a negative voltage (VBB, typically -0.4 volts to -0.5 volts) to the word lines of unselected memory cells.

However, negatively biased wordline structures present several problems. First, during the precharge operation, a large capacity negative voltage source is required to handle the high discharge current generated when the word line is discharged from the boost voltage or the supply voltage to the negative voltage VBB. These discharge currents are likely to cause fluctuations in the negative voltage VBB.

The current required to operate the word line control circuit requires an additional negative voltage source. In other words, the negative voltage source is likely to occupy a large area in the memory device.

Second, conventional negatively biased wordline structures require a complex structure, which is typically disadvantageous in chip area since one negative wordline driver is required per wordline. Moreover, it is difficult to implement negative voltage converters in wordline driver pitch.

Accordingly, a technical problem of the present invention is to provide a subword line driving signal generation circuit capable of reducing a variation in negative voltage in a negatively biased word line structure and reducing noise generated by the variation in the negative voltage. It is.

A subword line driving signal generation circuit for providing a subword line driving signal to a corresponding sub word line driving circuit for achieving the technical problem comprises: an input terminal for receiving a decoded signal; An output terminal for outputting the subword line driving signal; And a pull-down connected to the output terminal for pulling down the output terminal to a first voltage in response to the decoding signal or for pulling down the output terminal to a second voltage in response to a control signal and the decoding signal. And a control circuit is activated when the output terminal is pulled down to the first voltage.

The first voltage is higher than the second voltage, the first voltage is a ground voltage, and the second voltage is a negative voltage.

The pull-down circuit includes a node; A first pull-down circuit connected to the output terminal and the node, for connecting the output terminal and the node in response to the decoding signal; A second pull-down circuit connected between the node and the first voltage and configured to pull down the node to the first voltage in response to a signal at the output terminal; And a third pull-down circuit connected between the output terminal and the second voltage, for pulling down the output terminal to the second voltage in response to the control signal and the decoding signal.

In addition, a subword line driving signal generation circuit for providing a subword line driving signal to a corresponding sub word line driving circuit according to the present invention includes an input terminal for receiving a decoded signal; An output terminal for outputting the subword line driving signal; A first current path formed between the output terminal and a first voltage in response to the decoded signal; And a second current path formed between the output terminal and a second voltage in response to a control signal and the decoding signal, wherein the output terminal is pulled down to the first voltage by the first current path. The second current path is formed in response to the activated control signal.

And a subword line driving signal generating circuit for providing a sub word line driving signal to a corresponding sub word line driving circuit according to the present invention. An output terminal for outputting the subword line driving signal; A first inverter for receiving the decoded signal; A second inverter for receiving the decoded signal; A pull-up circuit for pulling up the output terminal to a boosted voltage in response to an output signal of the first inverter; A first pull-down circuit for pulling down the output terminal to a first voltage in response to an output signal of the first inverter and a signal of the output terminal; And a second pull-down circuit for pulling down the output terminal to a second voltage in response to a control signal and an output signal of the second inverter.

A method of providing a subwordline drive signal to a corresponding subwordline driver circuit in accordance with the present invention comprises the steps of: receiving a decoded signal; And pulling down the subword line driving signal to a first voltage in response to the decoding signal, or pulling down the subword line driving signal to a second voltage in response to a control signal and the decoding signal. And when the subwordline driving signal is pulled down to the first voltage, the subwordline driving signal is pulled down to the second voltage in response to the activated control signal. The first voltage is a ground voltage, and the second voltage is a negative voltage.

A method of providing a subword line driving signal to a corresponding sub word line driving circuit by a sub word line driving signal generation circuit having an input terminal and an output terminal according to the present invention may include receiving a decoding signal through the input terminal. ; Forming a first current path between the output terminal and a first voltage in response to the decoded signal; And forming a second current path between the output terminal and the second voltage in response to a control signal and the decoding signal, wherein the output terminal is pulled down to the first voltage through the first current path. The second current path pulls down the output terminal to the second voltage in response to the activated control signal. Preferably, the first voltage is higher than the second voltage.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 illustrates a core structure of a DRAM device using a conventional sub-wordline driver structure. The core structure shown in FIG. 2 includes memory cell arrays ARRAY 32, sense amplifier blocks SAs, sub wordline blocks SWDs, a row decoder 38, and a connection region CONJUNCTION. . The connection area CONJUNCTION includes voltage generation circuits 30 and 40 (hereinafter, referred to as PXID generation circuits) for supplying a boosted voltage to the word line.

Within each memory cell array ARRAY are individual memory cells MC and a sub-wordline driver 36. Each memory cell MC has a cell transistor and a cell capacitor positioned at an intersection of a word line WL and a bit line BL / BLB.

The row decoder 38 receives and decodes the upper row addresses 2 to 8 to activate one word line enable signal among the word line enable signals WEI <i> where i is 0 to n. . Each activated word line enable signal WEI has a boosted voltage level VPP.

The decoding signal generation circuit 42 receives the lower row addresses 0 to 1 and decodes it to generate four decoding signals PXI (j>, where j is 0 to 3).

4 shows a conventional NMOS type sub-wordline driver, and FIG. 5 shows a conventional CMOS type sub-wordline driver. Here, PXIB is a signal having a phase opposite to that of the decoding signal PXI, and the activated decoding signal PXI has a boosted voltage VPP level. The WEIB is a signal having a phase opposite to that of the word line enable signal WEI.

Accordingly, the sub-wordline driver of FIGS. 4 and 5 drives the subwordline WL to the boosted voltage VPP level in response to the decoding signal PXI and the wordline enable signal WEI.

3 shows a conventional sub-word line driving signal generation circuit. Referring to FIG. 3, a sub-word line driving signal generating circuit (hereinafter referred to as a 'PXID generating circuit') includes a plurality of inverters 310, 320, and 330, two transistors 350 and 380, and a delay circuit. And 360 and 370.

The power supply voltage VCC has a high level as a supply voltage of the memory cell array. Transistor 340 has a small channel width. When the decoding signal PXI transitions from low to high, the output signal PXID of the inverter 320 has a boosted voltage VPP level. In this case, the subword line WL of FIGS. 4 and 5 also has a boosted voltage VPP level in response to the activated word line enable signal WEI.

When the decoding signal PXI transitions from high to low, since the output terminal of the inverter 320 has a large parasitic capacitance, the output signal PXID of the inverter 320 gradually decreases from the high level to the low level. When the output signal PXID of the inverter 320 is greater than the threshold voltage of the transistor 350, most of the current at the output terminal of the inverter 320 is discharged to the ground power supply VSS through the transistor 350. do. At this time, the output terminal of the inverter 320 by the transistor 380 discharges a small current toward the negative voltage (VBB).

By the delay circuit 360 connected to the gate of the transistor 350, the current at the output terminal of the inverter 320 is grounded through the transistor 350 until the output voltage PXID of the inverter 320 becomes almost zero. Discharged to the power supply VSS. After the transistor 350 is turned off, the output signal of the inverter 320 or the voltage of the subword line WL of FIGS. 4 and 5 becomes the negative power supply VBB level through the transistor 380.

That is, when the power supply voltage VCC is low, since the voltage between the gate and the source of the transistor 380 is small, the current flowing through the transistor 380 does not have much influence on the variation of the negative voltage VBB.

However, when the power supply voltage VCC is high (e.g., the test mode), when the voltage between the gate and the source of the transistor 380 increases, the current flowing through the transistor 380 increases, so that the variation of the negative voltage VBB Increases. Therefore, the noise caused by the variation of the negative voltage VBB also increases.

6 illustrates a sub-word line driving signal generation circuit according to an embodiment of the present invention.

Referring to FIG. 6, the sub-word line driving signal generation circuit 30 for providing the subword line driving signal PXID to the corresponding sub word line driving circuit receives the decoding signal PXI input to the input terminal. An output terminal for outputting a subword line driving signal PXID, an output terminal for outputting a subword line driving signal PXID, and an output terminal of the inverter 610 in response to an output signal of the inverter 610, that is, a decoding signal PXI. A pull-down circuit for pulling down the output terminal to the second voltage VBB in response to the control signal PXID_CON and the output signal of the inverter 630, that is, the decoding signal PXI. 660 to 670), and when the output terminal is pulled down to the first voltage VSS, the control signal PXID_CON is activated. The first voltage VSS is a ground voltage and the second voltage VBB is a negative voltage. Therefore, the first voltage VSS is higher than the second voltage VBB.

The sub-word line driving signal generation circuit 30 includes a plurality of inverters 610, 620, and 630 and a plurality of transistors 650, 660, and 670. The sub-word line driving signal generation circuit further includes a delay circuit 640.

The inverter 610 includes a PMOS transistor 601 and an NMOS transistor 603. The decoding signal PXI is input to the gates of the PMOS transistor 601 and the NMOS transistor 603, and the PMOS transistor 601 is connected between the boost voltage VPP and the output terminal of the inverter 610, and the NMOS transistor 603. ) Is connected between the output terminal of the inverter 610 and the ground voltage (VSS). The inverter 610 outputs an output signal swinging between the boosted voltage VPP and the ground residual voltage VSS to the inverter 620 according to the state (eg, high or low) of the decoding signal PXI.

The inverter 620 includes a PMOS transistor 605 and an NMOS transistor 607. The output signal of the inverter 610 is input to the gates of the PMOS transistor 605 and the NMOS transistor 607, the PMOS transistor 605 is connected between the boosted voltage VPP and the output terminal of the inverter 620, and the NMOS transistor 607 is connected between the output terminal of the inverter 620 and the node 655. The NMOS transistor 607 connects the output terminal of the inverter 620 and the node 655 in response to the output signal of the inverter 610 having a boosted voltage (VPP) level.

The inverter 620 outputs an output signal PXID swinging between the boosted voltage VPP and the ground voltage VSS according to the state of the output signal of the inverter 610. That is, the PMOS transistor 605 pulls up the output signal PXID of the inverter 620 to the boosted voltage VPP. The output signal PXID of the inverter 620 is a driving signal for driving the sub-word line driver shown in FIG. 4 or 5.

The inverter 630 receives the decoding signal PXI and outputs the output signal PXIB swinging between the power supply voltage VCC and the negative voltage VBB according to the state of the decoding signal PXI in FIG. 4 or 5. Output to the sub-wordline driver shown. The output signal PXIB of the inverter 630 is a driving signal for driving the sub-word line driver.

The delay circuit 640 is connected between the output terminal of the inverter 620 and the gate of the transistor 650. Transistor 650 is connected between node 655 and ground voltage VSS. The transistor 650 pulls down the node 655 to the ground voltage VSS in response to the output signal PXID of the inverter 620.

Each of the transistors 607 and 650 has a first current between the output terminal of the inverter 620 and the ground voltage VSS in response to the output signal of the inverter 610 and the output signal of the inverter 620, that is, the decoding signal PXI. Form a pass.

The transistor 660 is connected between the output terminal of the inverter 620 and the node 665, and the control signal PXID_CON is input to the gate of the transistor 660. Transistor 670 is connected between node 665 and negative voltage VBB, and the gate of transistor 670 is connected to the output terminal of inverter 630. The NMOS transistors 660 and 670 pull down the output terminal of the inverter 620 to the negative voltage VBB in response to the control signal PXID_CON and the decoding signal PXI.

That is, the NMOS transistors 660 and 670 form a second current path between the output terminal of the inverter 620 and the negative voltage VBB in response to the control signal PXID_CON and the decoding signal PXI. The second current path is formed in response to the control signal PXID_CON activated when the output signal PXID of the inverter 620 is pulled down to the ground voltage VSS level by the first current path.

The output terminal of the inverter 620 of the server-word line driving signal generation circuit according to the present invention may be directly connected to the gate of the NMOS transistor 650. In this case, the metal line electrically connecting the output terminal of the inverter 620 and the gate of the NMOS transistor 650 has a function of the delay circuit 640, that is, a function of delaying the output signal PXID of the inverter 620 for a predetermined time. Perform.

FIG. 7 is a timing diagram of the sub-word line driving signal generation circuit shown in FIG. 6. The operation of the PXID generation circuit will be described in detail with reference to FIGS. 4, 6 and 7.

When the decoding signal PXI transitions from the low VBB to the high VPP, the subword line driving signal PXID transitions from the low to the high by the inverters 610 and 620. Accordingly, the subwordline WL of the sub-wordline driver of FIG. 4 or 5 is pulled up to the boosted voltage VPP level in response to the activated wordline enable signal WEI and the deactivated PXIB.

When the decoding signal PXI transitions from the high VPP to the low VBB, the control signal PXID_CON is low, so the transistor 660 is turned off. Therefore, no current flows to the transistor 670. The current at the output terminal of the inverter 620 flows to the ground power supply VSS only through the transistor 650. Since the parasitic capacitance of the output terminal of the inverter 620 is considerably large, the voltage of the output terminal of the inverter 620, that is, the subword line driving signal, decreases slowly.

The control signal PXID_CON is inactivated before the decoding signal PXI is activated, and is preferably activated after the decoding signal PXI is inactivated.

By the delay circuit 640 or by the metal line, the transistor 650 can remain turned on until the voltage level of the output signal PXID of the inverter 620 becomes almost the ground voltage VSS. The current of the output terminal of the inverter 620 or the current of the subword line WL is discharged to the ground voltage VSS through the transistor 650.

 When the transistor 650 is turned on in response to the subword line driving signal PXID having a nearly ground voltage VSS level, when the control signal PXID_CON is activated, the transistor 660 is turned on. Is turned on. Accordingly, since the subword line driving signal PXID is at the negative voltage VBB level through the transistors 660 and 670, the subword line WL of FIGS. 4 and 5 becomes the negative voltage VBB.

Accordingly, the transistor 660 of the PXID generating circuit according to the present invention is turned off regardless of the turn-on of the transistor 670 by the control signal PXID_CON. Therefore, when the power supply voltage VCC is higher than a predetermined reference, that is, even if the voltage between the gate and the source of the transistor 670 increases, the current flowing through the transistor 670 does not increase, and noise caused by the negative power supply VBB is also increased. It does not occur.

In addition, since the current flowing through the transistor 670 always flows only a voltage difference corresponding to the negative voltage VBB from the ground voltage VSS, the transistor 670 has only a constant current regardless of the power supply voltage VCC. Consume. Therefore, the noise due to the variation of the negative voltage VBB is considerably reduced.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the subword line driving signal generation circuit according to the present invention has the effect of reducing the variation of the negative voltage in the negatively biased word line structure and reducing the noise generated by the variation of the negative voltage.

In addition, when the negative voltage is stabilized, since the leakage current and the sub-threshold current of the memory cell are reduced, the refresh characteristic of the memory cell is improved.

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.

1 shows a memory cell of a conventional DRAM memory device.

2 illustrates a core structure of a DRAM device using a conventional sub-wordline driver structure.

3 shows a conventional subword line driving signal generation circuit.

4 shows a conventional NMOS type sub wordline driver.

Fig. 5 shows a conventional CMOS sub wordline driver.

6 illustrates a subword line driving signal generation circuit according to an exemplary embodiment of the present invention.

FIG. 7 is a timing diagram of the subword line driving signal generation circuit shown in FIG. 6.

Claims (11)

A subword line driving signal generation circuit for providing a subword line driving signal to a corresponding sub word line driving circuit, An input for receiving a decoded signal; An output terminal for outputting the subword line driving signal; And A pull-down circuit connected to the output terminal for pulling down the output terminal to a first voltage in response to the decoding signal or for pulling down the output terminal to a second voltage in response to a control signal and the decoding signal; Equipped with The pull-down circuit Node; A first pull-down circuit connected between the output terminal and the first voltage and pulling down the output terminal to the first voltage in response to the output terminal signal; A second pull-down circuit connected between the output terminal and the node and coupling the output terminal to the node in response to the control signal; And A third pull-down circuit connected between said node and said second voltage, for pulling down said node to said second voltage in response to said decoding signal, And the control signal is activated when the output terminal is pulled down to the first voltage. The sub word line driving signal generation circuit of claim 1, wherein the first voltage is higher than the second voltage. The sub word line driving signal generation circuit of claim 1, wherein the first voltage is a ground voltage, and the second voltage is a negative voltage. delete A subword line driving signal generation circuit for providing a subword line driving signal to a corresponding sub word line driving circuit, An input for receiving a decoded signal; An output terminal for outputting the subword line driving signal; A first current path formed between the output terminal and a first voltage in response to the decoded signal; And A second current path formed between the output terminal and a second voltage in response to a control signal and the decoded signal, And the second current path is formed in response to the activated control signal when the output terminal is pulled down to the first voltage by the first current path. 6. The subword line driving signal generation circuit of claim 5, wherein the first voltage is a ground voltage and the second voltage is a negative voltage. A subword line driving signal generation circuit for providing a subword line driving signal to a corresponding sub word line driving circuit, An input for receiving a decoded signal; An output terminal for outputting the subword line driving signal; A first inverter for receiving the decoded signal; A second inverter for receiving the decoded signal; A pull-up circuit for pulling up the output terminal to a boosted voltage in response to an output signal of the first inverter; A first pull-down circuit for pulling down the output terminal to a first voltage in response to an output signal of the first inverter and a signal of the output terminal; And And a second pull-down circuit for pulling down the output terminal to a second voltage in response to a control signal and an output signal of the second inverter. A method of providing a subword line driving signal to a corresponding sub word line driving circuit, Receiving a decoded signal; And Pulling down the subword line driving signal to a first voltage in response to the decoding signal, or pulling down the subword line driving signal to a second voltage in response to a control signal and the decoding signal; , And when the subword line driving signal is pulled down to the first voltage, the subword line driving signal is pulled down to the second voltage in response to the activated control signal. How to provide a signal. 10. The method of claim 8, wherein the first voltage is a ground voltage, and the second voltage is a negative voltage. A method of providing a subword line driving signal to a corresponding sub word line driving circuit through a sub word line driving signal generation circuit having an input terminal and an output terminal, the method comprising: Receiving a decoded signal through the input terminal; Forming a first current path between the output terminal and a first voltage in response to the decoded signal; And Forming a second current path between the output terminal and a second voltage in response to a control signal and the decoded signal, And when the output terminal is pulled down to the first voltage through the first current path, the second current path pulls down the output terminal to the second voltage in response to the activated control signal. Subword line driving signal providing method. The method of claim 10, wherein the first voltage is higher than the second voltage.