KR100314646B1 - Bootstrap circuit - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a bootstrap circuit.

2. The technical problem of the invention

It provides a bootstrap circuit that improves device reliability during read operations by reducing power dissipation and loss of bootstrapping voltage.

3. Summary of the Solution of the Invention

Means for raising the output node to a first potential, means for regulating the output to a first potential, and raising the output node to a second potential by supplying a power supply voltage by a different signal or by dropping to a ground potential; Means for configuring the bootstrap circuit.

Description

Bootstrap circuit

The present invention relates to a bootstrap circuit, and more particularly to a bootstrap circuit that can improve the reliability of the device during the read operation by reducing the power consumption and the consumption of the bootstrapping voltage.

In a low voltage flash memory device, a voltage higher than a power supply voltage must be applied to a word line in order to obtain a cell current necessary to secure an appropriate read margin. As such, the bootstrap circuit shown in FIG. 1 is used to apply a voltage higher than the power supply voltage to the word line.

1 is a circuit diagram of a conventional bootstrap circuit, and is configured as follows.

The first to fourth inverters I1, I2, I3, and I4 and the first capacitor C1, which is a boosting capacitor, between the input terminal to which the boosting voltage VBOOT is input to enable the bootstrapping operation and the first node Q1. ) Are connected in series. The diode D1 is connected between the power supply terminal and the first node Q1, and the second capacitor C2, which is a loading capacitor, is connected between the first node Q1 and the ground terminal V _SS .

The bootstrap circuit configured as described above is operated as follows.

First, when the boosting voltage VBOOT that enables the bootstrapping operation is input in the low state and is disabled, the power supply voltage V _CC is input through the diode D1 to enable the first node ( Q1) maintains the potential of the power supply voltage V _CC , thereby occupying the first and second capacitors C1 and C2. On the other hand, the boosting voltage VBOOT input in the low state becomes a low state which is delayed for a predetermined time through the first to fourth inverters I1, I2, I3, and I4 connected in series, and the potential becomes the first node ( Although applied to Q1), the first and second capacitors C1 and C2 maintain the potential of the power supply voltage V _CC .

The power supply voltage V _CC is input through the diode D1 so that the first node Q1 maintains the potential of the power supply voltage V _CC , which causes the first and second capacitors C1 and C2 to supply the power supply voltage. When the boosting voltage VBOOT is input in the state occupied by the potential of the VCC and the bootstrapping operation is enabled, the following operation is performed. The boosting voltage VBOOT input in the high state is delayed for a predetermined time through the first to fourth inverters I1, I2, I3, and I4 connected in series to become a high state, and the potential is first capacitor C1. Occupy). Therefore, a boosting voltage is applied to the first node Q1 that has maintained the potential of the power supply voltage V _CC , and thus the first node Q1 becomes a potential at which the boosting voltage is added to the power supply voltage V _CC . . The potential of the first node Q1 is supplied to the word line to perform a read operation.

However, in the conventional bootstrap circuit constructed and driven as described above, since the capacitance of the first capacitor C1 is set to be considerably large, the fourth inverter I4 for driving the same has a fairly large size. If the size of the fourth inverter I4 is large, a large short current flows when the circuit is driven, thereby increasing power consumption. In addition, since the junction capacitance of the second capacitor C2 is considerably large, unwanted charge sharing occurs between the first capacitor C1 and the second capacitor C2, resulting in loss of bootstrapping voltage. Problem is caused. Accordingly, the bootstrapping voltage is applied to the word line less than the desired voltage, which may adversely affect the operation of the device.

Accordingly, an object of the present invention is to provide a bootstrap circuit that can improve the reliability of a device during a read operation by reducing power consumption and loss of bootstrapping voltage.

1 is a circuit diagram of a conventional bootstrap circuit.

2 is a circuit diagram of a bootstrap circuit in accordance with the present invention.

3 is an output waveform diagram of each part of FIG. 2;

<Description of the symbols for the main parts of the drawings>

I1 to I4: first to fourth inverters

C1 and C2: first and second capacitor

D1: diode Q1: first node

I11 to I14: first to fourth inverters

11 and 12: first and second NAND gate

13: latch circuit

C11 to C13: first to third capacitors

P11 to P13; First to third PMOS transistors

N11 to N14; First to fourth NMOS transistors

D11 and D12: first and second diode

Q11 to Q15: first to fifth nodes

In order to achieve the above object, the present invention includes: first means connected to a power supply terminal for precharging an output node to a first potential; A first logic gate for combining the first signal and its inverted signal with the second signal; Second means for delaying an output signal of the first logic gate for a predetermined time; A second logic gate for combining the first signal and its inverted signal with a third signal output from the second means; Third means for outputting a fourth signal in accordance with an output signal of said second logic gate and an inverted signal thereof; And a fourth means for outputting a second potential to the output node in accordance with the fourth signal and for outputting the second signal.

The present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of a bootstrap circuit according to the present invention and is configured as follows.

The first diode D11 is connected between the power supply terminal and the first node Q11, and the third capacitor C13, which is a loading capacitor, is connected between the first node Q11 and the ground terminal V _SS . The first NAND gate 11 receives the boosting voltage VBOOT and the potential of the fifth node Q15 as inputs, respectively. The first capacitor C11 is connected between the output terminal of the first NAND gate 11 and the ground terminal V _SS . The first and second inverters I11 and I12 are connected in series with the output of the first NAND gate 11. The second NAND gate 12 inputs the output of the second inverter I12 and the boosting voltage VBOOT, respectively. The output of the second NAND gate 12 is connected to the gates of the second NMOS transistor N12 and the third PMOS transistor P13, respectively, and the output of the second NAND gate 12 is connected through the third inverter I13. Inverted and connected to the gate of the first NMOS transistor N11. The first NMOS transistor N11 is connected between the second node Q12 of the latch circuit 13 and the ground terminal V _SS , and the second NMOS transistor N12 is connected to the third node of the latch circuit 13 ( Q13) and the ground terminal (V _SS ) are connected. In the latch circuit 13 connected between the first node Q11 and the contact terminal V _SS , the first PMOS transistor P11 and the second node Q12 having the third node Q13 connected to the gate are connected to each other. The second PMOS transistors P12 connected to each other are cross-connected and each of the first and second NMOS transistors N11 and N12 connected to the ground terminal V _SS . In the third PMOS transistor P13, an output terminal of the second NAND gate 12 is connected with the gate and is connected between the power supply terminal and the fourth node Q14. The third NMOS transistor N13 having the third node Q13 connected to the gate is connected between the fourth node Q14 and the fifth node Q15. The fourth NMOS transistor N14 having the fourth inverter I14 connected to the gate is connected between the fifth node Q15 and the ground terminal V _SS . The potential of the first node Q11 through the first diode D11 and the potential of the fourth node Q14 through the second diode D12 are added to occupy the second capacitor C12 which is a boosting capacitor.

The driving method of the bootstrap circuit according to the present invention configured as described above will be described with reference to the waveform diagram of FIG. 3.

The power supply voltage V _CC is input through the first diode D11 so that the first node Q11 maintains the potential of the power supply voltage V _CC , and the potential of the first node Q11 is the second capacitor. Accounted for (C12).

In this state, when the low boosting voltage VBOOT for disabling the bootstrapping operation is input to one input terminal of the first NAND gate 11, a high state signal is output. The output signal of the first NAND gate 11 in the high state occupies the first capacitor C11 and is delayed for a time set by the first and second inverters I11 and I12. The high state signal and the low boosting voltage VBOOT that are delayed for a predetermined time are input to the second NAND gate 12 to output a high state signal. The second NMOS transistor N12 is turned on by the output signal of the second NAND gate 12 in the high state, and the first NMOS transistor N11 is turned on by the signal inverted to the low state through the third inverter I13. Is turned off. Accordingly, the potential of the third node Q13 of the latch circuit 13 is turned low to turn on the first PMOS transistor P11, and the potential of the second node Q12 is turned high so that the second PMOS transistor ( Turn off P12). The third NMOS transistor N13 is turned off by the potential of the third node Q13 in the low state, and the third PMOS transistor P13 is turned off by the output signal of the second NAND gate 12 in the high state. As a result, the fourth node Q14 maintains the potential of the low state. On the other hand, the boosting voltage VBOOT in the low state is inverted to the high state through the fourth inverter I14 to turn on the fourth NMOS transistor N14 so that the fifth node Q15 is in the low state. The potential of the fifth node Q15 in the low state is fed back to be input to one input terminal of the first NAND gate 11, and the potential of the fourth node Q14 in the low state is passed through the second diode D12. Since it does not occupy the second capacitor C12, the first node Q11 maintains a potential of the power supply voltage V _CC , which is supplied to the word line through the output terminal OUT but does not perform a read operation. It cannot be done.

As described above, while the first node Q11 maintains the potential of the power supply voltage V _CC to occupy the second capacitor C12, the boosting voltage VBOOT transitions from a low state to a high state to perform a bootstrapping operation. When enabled, it works as follows.

The boosting voltage VBOOT in the high state and the potential of the fifth node Q15 in the low state are input to the first NAND gate 11 to output a high state signal. The output signal of the first NAND gate 11 in the high state occupies the first capacitor C11 and is delayed for a predetermined time through the first and second inverters I11 and I12 to the second NAND gate 12. Is entered. The second NAND gate 12 receives a high state signal and a high boosting voltage VBOOT that are delayed for a predetermined time and output a low state signal.

The second NMOS transistor N12 is turned off by the output signal of the second NAND gate 12 in the low state and the first NMOS transistor N11 by the signal inverted to the high state through the third inverter I13. Is turned on. Accordingly, the potential of the third node Q13 of the latch circuit 13 is turned high to turn off the first PMOS transistor P11, and the potential of the second node Q12 is turned low to make the second PMOS transistor low. Turn on (P12). The third NMOS transistor N13 is turned on by the potential of the third node Q13 in the high state, and the third PMOS transistor P13 is turned on by the output signal of the second NAND gate 12 in the low state to supply power. Since the voltage V _CC is supplied, the fourth node Q14 maintains the potential of the high state. On the other hand, the high control signal VBOOT is inverted to the low state through the fourth inverter I14 to turn off the fourth NMOS transistor N14 so that the fifth node Q15 is in the high state. However, the potential of the fifth node Q15, which is turned high through the third PMOS transistor P13 and the third NMOS transistor N13, drops as much as the threshold voltage V _T of the two transistors at the power supply voltage V _CC . To become a potential. Thus, the high state potential through the second diode D12 is supplied to the fifth node Q15 to restore this potential to the complete power supply voltage. The potential of the fifth node Q15 in the high state is fed back to be input to one input terminal of the first NAND gate 11, and the potential of the fourth node Q14 in the high state is passed through the second diode D12. The second capacitor C12 is occupied. Therefore, the second capacitor C13 maintains the potential of twice the power supply voltage. Since the potential is output to the output terminal OUT and supplied to the word line, a read operation is performed.

The bootstrap circuit according to the present invention constructed and operated as described above has the following features.

First, when the control signal VBOOT is applied in a high state, since the third PMOS transistor P13 is turned on and the power supply voltage V _CC is supplied, the fourth node Q14 applies a potential of the power supply voltage V _CC . Will be maintained. This potential is charged to the second capacitor C12 through the second diode D12. Accordingly, charge sharing is generated between the second capacitor C12 and the third capacitor C13. However, the fourth node Q14 is supplied with a potential lowered by the built-in potential of the PN junction at the power supply voltage V _CC . The following method is used to compensate for the potential lowered by this internal diffusion potential. Since the voltage rise due to charge sharing occurs at the first node Q11 occupied by the potential of the power supply voltage, the voltage of this node is connected to the third NMOS transistor N13 using the latch circuit 13. Accordingly, the charge of the fourth node Q14 can be transferred to the fifth node Q15 without a voltage drop, and the loss of the internal diffusion potential of the previously generated second diode D12 can be completely compensated. have.

On the other hand, the third PMOS transistor P13 can be turned off again by controlling the input terminal used for enabling the feedback of the potential of the fifth node Q15. Accordingly, the third PMOS transistor P13 and the fourth NMOS transistor N14 may be controlled so that no current path occurs between the power supply voltage V _CC and the ground voltage V _SS at both the enable and the disable. have.

In addition, the junction capacitance of the third PMOS transistor P13, which is significantly larger in size, may be separated from the second capacitor C12 by the second diode D12, and a large size may drive a large amount of current even with a small size. Therefore, unwanted sharing of charge with the second capacitor C12 can be suppressed as much as possible.

For reference, in FIG. 3, reference numeral Q11 denotes a potential of the first node, Q13 denotes a potential of the third node, Q14 denotes a potential of the fourth node, Q15 denotes a potential of the fifth node, WL denotes a voltage supplied to the word line, and OUT. Denotes the output voltage, respectively.

As described above, according to the present invention, power loss due to a short circuit current can be reduced, and charge sharing between the first and second capacitors can be prevented, so that the loss of the boosting voltage can be prevented.

Claims (5)

First means connected to a power supply terminal for precharging the output node to a first potential; A first logic gate for combining the first signal and its inverted signal with the second signal; Second means for delaying an output signal of the first logic gate for a predetermined time; A second logic gate for combining the first signal and its inverted signal with a third signal output from the second means; Third means for outputting a fourth signal in accordance with an output signal of said second logic gate and an inverted signal thereof; And a fourth means for outputting a second potential to said output node in accordance with said fourth signal and for outputting said second signal. The method of claim 1, And said first means comprises a first diode. The method of claim 1, And the second means comprises an NMOS transistor between the output terminal of the first logic gate and the first and second inverters in series, and between the output terminal of the first logic gate and the ground terminal. The method of claim 1, The third means includes a third inverter connected to an output terminal of the second logic gate; A first NMOS transistor connected between an output terminal of the third inverter and a first node and a ground terminal; A first PMOS transistor connected to said first output node and said first node; A second PMOS transistor cross-connected with said first PMOS transistor and connected between said output node and a second node; And a second NMOS transistor connected between the second node and the ground terminal. The method of claim 1, The fourth means includes: a third PMOS transistor for supplying the power supply voltage to a third node in accordance with an output signal of the second logic gate; A third NMOS transistor for supplying the power supply voltage to a fourth node via the third PMOS transistor in accordance with the fourth signal; A fourth NMOS transistor for supplying ground power to the fourth node according to an output signal of a fourth inverter to which the first signal and its inverted signal are directly input; A second diode connected between the third node and a fourth node; And a capacitor connected between said second diode and an output node.