KR100293634B1 - Erasing control circuit for flash memory device - Google Patents

Abstract

PURPOSE: An erasing control circuit for flash memory device is provided to reduce a peak current caused by a band-to-band tunneling generated at a drain and a floating gate when many cells are simultaneously removed by an F-N tunneling. CONSTITUTION: An inverter(11) receives a pumping voltage and a second erasing signal. A logic part(12-15) receives a block selection signal and a first erasing signal(BLOCK_A). A buffer(16-19) outputs first and second output signals according to an output signal of the logic part, the pumping voltage, and an output signal of the inverter. A first switch transmits a power voltage to a cell block according to a second output signal of the buffer, and maintains a status prior to erasing action. A second switch transmits a voltage lowered by a predetermined voltage from the power voltage according to the second erasing signal, and performs a weak erasing action. A third switch transmits the pumping voltage to the cell block according to a first output signal of the buffer, and performs a normal erasing action.

Description

Erase Control Circuit of Flash Memory Device

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an erase control circuit for reducing peak current of a high density flash memory device, in particular by fowl tunneling a large number of cells in a flash memory device. An erase control circuit for reducing peak current of a flash memory device that can stabilize chip operation by minimizing peak current due to band-to-band tunneling occurring at the drain and the floating gate during erasing. It is about.

In a conventional low density flash memory device, the peak current due to band-to-band tunneling generated in the drain can be reduced by simply controlling the bias circuit applied to the drain of the cell.

However, as the cell density increases, the cell is divided into blocks and erase operations are performed at once as shown in FIG. 1. In this case, some band-to-band tunneling is generated even in the block in which the erase operation is not performed. As a result, the peak current is generated, so that the total peak current increases as the cell density increases, resulting in unstable chip operation.

Accordingly, the present invention provides a flash memory device capable of stabilizing the overall chip operation by eliminating the peak current generated in the block in which the erase operation is not performed by simultaneously controlling the block in which the erase operation is performed and the block in which the erase operation is not performed. It is an object of the present invention to provide a control circuit for reducing peak current in an erase operation in a block unit.

The present invention for achieving the above object is an inverter means to which the pumping voltage and the second erase signal is input, logic means to which the block selection signal and the first erase signal are input, output signal, pumping voltage and inverter of the logic means. Buffer means for outputting first and second output signals in accordance with the output signal of the means, and a power supply voltage to the cell block in accordance with the second output signal of the buffer means to maintain the state before the erase operation is performed. A first switch means for performing a weak erase operation by applying a voltage, which is a constant voltage decreased from a power supply voltage, to the cell block according to the second erase signal, and a first output of the buffer means. A third switch means for causing the pumping voltage to be applied to the cell block in response to a signal to perform a normal erase operation; Luer jidoe, said logic means, and buffer means, the first switching means, second switching means and the third switching means is characterized in that each configuration by the number of cell blocks.

1 is a block diagram illustrating an example of a flash memory device divided into blocks;

2 is a circuit diagram of an erase control circuit for reducing peak current of a flash memory device according to the present invention;

3 is a detailed circuit diagram of the high voltage inverter used in FIG.

4 is a detailed circuit diagram of a high voltage buffer used in FIG.

<Description of the symbols for the main parts of the drawings>

A1 and A2: first and second nodes of the first block

B1 and B2: first and second nodes of the second block

C1 and C2: first and second nodes of the third block

D1 and D2: first and second nodes of the fourth block

11: high voltage inverter means

12 to 15: first to fourth NAND gates

16 to 19: first to fourth high voltage buffer means

P1 to P8: first to eighth PMOS transistors

N1 to N4: first to fourth NMOS transistors

P11: PMOS transistor of high voltage inverter means

N11: NMOS transistor of high voltage inverter means

I11 to I13: first to third inverters of the inverter means for high voltage

P21: PMOS transistor of high voltage buffer means

N21: NMOS transistor of high voltage buffer means

I21 to I23: first to third inverters of high voltage buffer means

21: NOR gate of high voltage buffer means

The present invention will be described in detail with reference to the accompanying drawings.

2 is a control circuit diagram for reducing peak current of a flash memory device according to an exemplary embodiment of the present invention. When the cell of the flash memory device is divided into a plurality of blocks, only four blocks will be described as an example.

In the present invention, a weak erase operation is first performed to remove peak current due to band-to-band tunneling that occurs when a normal erase operation is performed at a time, and then normal erase operation is performed again.

A method of operating a control circuit for reducing peak current of a flash memory device according to the present invention will be described below.

The first erase signal ERASE maintains a high state when the erase operation is performed and maintains a low state when the erase operation is not performed. Each block selection signal, that is, a first block selection (BLOCK_A) signal, a second block selection (BLOCK_B) signal, a third block selection (BLOCK_C) signal, and a fourth block selection (BLOCK_D) signal are corresponding blocks for performing an erase operation. If it is selected, it is kept high, otherwise it is kept low. In addition, the second erase signal WEAK_ERASE for weakly performing the erase operation is maintained in a high state when the weak erase operation is performed, and is maintained in a low state when performing the normal erase operation and when the erase operation is not performed. . In addition, the pumping voltage (V _CC + V _T ) is a high state signal pumped to a potential higher than the power supply voltage.

First, the driving method of the high voltage inverter means 11 and the high voltage buffer means 16 to 19 applied to the circuit according to the present invention will be described.

As shown in FIG. 3, the high voltage inverter means 11 receives a second erase signal at the first input terminal IN and a pumping voltage at the second input terminal VVCP. The second erase signal input to the first input terminal IN maintains a high state when performing a weak erase operation, and maintains a low state when not performing an erase operation and when performing a normal erase operation.

The low state signal is input to the first input terminal IN, and the low state signal is inverted to the high state through the first inverter I11. The power supply voltage V _CC is supplied to the gate, and the high signal passing through the NMOS transistor N11 which is always turned on is inverted to the low state through the second inverter I12. The low state signal inverted through the second inverter I12 is applied to the gate of the PMOS transistor P11 to turn on the PMOS transistor P11. The pumping voltage input through the turned-on PMOS transistor P11 through the second input terminal VVCP is supplied to the first node K11 so that the potential of the first node K11 is increased to the same potential as the pumping voltage. The signal inverted to the low state through the second inverter I12 is inverted to the high state through the third inverter I13 and output. However, since the pumping voltage is supplied to the second inverter I12 and the third inverter I13, the high state signal output to the output terminal OUT maintains the potential of the pumping voltage. That is, a low state signal is input to the first input terminal IN, and a high state signal is output to the output terminal OUT at the potential of the pumping voltage.

The high state signal is input to the first input terminal IN, and the high state signal is inverted to the low state through the first inverter I11. The power supply voltage V _CC is supplied to the gate, and the low signal passing through the NMOS transistor N11 in the turned-on state is inverted to the high state through the second inverter I12. The high state signal inverted through the second inverter I12 is applied to the gate of the PMOS transistor P11 to turn off the PMOS transistor P11 so that the potential of the first node K11 remains low. The signal inverted to the high state through the second inverter I12 is inverted to the low state through the third inverter I13 and output to the output terminal OUT 1. However, although the pumping voltage is supplied to the second inverter I12 and the third inverter I13, the pumping voltage does not affect the output signal because the signal output to the output terminal OUT is low.

As described above, the high voltage inverter means 11 outputs a pumping voltage when a low state signal is input to the first input terminal, and outputs a low state signal when a high state signal is input.

The high voltage buffer means 16 to 19 are high voltage buffers having a disable function, and as shown in FIG. 4, the block select signal and the first erase signal are transmitted to the first input terminal IN by the NAND gate. A logically combined signal is input, a pumping voltage is input to the second input terminal VVCP, and the third input terminal DISb is an output terminal of the high voltage inverter means 11 as a disable terminal.

A circuit driving method when the signal input to the third input terminal DISb is kept high and the signal input to the first input terminal IN is high will be described.

The high state signal is input and inverted to the low state through the first inverter I21. The low voltage signal is input to the second inverter I22 through the NMOS transistor N21 which is supplied with a power supply voltage V _CC to the gate and is always turned on. The signal in the low state is inverted to the high state through the second inverter I22. A high state signal is applied to the gate of the PMOS transistor P21 to turn off the PMOS transistor P21 so that the state of the first node K21 is kept low. The signal inverted to the high state through the second inverter I22 is inverted to the low state through the third inverter I23 and input to the NAND gate 21. The NAND gate 21 receives the signal inverted to the low state through the third inverter I23 and the signal of the high state input to the third input terminal DISb as inputs, and sends the high state signal to the first output terminal OUT. Output However, since the pumping voltage is supplied to the PMOS transistor P21, the second inverter I22, the third inverter I23, and the NAND gate 21, a high state signal output to the first output terminal OUT is pumped. The potential of the voltage is maintained. On the other hand, the signal of the low state inverted through the third inverter I24 is output to the second output terminal OUTb.

A driving method of the circuit when the signal input to the third input terminal DISb is kept high and the signal input to the first input terminal IN is low will be described.

The low state signal is input and inverted to the high state through the first inverter I21. A signal having a high state is input to the second inverter I22 through an NMOS transistor N21 which is supplied with a power supply voltage V _CC to the gate and is always turned on. The signal in the high state is inverted to the low state through the second inverter I22. Since the signal in the low state is applied to the gate of the PMOS transistor P21 and turns on the PMOS transistor P21 to supply the pumping voltage to the first node K21, the first node K21 maintains the potential of the pumping voltage high. Is kept in a state. The signal inverted to the low state through the second inverter I22 is inverted to the high state through the third inverter I23 and input to the NAND gate 21. The NAND gate 21 receives the signal inverted to the high state through the third inverter I23 and the signal of the high state inputted to the third input terminal DISb to input the low state signal to the first output terminal OUT. Output Meanwhile, a signal inverted to the high state through the third inverter I23 is output to the second output terminal OUTb.

In addition, when a signal having a low state is input to the third input terminal DISb, the signal of the third input / output terminal is input to the NAND gate 21, and thus, regardless of the signal input to the first input terminal IN, the first output terminal ( OUT) outputs a high state signal that maintains the potential of the pumping voltage, and when a high state signal is input to the second output terminal OUTb, a low state signal is output, and a low state signal is input. A high state signal is output.

As described above, the high voltage buffer means 16 to 19 pump to the first output terminal OUT when the input signal of the third input terminal DISb is high and the input signal of the first input terminal IN is high. A voltage is output and a low signal is output to the second output terminal OUTb. When the input signal of the third input terminal DISb is high and the input signal of the first input terminal IN is low, the low output signal is output to the first output terminal OUT, and the second output terminal OUTb is output. Outputs the pumping voltage. In addition, when the input signal of the third input terminal DISb is in a low state, the pumping voltage is output to the first output terminal OUT and the second output terminal OUTb regardless of the state of the input signal of the first input terminal IN. When a high state signal is input, a low state signal is output. When a low state signal is input, a high state signal is output.

Now, a case of selecting and erasing a first block in the method of driving a circuit according to the present invention will be described as an example.

The first erase signal, the block select signal, and the second erase signal all remain low when the erase operation is maintained before being idle, that is, when the erase operation is not performed in the erase mode. .

The second erase signal in the low state and the voltage V _CC + V _T pumped to a potential higher than the power supply voltage V _CC are input to the first and second input terminals IN and VCVP of the high voltage inverter means 11. The signal of the high state which maintains the electric potential of a pumping voltage is output.

On the other hand, the first block selection (BLOCK_A) signal and the first erase (ERASE) signal in the low state are input to the first NAND gate 12 to output a high state signal.

A high state signal output from the first NAND gate 12 is input to the first input terminal IN of the first high voltage buffer means 16, and a pumping voltage is input to the second input terminal VVCP. A high state signal having a potential of the pumping voltage output through the high voltage inverter means 11 is input to the input terminal DISb, and a high state signal having a potential of the pumping voltage is output to the first output terminal OUT. A low state signal is output to the second output terminal OUTb.

The high state signal output to the first output terminal OUT of the first high voltage buffer means 16 acts as a first switch means and is applied to the gate of the first PMOS transistor P1 to which the pumping voltage is applied and thus the first signal. The PMOS transistor P1 is turned off, and the output signal of the second output terminal OUTb in the low state serves as a second switch means to be applied to the gate of the second PMOS transistor P2 to which a power supply voltage is applied to the second PMOS. The transistor P2 is turned on. Meanwhile, the second erase signal in the low state is applied to the gate of the first NMOS transistor N1 serving as the third switch means to turn off the first NMOS transistor N1. Therefore, the potential of the first node A1 to which the first and second PMOS transistors P1 and P2 and the first NMOS transistor N1 are connected is supplied with a power supply voltage by the turned-on second PMOS transistor P2. The potential of the voltage is maintained. The first node A1, which maintains the potential of the power supply voltage, is applied to the gate of the first NMOS transistor N10 that applies the power supply voltage to the first block BLOCK_A of FIG. 1 to turn on the first NMOS transistor N10. Thus, the potential of the second node A2 becomes a voltage (V _CC -V _T ) lowered by the threshold voltage of the first NMOS transistor.

Now, the circuit driving in the case of performing the erase operation will be described.

First, when the first block is selected and a weak erase operation is performed, that is, the first erase signal, the first block selection (BLOCK_A) signal, and the second erase signal are all maintained in a high state, and thus a weak erase operation is performed on the first block. The circuit driving in the case of performing will be described as follows.

The second erase signal in the high state and the voltage V _CC + V _T pumped to a potential higher than the power supply voltage V _CC are input to the first and second input terminals IN and VCVP of the high voltage inverter means 11. Signal is outputted.

On the other hand, the first block select (BLOCK_A) signal and the first erase (ERASE) signal in a high state are input to the first NAND gate 12 to output a low state signal.

A low state signal output from the first NAND gate 12 is input to the first input terminal IN of the first high voltage buffer means 16, a pumping voltage is input to the second input terminal VVCP, and a third A low state signal output through the high voltage inverter means 11 is input to the input terminal DISb, and a high state signal is output to the first output terminal OUT regardless of the signal input to the first input terminal. Since a low state signal is input to the first input terminal to the output terminal OUTb, a high state signal is output. At this time, the high state signals output to the first and second output terminals have a potential of a pumping voltage.

A high state signal output to the first output terminal OUT of the first high voltage buffer means 16 is applied to the gate of the first PMOS transistor P1 to turn off the first PMOS transistor P1, and the second The high state signal output to the output terminal OUTb is applied to the gate of the second PMOS transistor P2 to which the power supply voltage is applied to turn on the second PMOS transistor P2. Meanwhile, the second erase signal in the high state is applied to the gate of the first NMOS transistor N1 to which the power supply voltage is applied, thereby turning on the first NMOS transistor N1.

Therefore, a power supply voltage is applied to the potential of the first node A1 to which the first and second PMOS transistors P1 and P2 and the first NMOS transistor N1 are connected by the turned-on first NMOS transistor N1. A potential lowered by the threshold voltage of the first NMOS transistor N1 at the power supply voltage (V _CC -V _T ) is maintained.

The first node A1, which maintains the potential of V _CC -V _T , is applied to the gate of the first NMOS transistor N10 that applies a power supply voltage to the first block BLOCK_A of FIG. 1, so that the first NMOS transistor N10. ) Is turned on so that the potential of the second node A2 becomes the voltage V _CC -2V _T lowered by the threshold voltage of the first NMOS transistor N10. Thus, the drain of the cell when performing an erase operation is the potential has a value of V _CC -2V _T of the second node (A2) comes to have a low peak current at V _CC -2V _T.

When the first block is selected to perform a normal erase operation, that is, the circuit driving when the first erase signal and the first block select signal BLOCK_A remain high and the second erase signal remains low will be described. Is as follows.

The second erase signal in the low state and the voltage V _CC + V _T pumped to a potential higher than the power supply voltage V _CC are input to the first and second input terminals IN and VCVP of the high voltage inverter means 11. A signal in a high state having a potential of the pumping voltage is output.

On the other hand, the first block select (BLOCK_A) signal and the first erase (ERASE) signal in a high state are input to the first NAND gate 12 to output a low state signal.

A low state signal output from the first NAND gate 12 is input to the first input terminal IN of the first high voltage buffer means 16, a pumping voltage is input to the second input terminal VVCP, and a third The high state signal having the potential of the pumping voltage outputted through the high voltage inverter means 11 is input to the input terminal DISb, and the low state signal is output to the first output terminal OUT, and the second output terminal OUTb is output. This outputs a high state signal having a potential of the pumping voltage.

The low-state signal output to the first output terminal OUT of the first high voltage buffer means 16 is applied to the gate of the first PMOS transistor P1 for applying the pumping voltage to the first PMOS transistor P1. The signal of the low state which is turned on and output to the second output terminal OUTb is applied to the gate of the second PMOS transistor P2 for applying the power supply voltage to turn off the second PMOS transistor P2. On the other hand, the second erase signal in the low state is applied to the gate of the first NMOS transistor N1 for applying the power supply voltage to turn off the first NMOS transistor N1.

Therefore, the potential of the first node A1 to which the first and second PMOS transistors P1 and P2 and the first NMOS transistor N1 are connected is pumped by applying a pumping voltage by the turned-on first PMOS transistor P1. The potential of the voltage is maintained. The first node A1, which maintains the potential of the pumping voltage, is applied to the gate of the first NMOS transistor N10 that applies the power voltage to the first block BLOCK_A of FIG. 1 to turn on the first NMOS transistor N10. As a result, the potential of the second node A2 has a potential of the power supply voltage V _CC , and the drain of the cell performs an erase operation at the potential of the power supply voltage. Therefore, the normal erase operation is performed after the peak current is reduced.

After the erase operation is completed for the first block, the erase operation is performed in the same manner for the remaining blocks.

When the erase operation performed as described above is applied to each block of FIG. 1, the potential of each node is shown in [Table 1].

As shown in Table 1, when the erase operation is performed weakly from the first block, the potential of the first node A1 is V _CC -V _T in the cell of the first block, and the second node is performed. The potential of (A2) is V _CC -2V _T. In the normal erase operation, the potential of the first node A1 is V _CC + V _T , and the potential of the second node A2 is V _CC . In addition, the potentials of the first nodes B1, C1, and D1 in the cells of the second, third, and fourth blocks in other modes in which the erase operation is not performed are V _CC , and the second nodes B2, C2, and The potential of D2) is V _CC -V _T. At this time, since the negative voltage due to the erase operation is not applied to the gate in the first, second and third blocks, the peak current due to the band-to-band tunneling does not flow.

In the above example, when the flash memory cell is divided into four blocks to perform a weak erase operation and then perform a normal erase operation, the peak current due to band-to-band tunneling can be reduced to 1/4.

Erase Command Erase Block Weak Erase Normal Erase A1 A2 B1 B2 C1 C2 D1 D2 No No No No V _CC V _CC -V _T V _CC V _CC -V _T V _CC V _CC -V _T V _CC V _CC -V _T Yes Block a Yes No V _CC -V _T V _CC -2V _T V _CC V _CC -V _T V _CC V _CC -V _T V _CC V _CC -V _T No Yes V _CC + V _T V _CC V _CC V _CC -V _T V _CC V _CC -V _T V _CC V _CC -V _T Block b Yes No V _CC V _CC -V _T V _CC -V _T V _CC -2V _T V _CC V _CC -V _T V _CC V _CC -V _T No Yes V _CC V _CC -V _T V _CC + V _T V _CC V _CC V _CC -V _T V _CC V _CC -V _T Block c Yes No V _CC V _CC -V _T V _CC V _CC -V _T V _CC -V _T V _CC -2V _T V _CC V _CC -V _T No Yes V _CC V _CC -V _T V _CC V _CC -V _T V _CC + V _T V _CC V _CC V _CC -V _T Block d Yes No V _CC V _CC -V _T V _CC V _CC -V _T V _CC V _CC -V _T V _CC -V _T V _CC -2V _T No Yes V _CC V _CC -V _T V _CC V _CC -V _T V _CC V _CC -V _T V _CC + V _T V _CC

As described above, according to the present invention, when performing an erase operation in a memory device with a high cell density, a weak erase operation is performed block by block, and then a normal erase operation is performed to effectively reduce peak current due to band-to-band tunneling. Can be.

Claims (2)

An inverter means to which a pumping voltage and a second erase signal are input; Logic means to which a block select signal and a first erase signal are input; Buffer means for outputting first and second output signals in accordance with the output signal of the logic means, the pumping voltage and the output signal of the inverter means; First switch means for applying a power supply voltage to the cell block according to a second output signal of the buffer means to maintain a state before an erase operation is performed; Second switch means for causing a weak erase operation to be performed by applying a voltage reduced in voltage from a power supply voltage to the cell block according to the second erase signal; And a third switch means for causing the pumping voltage to be applied to the cell block according to the first output signal of the buffer means to perform a normal erase operation, wherein the logic means, buffer means, first switch means, first And the second switch means and the third switch means are each configured by the number of cell blocks. A high voltage inverter means to which a pumping voltage and a second erase signal are input; A NAND gate to which a block select signal and a first erase signal are input; High voltage buffer means for outputting first and second output signals according to an output signal of the NAND gate, a pumping voltage and an output signal of a high voltage inverter means; A first PMOS transistor for applying a power supply voltage to the cell block according to a second output signal of the buffer means to maintain a state before an erase operation is performed; An NMOS transistor configured to apply a voltage reduced by a threshold voltage from a power supply voltage to the cell block according to the second erase signal to perform a weak erase operation; And a second PMOS transistor configured to perform the normal erase operation by applying the pumping voltage to the cell block according to the first output signal of the high voltage buffer means, wherein the NAND gate and the high voltage buffer means are provided. The PMOS transistor, the NMOS transistor and the second PMOS transistor are each configured by the number of cell blocks, the erase control circuit of the flash memory device.