KR100217918B1 - Flash memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device. The present invention relates to a flash memory device that can reduce program test time and reduce power consumption by enabling a program check operation in a flash memory cell program mode.

Description

Flash memory device

1 is a schematic circuit diagram illustrating a conventional flash memory device.

2 is a schematic circuit diagram of a flash memory device according to the present invention.

FIG. 3 is a voltage waveform diagram of a conventional time and a flash memory device according to the present invention.

* Explanation of symbols for main parts of the drawings

S / A: Sense Amplifier MC and MCr: Memory Cell

Ni, Nr, Nr1, Np: Pass Transistor

The present invention relates to a flash memory device, and more particularly, to a flash memory device that enables a program and a program check operation in a byte program mode of a flash memory cell.

In general, a flash memory is a memory device that realizes a bit storage state as one memory cell and can be electrically programmed and erased. A configuration of a conventional flash memory device for checking whether the flash memory cell is normally programmed after programming the flash memory cell is described below with reference to FIG.

The first pull-up resistor R1 is connected between the power supply terminal Vcc and the first node K1, and the Y decoder signal Yi is input between the first node K1 and the ground terminal Vss. The main memory cell MC having the one-pass transistor Ni and the word line Wi as an input is connected in series. Further, a second pull-up resistor R2 is connected between the power supply terminal Vcc and the second node K2, and a Y decoder signal Yr is input between the second node K2 and the ground terminal Vss. The dummy memory cell MCr, which receives the two-pass transistor Nr and the word line Wr, is connected in series. And a sense amplifier S / A for comparing the voltages of the first and second nodes K1 and K2.

The operation of the conventional flash memory device configured as described above will be described with reference to FIG. 3.

The time t2 shown in FIG. 3 represents the time required to switch from the program mode to the program check mode, the time count represents the time required for the program, the time tv represents the time required for the program check, and the time t3 is the program check mode. Indicates the time required to enter the program mode. The input signal P1 is supplied to the word line Wi of the main memory cell shown in FIG. 1, and the input signal P2 is supplied to the bit line Bi of the main memory cell. The program operation is performed on the main memory cell MC. Upon completion, the voltages of the first and second nodes K1 and K2 are compared, and the result is output through the sense amplifier S / A to output the output signal S1. In this case, the average period (T) required for the program and the program check operation is

Becomes

Therefore, there is a problem in that it takes a long time because the time t2 required to switch from the program mode to the program check mode and the time t3 required to call the program mode from the program check mode are required for the program and the program check operation.

Accordingly, an object of the present invention is to solve a conventional problem as described above, and to provide a flash memory device that enables a program check operation in a program mode of a flash memory cell.

The present invention for achieving the above object is connected between a memory cell operated according to a word line signal during programming, a drain voltage source and the memory cell, the voltage from the drain voltage source in accordance with a Y decoder signal to the memory cell A first pass transistor for supplying to a second pass transistor connected between the memory cell and the ground terminal, the second pass transistor being operated according to a program enable signal, and connected in series between the memory cell and the ground terminal, and having a program check-in A third fast transistor and a pull-down resistor for causing a potential between the memory cell and the second pass transistor to have a predetermined potential according to an enable signal, and the memory cell potential according to the program confirmation enable signal and a program enable signal. Sense amplifier for comparing and outputting reference voltage It is characterized by.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a schematic circuit diagram of a flash memory device according to the present invention. The configuration thereof is as follows.

The first pass transistor Ni is connected between the voltage source and the main memory cell MC to supply the drain voltage V _PD to the main memory cell MC during programming in accordance with the Y decoder signal Yi. The main memory cell MC is connected between the first pass transistor Ni and the node K3 and is programmed by a voltage supplied from the word line Wi. The third pass transistor Nr1 and the pull down resistor K3 are connected between the node K3 and the ground terminal Vss, and the third pass transistor Nr1 is operated according to the program confirmation enable signal Sr. . The second pass transistor Np is connected between the node K3 and the ground terminal Vss to operate according to the program enable signal Sp. The sense amplifier S / A compares the reference voltage Vref with the voltage of the main memory cell MC according to the program enable signal Sp and the program check enable signal Sr, and outputs the result.

The driving method of the flash memory device according to the present invention configured as described above is as follows.

First, during the program operation, the program check enable signal Sr goes low, and the program enable signal Sp goes high. Therefore, the first pass transistor Ni, which receives the Y decoder signal Yi, is turned on to supply the drain voltage V _PD during programming to the bit line Bi, and the gate voltage during programming to the word line Wi. V _PG ) is supplied. Accordingly, the main memory cell MC is programmed.

During the program check operation after the main memory cell MC is programmed, the program enable signal Sp goes low and the program check enable signal Sr goes high. That is, the second pass transistor Np, which receives the program enable signal Sp, is turned off, and the third pass transistor Nr1, which inputs the program confirm enable signal Sr, is turned on. At this time, the main memory cell MC is switched from the program mode to the program check mode, and the voltage applied to the selected word line Wi does not change. When the main memory cell MC is not sufficiently programmed, the node K3 voltage between the source electrode of the main memory cell MC and the drain electrode of the second pass transistor Np is the reference of the sense amplifier S / A. It becomes relatively higher than the voltage Vref. However, when the main memory cell MC is sufficiently programmed, the voltage of the node K3 becomes lower than the reference voltage Vref of the sense amplifier S / A. In this case, the sense amplifier S / A is enabled to compare the voltage of the node K3 with the reference voltage Vref, and output the result S1.

Therefore, the average period (T1) required for the program and program check operation is

Program test time saved per cycle (△ T)

Becomes

Therefore, the time t2 for switching from the program mode to the program check mode and the time t3 for switching from the program check mode to the program mode are shortened.

As described above, according to the present invention, by performing the program check operation of the flash memory cell in the program mode, the program test time can be reduced and the power consumption can be reduced.

Claims (3)

A first pass transistor connected between a memory cell operated according to a word line signal during programming, a drain voltage source and the memory cell, and for supplying a voltage from the drain voltage source to the memory cell according to a Y decoder signal; A second pass transistor connected between the memory cell and the ground terminal, the second pass transistor being operated according to a program enable signal, and connected in series between the memory cell and the ground terminal, and in accordance with a program confirmation enable signal. A third pass transistor and a pull-down resistor having a potential between the two pass transistors and a sense amplifier for comparing and outputting the memory cell potential and a reference voltage according to the program check enable signal and the program enable signal; Flash memory characterized in that consisting of . The flash memory device as set forth in claim 1, wherein the memory cell is supplied with a drain voltage during programming through the first pass transistor even during program check. 2. The flash memory device of claim 1, wherein the voltage applied to any word line selected when the memory cell switches as a program and a program check operation is unchanged.