JPH0777344B2 - Output buffer circuit - Google Patents

Description

The present invention relates to an output buffer circuit used in a semiconductor device or the like.

[Conventional technology]

FIG. 4 is a circuit diagram showing a conventional output buffer circuit used in a semiconductor device. Of these, Figure 4 (a)
FIG. 6 is a circuit diagram showing a CMOS type output buffer circuit. cm
The OS circuit C is a P-channel MOS transistor (hereinafter P-MOS
Abbreviated as T. ) P1 and N-channel MOS transistor (hereinafter N-
Abbreviated as MOST. ) A series connection of N1 is connected between the power supply voltage V _CC and ground. And
The read data RD is input to the gate common connection point of the P-MOSTP1 and the N-MOSTN1 via the inverter I1, and the output DO is taken out from the drain common connection point.

FIG. 4B is a circuit diagram showing an NMOS type output buffer circuit. The series connection of N-MOST N2 and N3 is the power supply voltage V _CC
Is connected to the ground. The read data RD is directly applied to the gate of the N-MOSTN2, and the read data RD is applied to the gate of the N-MOSTN3 via the inverter I2.
Then, the output DO is taken out from the common source / drain connection point of the N-MOSTN2 and N3.

Next, the operation will be described with reference to FIG. First, the operation of the CMOS type output buffer circuit shown in FIG. 4 (a) will be described with reference to FIG. 5 (a).
When access is started (address A changes), read data RD is given to inverter I1 and the output of inverter I1 becomes "H", P-MOSTP1 is turned off after a certain delay.
Then, N-MOST N1 turns on. Therefore, the output DO becomes "L". On the other hand, when the read data RD is given and the output of the inverter I1 becomes "L", the P-MOSTP1 turns ON after a certain time delay.
Then, N-MOSTN1 turns off. Therefore, the output data DO becomes "H". In this case, the “H” level becomes the power supply voltage V _CC .

Next, the operation of the NMOS type output buffer circuit shown in FIG. 4 (b) will be described with reference to FIG. 5 (b). When the read data RD is "H", the output of the inverter I2 is "L". Therefore, N-MOSTN2 turns ON after a certain time delay.
Then, since the N-MOSTN3 is turned off, the output data DO becomes "H". In this case, the "H" level is V _CC -V _THN when the threshold of N-MOSTN2 is "V _THN ".

On the other hand, when the read data RD is "L", the output of the inverter I2 is "H". Therefore, N-MOSTN2 will
Since it is turned off and N-MOSTN3 is turned on, the output data DO is "L".
Becomes

[Problems to be Solved by the Invention]

Since the conventional output buffer circuit is configured as described above, it has the following problems. In recent years, the output inversion time of the output buffer has been shortened along with the speeding up of device operation. This means increasing the driving force of the output buffer, and lowering the impedance of the transistor of the output buffer in terms of the circuit.
The decrease in the impedance of the transistor of the output buffer means that the maximum value of the current flowing into or out of the output buffer increases, and along with this, the change in current per unit time di / dt becomes large. This amount of change in current di / dt is generally called the magnitude of noise, and causes a malfunction of the device or system. In the CMOS type output buffer circuit shown in FIG. 4 (a), since the "H" level is the power supply voltage V _CC as described above, when the output DO changes from "H" to "L", "L" The N-MOSTN1 that drives the N-MOSTN1 has to extract a considerable amount of electric charge, and the noise level becomes 0.5 to 0.7V when the N-MOSTN1 has a large size for speeding up, and it is easy to cause a malfunction. There was a problem.

In order to solve the above problems of the CMOS type output buffer circuit, the "H" level shown in FIG.
_An NMOS type output buffer circuit that is _CC- V _THN may be used. That is, since the “H” level is V _CC −V _THN ,
N- that drives “L” when output DO changes from “H” to “L”
The amount of charge that MOSTN3 has to be extracted is smaller than in the case of a CMOS type output buffer. As a result, the amount of change in current di / dt also decreases, and noise also decreases. When the output DO changes from “H” to “L”, the level of the output DO changes from V _CC −V _THN to 0, which is higher than V _CC − (V Time can be saved by the change time of ( _CC- V _THN ). Therefore, “H” →
Access time to "L" can be shortened.

The NMOS type output buffer circuit solves the problems of the CMOS type output buffer circuit as described above, and has an advantage that the speed can be increased when the output DO changes from “H” to “L”. It has the following disadvantages. In other words, the output DO is “L” →
When it changes to "H", it is N-MOSTN2 that drives "H". Therefore, when the N-MOSTN2 is turned on and the output DO is set to "H", the potential difference between the source and drain of the N-MOSTN2 is gradually reduced, and the driving capability is lowered. Therefore, there is a problem that the access time for the output DO to change from “L” to “H” becomes longer than that of the CMOS type output buffer circuit.

The present invention has been made to solve the above problems, and an object thereof is to obtain an output buffer circuit with less noise and a shorter access time.

[Means for Solving the Problems] In the output buffer circuit according to the present invention, a transistor of a first conductivity type which becomes conductive when a first activation signal is applied to the control electrode and a second transistor of the control electrode are provided. A second conductivity type transistor, which is rendered conductive when an activation signal is applied, is connected in series between a high potential node and a low potential node, and a complementary circuit having the connection point as an output node, the complementary circuit A potential holding circuit that is connected to the output node of the complementary circuit and outputs a predetermined potential lower than the potential of the high potential node to the output node of the complementary circuit when the control node receives the third activation signal. And receiving a second input signal and not outputting the third activation signal when the first input signal is active, the first activation signal is generated in response to the second input signal. Signal or the second activation One of the signals is output, the first activation signal is not output when the first input signal is inactive, and the second activation signal is output in response to the second input signal. Signal or the third
It has a logic circuit for outputting any of the activation signals.

In a second aspect of the output buffer circuit according to the present invention, the output of the potential holding circuit is a threshold voltage 1 between the source and gate of the transistor, which is higher than the potential of the high potential node.
It is lower by a step.

[Action]

According to the present invention, when the third activation signal is output in response to the second input signal, the potential holding circuit outputs a predetermined potential lower than the potential of the high potential node to the output node of the complementary circuit. To be done. At this time, the first activation signal and the second activation signal
Since the activation signal of is not output, the first conductivity type transistor and the second conductivity type transistor are in the non-conductive state, and the output node of the complementary circuit is the potential of the high potential node output by the potential holding circuit. It will be held at a lower predetermined potential. Further, since the configuration is such that either the second activation signal or the third activation signal is output when the first activation signal is not output, the second activation signal is output.
And the third activation signal are never output at the same time.

According to the second aspect of the output buffer circuit of the present invention, the potential of the output node of the complementary circuit is lower than the potential of the high potential node by one stage of the threshold voltage between the source and gate of the transistor. Becomes

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of an output buffer circuit according to the present invention. The read data RD and the control clock φ are input to the NAND circuit A1, and the output is given to the gate of the P-MOS TP1. Note that NA is set so that P-MOSTP1 turns on.
The application of the output of the ND circuit A1 is referred to as "the activation signal is applied to the gate of P-MOS TP1". Here, the control clock φ is a signal that remains “H” for a certain period when access is started. Read data RD is input to the inverter I3, and its output is given to the gate of the N-MOS TN1.
The application of the output of the inverter I3 so that the N-MOSTN1 is turned on is referred to as "the activation signal is applied to the gate of the N-MOSTN1". The read data RD and the control clock φ via the inverter I4 are input to the NAND circuit A2, and the output thereof is input to the gates of N-MOSTN4 and P-MOSTP2 forming the transmission gate X via the inverter I5. In other words, the inverter of the gate of N-MOSTN4
The output of I5 (denoted as node a) is directly input to P-MOST
The output of the inverter I5 is input to the gate of P2 via the inverter I6. Transmission gate X is ON here
That the output of the inverter I5 is given as
It is referred to as "the activation signal is given to the node a".

N-MOSTN5 and P-MOSTP3 are connected in series, and the drain of N-MOSTN5 is connected to the power supply voltage V _CC and also to the gate. The drain of the P-MOS TP3 is grounded via the resistor R1 and is also connected to the gate. N-
MOSTN6, P-MOSTP4 and N-MOSTN7 are connected in series in this order. The source of N-MOST N6 is connected to the power supply voltage V _CC and also to the gate. The gate of P-MOSTP4 is connected to the drain of P-MOSTP3. N-
MOSTN7 has its source grounded and its gate has an inverter I5.
The output of is given. And N-MOSTN6 and P-MOSTP4
A common connection point between the source and the drain is defined as a node b. N-
The circuit composed of MOSTN5, N6, N7 and P-MOSTP3, P4 and the resistor R1 keeps the potential of the node b at V _CC -V _THN .
This circuit is called a constant voltage generating circuit. Further, the potential of the node b becomes an output DO when the transmission gate X turns on. In other words, by being activated,
The potential holding circuit D that keeps the output DO potential at V _CC -V _THN is the transmission gate X, the inverter I6, P-MOSTP2, P3, P
4, N-MOST N5, N6, N7 and resistor R1. Here, the transmission gate X is a "switch circuit".
The node a is called a "control node" because of its function.

Next, referring to the solid line in Fig. 2 (a), the output DO is "L".
The operation of changing from "H" to "H" will be described. Before access, read data RD is "L", control clock is "L"
Suppose In this case, P-MOSTP1 is OFF, N-MOSTN
Since 1 is ON and node a is "L", the output DO becomes GND level ("L").

Next, when the access is started, the control clock φ becomes “H” for a certain period. Then, it is assumed that the read data RD becomes "H". Then, P-MOSTP1 turns on, N-MOSTN1 turns off,
The node a becomes "L". Therefore, the output DO becomes "H" (V _CC ) after a certain period of delay. After that, access is completed,
When only the control clock φ goes to "L", P
-MOSTP1 is turned off, N-MOSTN1 is turned off, and the node a becomes "H". The transmission gate X is turned on in response to "H" of the node a. Therefore, the potential of the node b, that is, V _CC -V _THN is output to the output DO. Thus, access is completed and only the control clock φ becomes "L", so that the level of "H" of the output DO falls V _CC -V _THN from V _CC. In this way, the output DO changes from “L” to “H”.
Changes to.

Next, the case where the output DO changes to "L" from the above-mentioned state will be described with reference to the solid line in FIG. 2 (a). Before access, as described above, the read data RD is "H", the control clock φ is "L", and P-MOSTP1 and N
-MOSTN1 is OFF, node a is "H", so transmission gate X is ON, output DO level is V _CC -V _THN
Has become. Read data RD when access starts
Becomes "L" and the control clock φ becomes "H". As a result, P-MOSTP1 is turned off and N-MOSTN1 is turned on after a certain period of delay, and the node a becomes "L". Therefore, the transmission gate X turns off and the output DO becomes GND level. After that, even if the access is completed and only the control clock φ becomes "L", P-
MOSTP1 is OFF, N-MOSTN1 is ON, node a remains "L", and output DO remains at GND level. In this way, the output DO changes from “H” (V _CC −V _THN ) to “L”.

Next, a case where the control clock φ changes from “L” to “H” to “L” while the read data RD remains “L” will be described. Even if the control clock φ changes in this way, P-MOS TP1 is OF
The F and N-MOSTN1 are ON, the node a remains "L", and therefore the output DO also remains at the GND level. This is shown by the solid line in FIG. 2 (b).

Next, while the read data RD remains "H", control clock φ
The case of changing from "L" to "H" to "L" will be described with reference to the solid line in FIG. 2 (b). In this way, when the control clock φ changes, the P-MOSTP1 becomes OF
It changes from F → ON → OFF, and the potential of node a changes from “H” to “L” →
Although it changes to "H", N-MOSTN1 remains OFF. The transmission gate X changes from ON to OFF to ON as the potential of the node a changes from "H" to "L" to "H". Therefore, the potential of output DO is (V _CC −V _THN ) → V _CC
→ It changes as (V _CC −V _THN ).

As described above, “H” (V _CC ) is output to the output DO, and when the control clock φ becomes “L” after that, the “H” level of the output DO becomes V
_Can be lowered from _CC to V _CC −V _THN . Therefore, in the next access, when the output DO becomes "L" (GND level), the current change amount di / dt becomes smaller depending on the case of using the CMOS type output buffer circuit. As a result, noise can be reduced. Further, the access time can be shortened by the change time of V _CC − (V _CC −V _THN ).

FIG. 3 is a circuit diagram showing another embodiment of the present invention. In this embodiment, a circuit for maintaining the potential of the output DO at a potential lower than V _CC when P-MOSTP1 and N-MOSTN1 are both off is constituted by a series circuit body of N-MOSTN7 and N8. ing. The N-MOSTN7 and N8 are connected in series, the drain of the N-MOSTN7 is connected to the power supply voltage V _CC, and the source of the N-MOSTN8 is grounded. Source-drain common connection points of N-MOSTN7 and N8 are connected to the output DO, and respective gates are commonly connected. The output of the inverter I5 is given to the common gate connection point of the N-MOS TN7 and N8. The other structure is similar to that of the embodiment shown in FIG.

Next, the operation will be described. P-MOSTP1 and N-MOSTN1
Read data RD and control clock φ when is turned on and off
Is the same as that of the embodiment shown in FIG. Also,
The levels of the read data RD and the control clock φ at which both N-MOSTN7 and N8 are turned on and off are the same as when the transmission gate X is turned on and off in the embodiment shown in FIG. In this embodiment, when both N-MOSTN7 and N8 are turned on, a potential (potential smaller than the power supply voltage V _CC ) according to the ratio of the driving capability of these transistors is output to the output DO, so that it is the same as the above embodiment. The effect of is obtained.

In the above embodiment, the case where the MOS transistor is used has been described, but the same effect as that of the above embodiment can be obtained by using the bipolar transistor.

〔The invention's effect〕

As described above, according to the present invention, when the control node is connected to the output node of the complementary circuit and the third activation signal is applied, a predetermined potential lower than the potential of the high potential node is applied to the complementary output node. Receiving the potential holding circuit for outputting to the first and second input signals, and not outputting the third activation signal when the first input signal is active, in response to the second input signal. , The first activation signal or the second activation signal is output, and when the first input signal indicates inactivity, the first activation signal is not output and the second input signal is output. In response, the logic circuit that outputs either the second activation signal or the third activation signal is provided, so that the output node of the complementary circuit is generated by the output of the third activation signal. Is maintained at a predetermined potential lower than the potential of the high potential node output by the potential holding circuit It becomes Rukoto. Therefore, when the potential of the output node of the complementary circuit changes from a high potential to a low potential, the current change amount di / dt becomes smaller than in the conventional case, and noise is also reduced. Further, there is an effect that the access time becomes faster than in the past. On the other hand, when the potential of the output node of the complementary circuit changes from the low potential to the high potential, the first conductivity type transistor forming the output complementary circuit is turned on, so that the access time does not become long. . Further, since the second activation signal and the third activation signal are not output at the same time, the second conductivity type transistor and the potential holding circuit operate at the same time, and the potential holding circuit outputs the second conductivity type signal. A state in which a current flows to the low potential node via the transistor of the mold is avoided.

According to the second aspect of the output buffer circuit of the present invention, the potential of the output node of the complementary circuit is made lower than the potential of the high potential node by one stage of the threshold voltage between the source and gate of the transistor. Only then, when the potential of the output node changes to a low potential, the amount of change in current di / dt can be made smaller than in the conventional case, and noise can be made small enough.

[Brief description of drawings]

1 is a circuit diagram showing an embodiment of an output buffer circuit according to the present invention, FIG. 2 is a diagram for explaining the operation of the circuit shown in FIG. 1, and FIG. 3 is another embodiment of the present invention. FIG. 4 is a circuit diagram showing an example, FIG. 4 is a circuit diagram showing a conventional output buffer circuit,
FIG. 5 is a diagram for explaining the operation of the circuit shown in FIG. In the figure, C is a CMOS circuit, D is a potential holding circuit, RD is read data, φ is a control clock, A1 and A2 are NAND circuits,
I3, I4 and I5 are inverters. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (4)

[Claims] 1. A transistor of a first conductivity type which is rendered conductive when a first activation signal is applied to the control electrode, and a second transistor which is rendered conductive when a second activation signal is applied to the control electrode. A conductivity type transistor connected in series between a high potential node and a low potential node, the complementary circuit having its connection point as an output node, connected to the output node of the complementary circuit, and connected to the control node as a first node. A potential holding circuit that outputs a predetermined potential lower than the potential of the high potential node to the output node of the complementary circuit when the activation signal of 3 is applied, and receives the first and second input signals and receives the first and second input signals. When the input signal is active, the third activation signal is not output,
In response to the second input signal, either the first activation signal or the second activation signal is output, and the first input signal is inactive when the first input signal is inactive. Output buffer circuit including a logic circuit that outputs either the second activation signal or the third activation signal in response to the second input signal. 2. The output buffer circuit according to claim 1, wherein the output of the potential holding circuit is lower than the potential of the high potential node by one threshold voltage between the source and the gate of the transistor. 3. The potential holding circuit is connected between the high potential node and the low potential node, and a constant voltage generating circuit for outputting the predetermined potential from an output node; and an output node of the constant voltage generating circuit. 3. The output buffer circuit according to claim 1, further comprising a switch circuit connected between the control circuit and an output node of the complementary circuit, the switch circuit being rendered conductive when a third activation signal is applied to the control node. . 4. The switch circuit includes a control electrode having the third electrode.
Of the first conductivity type transistor and the second conductivity type transistor which become conductive when the activation signal of
4. The output buffer circuit according to claim 3, wherein the output buffer circuit comprises a transistor of the conductivity type.