JP2003188278A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has excellent electrostatic breakdown voltage or the like and high reliability when a circuit operable at a low voltage is contained. <P>SOLUTION: The semiconductor device comprises a logic circuit 83 and an SRAM 84 operating at 0.5 V. The device further comprises an interface unit 82 having both a circuit for converting an input signal having a 3 V amplitude input from an external unit into a signal of a 0.5 V amplitude to supply to an interior and a circuit for converting the internal signal of the 0.5 V amplitude into a signal of the 3 V amplitude to output to the exterior. A channel region of a MOS transistor operating at the 0.5 V is electrically isolated by a trench and a deep well formed in a shallow well. Meanwhile, a channel region of a MOS transistor operating at the 3 V is formed on a deep well and electrically isolated. Thus, reliability of the MOS transistor to the electrostatic breakdown voltage for transmitting/receiving the signal directly to or from the exterior by operating at the 3 V is improved. <P>COPYRIGHT: (C)2003,JPO

Description

Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device.
I do. 2. Description of the Related Art In recent years, with the development of fine processing technology and the like,
High speed and high integration of LSI (Large Scale Integrated Circuit)
In. By the way, a high-speed operating LSI is put to practical use.
Therefore, low power consumption of LSI is one of the important technologies.
is there. That is, when the LSI is operated at high speed, the power consumption is
Becomes large and the LSI operates stably.
Has a ceramic package and heat dissipation fins.
It becomes necessary, and the cost increases. Ma
In recent years, portable devices have become smaller and lighter.
Power consumption from longer battery life.
is important. Conventionally, N-type MOS (metal oxide semiconductor) transistors
Consisting of four transistors and two P-type MOS transistors
SRAM cells are commonly used. In FIG.
A conventional N-type MOS (hereinafter abbreviated as NMOS) transistor
4 transistors and P-type MOS (hereinafter abbreviated as PMOS)
FIG. 2 shows a circuit diagram of an SRAM cell composed of two transistors.
You. FIG. 10 shows the case where the SRAM cell having the above-described configuration is used.
1 shows a layout of an entire SRAM. [0004] In FIG.
Force interface unit 2, spread the above SRAM cells
Memory unit 3, address decoder unit 4, data writing
The read control unit 5 is schematically configured. And the note above
The SRAM cell forming the memory section 3 has a structure as shown in FIG.
Have That is, the bit line B is connected to the first NMOS
Connected to the source (drain) of transistor 11
The gate line WL is connected to the first NMOS transistor 11 and the second N
Connected to the gate of the MOS transistor 12,
The line BX is connected to the source (gate) of the second NMOS transistor 12.
Rain). In the first NMOS transistor 11,
Drain (source) to which bit line B is not connected
Y has a third NMOS transistor 13 and a first PM
The gate of the OS transistor 15 is connected.
4 NMOS transistor 14 and second PMOS transistor
The drain of the transistor 16 is also connected. In the second NMOS transistor 12,
Drain to which the inverted bit line BX is not connected
(Source) YX has a fourth NMOS transistor 14 and
And the gate of the second PMOS transistor 16 is connected,
Furthermore, the third NMOS transistor 13 and the first PM
It is also connected to the drain of the OS transistor 15. The third NMOS transistor 13 and
The source of the fourth NMOS transistor 14 is connected to GND
And the first PMOS transistor 15 and the second
The source of the PMOS transistor 16 is connected to VDD.
ing. In the above configuration, the first NMOS transistor
MOs of the transistors 11 to the fourth NMOS transistor 14
A channel is formed when the S transistor is turned on
The semiconductor region is connected to GND. On the other hand, the first P
MOS transistor 15 and second PMOS transistor
When each MOS transistor of the
The semiconductor region where the semiconductor device is formed is connected to VDD.
You. [0009] However, the above-mentioned
The conventional SRAM has the following problems. That is,
In order to reduce the power consumption of the SRAM, the operating voltage (VD
A large effect can be obtained by lowering D). Toko
However, when VDD is lowered, the driving current of the MOS transistor is reduced.
And the delay time of the circuit increases and the operating speed
Is reduced. Therefore, even at low voltage, MOS
Make sure that the drive current of the transistor does not become too small
Lower threshold voltage (Vth) of MOS transistor
It is possible to do. However, when Vth is lowered, M
OS transistor leakage current increases, causing standby
High power consumption due to leakage current even in mode
Problem. [0010] By the way, 0.5 which can deal with the above-mentioned problem.
Low power consumption and small area operable at low voltage of about V
In a semiconductor device with a built-in SRAM,
For example, an input signal having a 3V amplitude is converted into a signal having a 0.5V amplitude.
While supplying the signal internally, the internal signal of 0.5V amplitude is
It is necessary to convert to 3V amplitude signal and output to outside
Become. In that case, the circuit that sends and receives signals to and from the outside
It is necessary to improve the reliability such as electrostatic withstand voltage. An object of the present invention is to operate at a low voltage.
Excellent in electrostatic withstand voltage, etc. when a possible circuit is built in
And to provide a highly reliable semiconductor device. [0012] To achieve the above object,
Therefore, in the semiconductor device of the present invention, a channel is formed when the semiconductor device is turned on.
The semiconductor region to be formed is formed in the first well,
The first MOS transistor for performing the internal processing and the
The semiconductor region where the tunnel is formed is deeper than the first well.
The second well is used to transmit signals directly to the outside.
And a second MOS transistor for receiving data.
are doing. [0013] According to the above configuration, transmission and reception of signals directly with the outside.
Of channel in second MOS transistor for performing
The region is in the first MOS transistor performing internal processing.
Second well deeper than the first well in which a channel is formed.
Is formed on Therefore, a signal with excellent electrostatic withstand voltage
A highly reliable semiconductor device can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention;
This will be described in detail according to the state. FIG. 1 shows the SR of the present embodiment.
FIG. 2 is a circuit diagram illustrating an example of an SRAM cell forming an AM.
You. The SRAM cell 27 in the present embodiment also has two P cells.
MOS transistor and 4 NMOS transistors
It is configured. The bit line B is a first NMOS transistor 2
1 and the word line WL is connected to the first
NMOS transistor 21 and second NMOS transistor
The inverted bit line BX is connected to the gate of the
Connected to the source (drain) of NMOS transistor 22
Have been. In the first NMOS transistor 21,
Drain (source) to which bit line B is not connected
Y has a third NMOS transistor 23 and a first PM
The gate of the OS transistor 25 is connected.
4 NMOS transistor 24 and second PMOS transistor
It is also connected to the drain of the transistor 26. In the second NMOS transistor 22,
Drain to which the inverted bit line BX is not connected
(Source) YX has a fourth NMOS transistor 24 and
And the gate of the second PMOS transistor 26 is connected,
Further, the third NMOS transistor 23 and the first PM
It is also connected to the drain of the OS transistor 25. The fourth NMOS transistor 24 and
GND is connected to the source of the third NMOS transistor 23.
The first PMOS transistor 25 and the
VDD is connected to the source of 2PMOS transistor 26
Have been. In the present embodiment, the first
1 NMOS transistor 21 to 4 NMOS transistors
The data 24 is composed of the DTMOS. On the other hand, the first P
MOS transistor 25 and second PMOS transistor
When each MOS transistor of the
A semiconductor region in which a semiconductor device is formed is formed by a conventional SRA shown in FIG.
It is connected to VDD like the M cell. FIG. 2 shows an SRAM cell 2 having the above configuration.
Cell array in SRAM with storage element 7
B. Connection between write circuit and read circuit
FIG. Here, the write circuits 29, 31
And a MOS transistor constituting the readout circuit 37
Are all DTMOS. Hereinafter, FIG. 1 and FIG.
When the circuit shown is operated at VDD = 0.5V,
Will be explained. First, in the SRAM cell 27,
The first and second NMOS transistors 21 and 22 are turned off.
And while the second PMOS transistor 26 is turned on,
4 The NMOS transistor 24 is turned off and the node Y becomes VD
D level, the first PMOS transistor 25 is turned off
While the third NMOS transistor 23 is turned on,
State when YX is at GND level,
Write data “0” to the state where “1” is stored.
The following describes the case of the insertion. The writing circuits 29 and 31 operate
The bit line B is at the GND (0) level and the inverted bit line BX is at V
The DD level is set. In addition, the selected SRAM cell
The word line WL of the channel 27 goes to the VDD level,
The first and second NMOS transistors 21 of the RAM cell 27,
22 are both turned on. Therefore, the potential of the node Y is
The potential difference (0.5 V) between VDD and GND is determined by the second PMOS.
ON resistance (RP2) of transistor 26 and first NMOS
The on-resistance (RN1) of the transistor 21 and the bit line B
The NMOS transistor of the write circuit 29 at the GND level
The potential divided by the ON resistance (RNW1) of the transistor 30
become. Therefore, the potential (VY) of the node Y is expressed by the following equation (1): VY = 0.5 × (RN1 + RNW1) / (RP2 + RN1 + RNW1) (1) Then, the potential of the node Y represented by the equation (1)
VY is the third NMOS transistor 23 and the first PMOS transistor.
The inverter composed of the transistor 25 can be inverted.
The second PMOS transistor 26 is set to a low potential.
While the on-resistance (PR2) of the first NMO
The on-resistance (RN1) of the S transistor 21 and the NMOS transistor
By setting the ON resistance (RNW1) of the transistor 30 small
is there. As a result, at the time of writing data “0”,
MOS transistor 23 and first PMOS transistor 2
5 is inverted and the inverter of node YX is inverted.
The potential goes to the VDD level. Then, the second PMOS transistor
And a fourth NMOS transistor 24.
The inverter is also inverted, and the second PMOS transistor 26
While turning off, the fourth NMOS transistor 24 turns on.
Therefore, the potential of the node Y goes to the GND level. Toes
Data "0" is written to the selected SRAM cell 27.
It will be. After that, the word line WL is set to the GND level.
And turn off the first and second NMOS transistors 21 and 22
By doing so, data "0" is stored. Next, the SRA storing data "0"
The case where data “1” is written to M cell 27 will be described.
Bell. By the write circuits 29 and 31, the bit line B is
VDD level and inverted bit line BX are set to GND level.
Is determined. Also, the word of the selected SRAM cell 27
The line WL goes to the VDD level, and the SRAM cell 27
, The first and second NMOS transistors 21 and 22 are both on.
I do. Therefore, the potential of the node YX is between VDD and GN
The potential difference (0.5V) from D to the first PMOS transistor
25 on-resistance (RP1) and 2nd NMOS transistor
22 and the inverted bit line BX is connected to GND.
Level of the NMOS transistor of the write circuit 31
The potential is divided by the on-resistance (RNW2) of the
You. Therefore, the potential (VYX) of the node YX is represented by the following equation (2): VYX = 0.5 × (RN2 + RNW2) / (RP1 + RN2 + RNW2) (2) Then, the node YX represented by the above equation (2)
Potential VYX between the fourth NMOS transistor 24 and the second P
The inverter composed of the MOS transistor 26 and the
1st PMOS transistor so that the potential becomes
The on-resistance (PR1) of the star 25 is set large. on the other hand,
The ON resistance (RN2) of the second NMOS transistor 22 and N
The ON resistance (RNW2) of the MOS transistor 32 is small.
It has been set. As a result, when data "1" is written
Is a fourth NMOS transistor 24 and a second PMOS transistor.
The inverter constituted by the transistor 26 is inverted, and
The potential of the node Y goes to the VDD level. Then, the first PMOS transistor
And a third NMOS transistor 23.
The inverter is also inverted, and the first PMOS transistor 25
While turning off, the third NMOS transistor 23 turns on.
Therefore, the potential of the node YX becomes the GND level. One
That is, data “1” is written to the selected SRAM cell 27.
It will be rare. Then, the word line WL is connected to the GND level.
And turn off the first and second NMOS transistors 21 and 22.
As a result, data "1" is stored. The SRAM cell 27 in the present embodiment is
First to fourth NMOS transistors to be configured
The transistor 24 is a DTMOS as described above.
Further, the NMOS transistors constituting the write circuits 29, 31
Transistors 30, 32 and PMOS transistors 33, 3
4 is also a DTMOS. Here, the DTMOS is
As described above, the semiconductor region where a channel is formed when turned on
The area is connected to the gate. Therefore, when turning on
| Vth | in the conventional SRAM cell shown in FIG.
First to fourth NMOS transistors 11 to
When the channel is GND as in the case of the
The channel is VDD like the PMOS transistor of
And the on-resistance is lower. On the other hand,
| Vth | in the conventional SRAM cell shown in FIG.
First to fourth NMOS transistors 11 to
Same as S transistor 14 and normal PMOS transistor
About high. Therefore, the above DTMOS is used.
Each of the MOS transistors 21 to 24, 30, 32 to 34 is
Low on-resistance and low off-state leakage current. That
As a result, a small area, low power consumption SRAM cell 27 is realized.
it can. Fast writing speed, small area, low power consumption
Powerful writing circuits 29 and 31 can be realized. On the other hand, the data stored in the SRAM cell 27
When reading data, the NMO of the write circuit 29 is used.
S transistor 30 and PMOS transistor 33
And the NMOS transistor 32 and the write circuit 31
And the PMOS transistor 34 are turned off, and the address signal
Bit line B and the power supply for a certain period immediately after
The read circuit 37 is provided between the power supply and the voltage VDD.
The NMOS transistor 35 to be turned on and the inverted bit line BX.
The read circuit 37 is provided between the power supply voltage VDD and the power supply voltage VDD.
Turn on the NMOS transistor 36 that constitutes
Line B and the inverted bit line BX are connected to (VDD-Vthnon) level.
Up to Then, the bit line B and the inverted bit
Line BX is (VDD-Vthnon) level
After the period has elapsed, the NMOS transistors 35 and 36
Is turned off. Here, the Vthnon is an NMOS transistor.
When the transistor 35 and the NMOS transistor 36 are turned on.
Vth at Thus, the NMOS transistor 3
When 5, 36 turns off, the selected word line WL becomes VD
D, the first NMOS transistor of the selected SRAM cell 27
Transistor 21 and the second NMOS transistor 22 are turned off.
While the potential of the node Y is led out to the bit line B,
The potential of the node YX is led out to the inverted bit line BX. Here, data is stored in the SRAM cell 27.
If “0” is stored, the first and second NMOS transistors
Before the transistors 21 and 22 turn on, the node Y
The level is GND. However, the first and second NMOSs
When the transistors 21 and 22 are turned on, the bit line B goes up.
As described above, it is precharged to the potential (VDD-Vthnon).
Therefore, the potential VY of the node Y becomes the fourth NMOS transistor.
Assuming that the on-resistance of the transistor 24 is RN4, temporarily
Expression (3) VY = (VDD−Vthnon) × RN4 / (RN1 + RN4) (3) Here, the expression (3)
The potential VY of the gate Y is connected to the first PMOS transistor 25 and the third PMOS transistor 25.
Of the inverter constituted by the NMOS transistor 23
A fourth NMOS transistor so as not to exceed the inversion voltage
ON resistance RN between the first NMOS transistor 21 and the first NMOS transistor 21
4 and RN1 are set. So a bit
The charge on line B is the first NMOS transistor in the ON state.
Through the transistor 21 and the fourth NMOS transistor 24.
And the bit line B goes to the GND level. On the other hand, the potential of the inversion bit line BX is
Since the potential of the node YX is VDD (VDD−Vthnon)
It does not change. Therefore, the read circuit 39
The level of the output Q becomes "L" via the inverter 38,
Data "0" is read. Then the word
The line WL goes to the GND level and the first and second NMOS transistors
Transistors 21 and 22 are turned off and stored in SRAM cell 27
Data is retained without being destroyed. The data is stored in the SRAM cell 27.
Similarly, when “1” is stored, the second NMOS transistor
When the transistor 22 is turned on, the potential V of the node YX is
YX indicates the on-resistance of the third NMOS transistor 23 as R
Assuming that the potential is N3, the potential is temporarily represented by the following equation (4): VYX = (VDD−Vthnon) × RN3 / (RN2 + RN3) (4) Here, the node represented by the equation (4)
The potential VYX of the second PMOS transistor 26
Inverter composed of fourth NMOS transistor 24
3rd NMOS transistor so as not to exceed the inversion voltage of
ON resistance R between the resistor 23 and the second NMOS transistor 22
N3 and RN2 are set. Therefore, SR
The data stored in the AM cell 27 is not destroyed.
Then, the potential of the inverted bit line BX is at the GND level.
Therefore, the data is inverted by the inverter 38 and the data is output by the output Q.
The data "1" is read. Here, the read circuit 37 is constructed.
NMOS transistor 35 and NMOS transistor
Reference numeral 36 denotes a DTMOS. Therefore, on
Low resistance and low leakage current when off
are doing. Therefore, bit line B and anti-bit line B
Reduce the precharge time when precharging X
Therefore, the leak current can be reduced with a small area.
The readout circuit 37 is a PMOS transistor made of DTMOS.
The same effect can be obtained by using a transistor. Also read
The inverter 38 forming the output circuit 39 is connected to the DTMO
If it is formed of S, the power consumption of the readout circuit can be further reduced and
And the speed of reading can be increased. Usually, in the above-mentioned SRAM cell, data storage is performed.
Turn off each transistor to reduce power consumption
It is necessary to keep the leakage current at the time of
| Vth | of the transistor cannot be made very small. But
Therefore, in the conventional SRAM cell shown in FIG.
The on-resistance (R) of the first and second NMOS transistors 11 and 12
N11, RN12) and two NMOS transistors of the write circuit.
Transistor (NMOS transistors 30 and 32 in FIG. 2)
In order to reduce the on-resistance of
Four NMOS transistors in M cell and write circuit
It is necessary to widen the gate width of the
The area of the transistor (that is, the area of the SRAM cell)
It gets bigger. The above four NMOS transistors
If the gate width is not widened, the SRAM cell
Increase the on-resistance of the first and second PMOS transistors 15 and 16
Need to be controlled for both PMOS transistors.
It is necessary to increase the gate length of the stars 15 and 16. did
Therefore, also in this case, the area of the SRAM cell becomes large.
Would. Also, the first and second PMOS transistors 15,
When the gate length of the SRAM cell is increased,
First and second NM when writing / reading data to / from
Because the on-resistance of the OS transistors 11 and 12 is large
Another problem is that the write / read time will be longer.
You. On the other hand, in the present embodiment,
First NMOS transistor in the SRAM cell 27
The first to fourth NMOS transistors 24 are the same as those described above.
As shown in FIG. Therefore, the above 4
Of NMOS transistors 21-24
The channel region voltage is at the GND level, and the voltage shown in FIG.
First NMOS transistor 1 in a conventional SRAM cell
It shows the same characteristics as the first to fourth NMOS transistors 14.
On the other hand, the channel region voltage at the time of ON is VDD.
You. Therefore, the NMOS transistors 21 to 24
| Vth | at the time of on is | Vth |
Each NMOS transistor in a conventional SRAM cell
| Vth |) of the data 11-14. That is,
0.5V, which was difficult in a conventional SRAM cell,
Operation at lower voltage, and power consumption during operation
Can be made smaller. Furthermore, the above on-resistance
| Vth | minus (VGS- | Vth |)
Since it is inversely proportional, the SRAM cell 27 of the present embodiment
ON resistance of each NMOS transistor 21 to 24 at
Represents each NMOS transistor in a conventional SRAM cell.
It becomes smaller than the on-resistance of the transistors 11 to 14. Accordingly
Write / read more than the conventional SRAM cell.
The speed can be increased. In addition, conventional SRAM cell
If the write / read speed is the same as the
The area can be smaller than that of a conventional SRAM cell. Moreover,
When each of the NMOS transistors 21 to 24 is off
Leakage current of each NMOS transistor of a conventional SRAM cell.
Same as leakage current when transistors 11-14 are off
There is no problem of increased power consumption during standby
It is. In the SRAM cell 27,
Gate oxide films of first and second PMOS transistors 25 and 26
The thickness of the first to fourth NMOS transistors 21 to 24 is
By increasing the thickness of the first and second oxide films, the first and second
Increase the on-resistance of PMOS transistors 25 and 26
To reduce the current value, and the first NMOS transistors 21 to 21
The fourth NMOS transistor 24 has a smaller transistor.
Data. Therefore, in that case,
In addition, small area, low leakage current and low power consumption S
A RAM cell can be provided. FIG. 3 is a block diagram of the SRAM cell 27 shown in FIG.
FIG. 2 is a sectional view showing a deep well and a shallow well.
It has a heavy well structure. First and third NMOS transistors
Shallow P well 4 in which transistors 21 and 23 are formed
Reference numerals 1 and 42 denote transistors for each of the MOS transistors 21 and 23.
H 43 and the deep N-well 44
I have. Then, the gate of the first NMOS transistor 21
Is connected to the shallow P-well 41, and the third NMOS transistor
The gate of the transistor 23 and the shallow P well 42 are in contact with each other.
Subsequently, a DTMOS is formed respectively. In addition,
The deep N well 44 is connected to VDD. The first PMOS transistor 25
The shallow N-well 45 in which is formed is connected to VDD.
On the other hand, the deep P well 46 is connected to GND.
ing. Note that the first PMOS transistor 25 (second PM
Even if the OS transistor 26) is configured by the DTMOS,
Good, but to increase on-resistance in a small area
It is better to connect the -N well 45 to VDD. FIG. 4 is a circuit diagram of the SRAM cell 27 shown in FIG.
This is an improved structure. First and third NMOS transistors
Shallow P well 5 in which transistors 21 and 23 are formed
Reference numerals 1 and 52 denote transistors for each of the MOS transistors 21 and 23.
H 53 and the deep N well 54
I have. Then, the gate of the first NMOS transistor 21
Is connected to the shallow P well 51, and the third NMOS transistor
The gate of the transistor 23 and the shallow P well 52 are in contact with each other.
Subsequently, a DTMOS is formed respectively. In addition,
The deep N well 54 is connected to VDD. Here, FIG. 3 shows in FIG.
However, the first and second PMOS transistors 25, 26
Is formed in each PMOS transistor.
Trench 47 and deep P-well 46 for each transistor
Electrically isolated. However, SRAM cells
27, the first and second PMOS transistors 25, 26
The semiconductor region where the channel is formed is common to VDD.
For each PMOS transistor 25, 26
There is no need to separate the N-well 45. Therefore, in FIG.
Deep N-well area for separating wells 51 and 52
The first PMOS is connected to a region 54 (where a voltage of VDD is applied).
Transistor 25 and second PMOS transistor 26
It forms. By doing so, the SRAM cell
In region 27, shallow N well and
There is no need to form a loop P-well, and the structure shown in FIG.
Therefore, the area of the SRAM cell 27 can be reduced. FIGS. 3 and 4 show the above SRAM cell.
27 is an example in the case where 27 is formed on a silicon single crystal substrate
Are the SRAM cell 27 shown in FIG. 1 and the SR cell shown in FIG.
AM is not limited to silicon single crystal substrates, but SOI (silicon
(On-insulator) substrate. FIG.
4 and FIG. 4, the first NMOS transistor 21
And the third NMOS transistor 23 and the first PMOS transistor.
The relationship with the transistor 25 is described.
MOS transistors 22, 24 and a second PMOS transistor
The same applies to the relationship with the transistor 26. FIG. 5 shows the SRAM cell 27 shown in FIG.
Of the first and second PMOS transistors 25 and 26
Is replaced by a first resistor 65 and a second resistor 66
AM cell 67. The first NMOS transistor 6
The first to fourth NMOS transistors 64 are shown in FIG.
First NMOS transistor 2 in SRAM cell 27
It corresponds to the first to fourth NMOS transistors 24. here
The first and second resistors 65 and 66 are high-resistance polysilicon.
And a thin film transistor (TFT) or the like. In the SRAM cell 67 having the above configuration, the data
Data “1” is written (node Y → VD
D, node YX → GND) when writing data “0”
In this case, assuming that the resistance value of the second resistor 66 is RP2, the equation (1)
The voltage VY of the node Y represented by
The inverter composed of the MOS transistor 63 is inverted.
Voltage that can be switched. Also, data “0” is
Write state (node Y → GND, node YX
When writing data “1” to (VDD), the first resistor
Assuming that the resistance value of the anti-65 is RP1,
The voltage VYX of the gate YX is applied to the second resistor 66 and the fourth NMOS transistor.
An inverter that can invert the inverter composed of the transistor 64
Pressure. By doing so, it is shown in FIG.
The SRAM cell 67 is different from the SRAM cell 27 shown in FIG.
The same operation is performed to write data. FIG. 6 shows an SRAM cell 6 having the above configuration.
Cell array in SRAM with storage element 7
B) a circuit indicating the connection relationship between 68 and the write circuits 69 and 70;
It is a road map. The writing circuit 69 performs the writing shown in FIG.
The PMOS transistor 33 of the circuit 29 is
With the configuration replaced with the NMOS transistor 73
You. On the other hand, the write circuit 70
The PMOS transistor 34 of the path 31 has a DTMOS structure.
With the configuration replaced with the NMOS transistor 74
You. Note that the NMOS transistor 71 of the write circuit 69
Is an NMOS transistor of the write circuit 29 shown in FIG.
Data 30. Also, the NMOS of the writing circuit 70
The transistor 72 is connected to the N of the write circuit 31 shown in FIG.
This corresponds to the MOS transistor 32. And NMOS
NMOS transistors are connected to the gates of the transistors 73 and 74.
The input signals WB, WBX to the gates of the
The inverted signals WBX and WB are input. According to the above configuration, the write cycle shown in FIG.
The circuit is simpler than the paths 29 and 31. Of course, the bit line
The potential at the time of writing to B and the inverted bit line BX is
(VDD-Vthnon) level.
Power consumption compared to the case of only the circuits 29 and 31 (VDD).
Become. FIG. 7 shows an SRAM cell in this embodiment.
1 shows a layout of a semiconductor device having a built-in device. Semiconductor equipment
The device 81 includes an external interface unit 82, a logic circuit
It is roughly composed of a unit 83 and an SRAM unit 84. Where
The logic circuit unit 83 and the SRAM unit 84 operate at 0.5V.
Area. The interface unit 82 has a
A region operating at a voltage higher than 5V (for example, 3V);
And a region operating at 0.5V. Toes
Input signal of 3V amplitude input from the outside
A circuit that converts the signal into an amplitude signal and supplies the signal to the inside;
Converts internal amplitude signal to 3V amplitude signal and outputs to outside
Circuit. FIG. 8 shows an example of the interface unit 82.
It is a sectional view of a part, a deep well and a shallow well.
It has a double structure. NMO operating at 0.5V
S transistor 91 and PMOS transistor 92
Are the shallow P well 93 and the shallow N well 94
And a trench 95, a deep N well 96 and
And a deep P-well 97.
On the other hand, the NMOS transistor 1 operating at 3V
01 and the PMOS transistor 102
Formed in the well 103 and the deep N well 104
And electrically isolated. This is M operating at 3V
The OS transistors 101 and 102 transmit signals directly to the outside.
Transmit and receive, improve reliability against electrostatic withstand voltage, etc.
That's because. Of course, deep well 96,97,10
The protection around 3,104 is the same as the conventional semiconductor device.
It goes without saying that the circuit is configured. As described above, in the present embodiment,
NMOS transistors forming SRAM cells 27 and 67
DTMOS with the channel region connected to the gate
Make up. Further, the SRAM cells 27 and 67 were used.
Construct SRAM write circuits 29, 31, 69, 70
MOS transistors 30, 32, 33, 34, 71 to 7
4 and the NMOS transistors constituting the readout circuit 37.
The transistors 35 and 36 are composed of the DTMOS. And
Therefore, | Vth | when on is lower than | Vth | when off.
Low voltage operation at 0.5 V, which was previously impossible
And power consumption during operation can be reduced. this
In contrast, | Vth | when off is a normal MOS transistor.
Same as star. Therefore, the off-state leakage current
Standby consumption equal to conventional SRAM cells
An increase in power can be prevented. Each of the DTMOS MOS transistors
The on-resistance of the transistor is low because | Vth |
Therefore, conventional DTMOS is not used.
Write / read speed faster than SRAM
You. In addition, the write / read speed is lower than that of the conventional SRAM.
If the on-resistance is small, the above-mentioned D is reduced by the amount corresponding to the small on-resistance.
The gate width of the TMOS can be reduced, and the area of the DTMOS can be reduced.
In other words, the area of the SRAM cell or SRAM can be reduced.
It is. The write circuit of the SRAM shown in FIG.
At 69 and 70, the bit line B and the inverted bit line BX are
The transistor that raises the potential is set to the DTMOS structure.
It consists of a built-in NMOS transistor. Accordingly
When writing the bit line B and the inverted bit line BX,
Potential can be set to (VDD-Vthnon) level, as shown in FIG.
In the case of the SRAM write circuits 69 and 70 (VDD)
Power consumption can be reduced. The above SRAM cells 27 and 67 are built in.
Configuration of interface unit 82 in a semiconductor device
Of MOS transistors 91 and 92 operating at 0.5V
The channel region is composed of shallow wells 93 and 94.
ing. In contrast, MOS transistors operating at 3V
The channel region of the star 101, 102 is a deep well
103 and 104. Therefore, with the outside
MOS transistor operating at 3V for directly transmitting and receiving signals
To improve the reliability of the
I can do it. As is clear from the above, a half of the present invention is achieved.
The conductor device is a second MOS transistor for directly transmitting / receiving signals to / from the outside.
Internal processing of channel formation area in transistor
Channel formed in the first MOS transistor
The second well deeper than the first well
Obtaining a highly reliable semiconductor device with excellent electrostatic withstand voltage
it can.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an SRAM built in a semiconductor device of the present invention.
FIG. 4 is a circuit diagram of an SRAM cell constituting the present embodiment. FIG. 2 is a diagram showing an SRA using the SRAM cell shown in FIG. 1 as a unit;
FIG. 3 is a diagram illustrating a connection relationship between an M cell array and a write circuit and a read circuit. FIG. 3 is a partial sectional view of the SRAM cell shown in FIG. 1; FIG. 4 is a partial sectional view different from FIG. 3; FIG. 5 is a circuit diagram of an SRAM cell different from FIG. 1; FIG. 6 is a diagram showing an SRA using the SRAM cell shown in FIG.
FIG. 3 is a diagram illustrating a connection relationship between an M cell array and a write circuit. FIG. 7 is a diagram showing a layout of a semiconductor device using the RAM cell shown in FIG. 1 or 5; 8 is a partial cross-sectional view of the interface unit in FIG. FIG. 9 is a circuit diagram of a conventional SRAM cell. FIG. 10 is a diagram showing a layout of an SRAM using SRAM cells. [Description of References] 21, 61: first NMOS transistor, 22, 62: second NMOS transistor, 23, 63: third NMOS transistor, 24, 64: fourth NMOS transistor,
25: first PMOS transistor, 26: second PMOS transistor
Transistors, 27, 67 ... SRAM cells,
28, 68 ... SRAM cell array, 29, 31, 69, 70
... Write circuit, 30, 32, 35, 36, 71 to 74, 9
1, 94, 101 ... NMOS transistors, 33, 34, 9
2, 102: PMOS transistor, 37, 39: readout circuit, 38: inverter, 41, 42, 5
1,52,93 Shallow P-well, 43,47,53,95
... Trench, 44,54,96,104 Deep N-well, 45,94 Shallow N-well, 46,97,103
... Deep P well, 65,66 ... Resistance,
81: semiconductor device, 82: interface unit, 83: logic circuit unit, 84: SRAM unit,
B: bit line, WL: word line,
BX: Inverted bit line.

Claims (1)

Claims: 1. A semiconductor region in which a channel is formed when turned on is formed in a first well, a first metal oxide semiconductor transistor for performing internal processing, and a channel is formed when turned on. A semiconductor device, wherein a semiconductor region is formed in a second well deeper than the first well, and a second metal oxide semiconductor transistor for directly transmitting / receiving a signal to / from the outside is provided.