JPH09200024A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set up the other power supply system automatically when one of two kinds of power supply systems is activated earlier. SOLUTION: When a 2nd power supply voltage VDD2 is applied while a 1st power supply voltage VDD1 is not applied, a current flows from a power supply potential point 42 to a power supply potential point 41 to a bypass power supply circuit 12 being series connected diodes D1, D2. Since inverter gates G1-G3, G6-G11 form a CMOS configuration, no current flows ideally, but a very small leakage current is in existence (transient through-current, sub threshold current or junction leakage current or the like). Through the current flowing, the diodes D1, D2 support a voltage VB of nearly 0.7V and even when the 1st power supply voltage VDD1 is not provided, a potential of nearly 3.6V is given to the power supply potential point 41.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit that requires two types of power supplies.

[0002]

2. Description of the Related Art FIG. 17 is a circuit diagram showing an example of the configuration of a conventional semiconductor integrated circuit with a signal level converting function.

A semiconductor integrated circuit with a signal level conversion function level-converts a signal voltage supplied by a device operating at the power supply voltage inside the LSI, and uses a power supply voltage different from the power supply voltage of the circuit inside the LSI (internal circuit). It means a semiconductor integrated circuit having a function of outputting to an operating external circuit and a function of converting a signal supplied from a device having a different external power supply voltage system into a signal level of an internal circuit and transmitting the signal level to the inside.

An internal circuit 20 is connected to the input / output terminal 1 via an input buffer 10. Also, input / output terminal 1
A control terminal 2 for receiving a control signal IN1 from the internal circuit and an input terminal 3 for receiving an output signal IN2 from the internal circuit are connected to each other via an output buffer 9.

The output buffer 9 comprises an input / output control circuit 6, a signal level conversion circuit 7, and a buffer circuit 8a. The control terminal 2 and the input terminal 3 are connected to the input / output control circuit 6. The input / output control circuit 6 outputs to the signal level conversion circuit 7,
The signal level conversion circuit 7 outputs to the buffer circuit 8a via connection points N13 and N23.

The first half of the input / output control circuit 6 and the signal level conversion circuit 7 are supplied with the first power supply potential VDD1 and the ground potential GND, which are the power supply voltage of the internal circuit, to operate. The first power supply potential VDD1 and the ground potential GND are supplied by the power supply potential point 41 and the ground potential point 5, respectively. Gate G, which is abbreviated to avoid complication
Power source potential point 41 and ground potential point 5 for all of 1 to G11
Is connected and its function is demonstrated.

On the other hand, the second power supply potential VDD2 higher than the first power supply potential VDD1 and the ground potential GND are applied to the latter half of the signal level conversion circuit 7 and the buffer circuit 8a to operate. The second power supply potential VDD2 and the ground potential GND are supplied by the power supply potential point 42 and the ground potential point 5, respectively.

When the control signal IN1 is at "H" level, whether the output signal IN2 is at "L" level or "H" level, the signal level conversion circuit 7 causes the connection point N1.
3 and N14 are each at "L" level (ground potential GN
D), "H" level (second power supply potential VDD2).
In response to this, the transistor Q9a of the buffer circuit 8a,
All of Q10 are turned off, and the buffer circuit 8a is in a high impedance state with respect to the input / output terminal 1. As a result, an external signal applied to input / output terminal 1 is transmitted to input buffer 10 without being damaged.

On the other hand, if the control signal IN1 is at "L" level and the output signal IN2 is at "L" level, the signal level conversion circuit 7 causes the connection point N1.
All 3 and N14 are at "L" level. In response to this, the transistors Q9a and Q10 of the buffer circuit 8a are turned off and on, respectively, and the "L" level is output to the input / output terminal 1.

When the control signal IN1 is at "L" level and the output signal IN2 is at "H" level, the signal level conversion circuit 7 causes the connection point N13,
All of N14 become "H" level. In response to this, the transistors Q9a and Q10 of the buffer circuit 8a are turned on and off, respectively, and the "H" level is output to the input / output terminal 1.

FIG. 18 is a sectional view showing a configuration example of the transistors Q9a and Q10. The ground potential GND is commonly applied to all the wells W.

FIG. 19 is a circuit diagram showing another example of the configuration of the input / output circuit of the conventional semiconductor integrated circuit with a signal level converting function. The configuration shown in FIG. 19 is a configuration in which the buffer circuit 8a of the configuration shown in FIG. 17 is replaced with a buffer circuit 8b. The buffer circuit 8b has a structure in which the inverter gate G18 and the NMOS transistor Q9a of the buffer circuit 8a are replaced with a PMOS transistor Q9b.

Even with such a configuration, it is clear that the operation described with reference to FIG. 18 is performed.

FIG. 20 is a sectional view showing a configuration example of the transistors Q9b and Q10. Unlike the transistor Q9a, the well W of the transistor Q9b has a second power supply potential V
DD2 is given.

[0015]

The conventional semiconductor integrated circuit with a signal level converting function is configured as described above, and when the normal operation is performed, the connection point N1
The set of potentials of N3 and N23 is any one of ("H" level, "H" level), ("L" level, "L" level), and ("L" level, "H" level).

However, when the first power supply potential VDD1 is not applied in the initial state where the second power supply potential VDD2 is applied, the values of the respective parts of the signal level conversion circuit 7 are not uniquely determined. For example, a pair of potentials at the connection points N13 and N23 may be (“H” level, “L” level). In such a situation, a pair of transistors Q9
a, Q10 (or Q9b, Q10) are both turned on at the same time, and the buffer circuit 8a (or 8
In b), there is a problem that an unnecessary current (through current) flows between the power supply potential point 42 and the ground potential point 5.

The present invention has been made to solve the above problems, and when one of two types of power supply systems is turned on first, a semiconductor integrated circuit which automatically realizes the other power supply system. The purpose is to get.

[0018]

Means for Solving the Problems Claim 1 of the present invention
According to the present invention, the first power supply system is required for driving, the first circuit that outputs at least one logical value, and the second power supply system is required for driving, and the output of the first circuit is required. And a second circuit that receives the logical value and performs logical processing. Here, the first power supply system is realized by a first power supply having a first potential difference with respect to a reference potential, and the second power supply system has a second potential difference with respect to the reference potential that is larger than the first potential difference. Two
It is realized by the power supply. Further, the first power supply system is also realized by the potential lowered from the second power supply when the second power supply is turned on before the first power supply.

According to claim 2 of the present invention,
The semiconductor integrated circuit according to claim 1, further comprising a power supply circuit having a first diode group including at least one diode connected in series in the same direction. The anode of the first diode group closest to the second power source is connected to the second power source, and the cathode of the first diode group farthest to the second power source is connected to the connection point. . When the second power supply is turned on before the first power supply, the potential obtained from the connection point realizes the first power supply system.

According to claim 3 of the present invention,
The semiconductor integrated circuit according to claim 2, wherein the power supply circuit further includes a second diode group including at least one diode connected in the same direction as the first diode group. An anode of the second diode group closest to the second power source is connected to the first connection point,
The reference potential is applied to the cathode of the second diode group that is farthest from the second power source.

According to claim 4 of the present invention,
The semiconductor integrated circuit according to claim 2, wherein the power supply circuit further includes a resistor including one end connected to the first connection point and the other end to which the reference potential is applied.

According to claim 5 of the present invention,
The semiconductor integrated circuit according to claim 1, further comprising a power supply circuit having a first diode group including at least one diode connected in series in the same direction. Here, the anode of the one of the first diode group closest to the second power supply is connected to the second power supply. Further, the power supply circuit has a current limiting element including a first end connected to the cathode of the one of the first diode group farthest from the second power supply and a second end connected to the connection point. . When the second power supply is turned on before the first power supply, the potential obtained from the connection point realizes the first power supply system.

According to claim 6 of the present invention,
The semiconductor integrated circuit according to claim 5, wherein the current limiting element is a resistor.

According to claim 7 of the present invention,
The semiconductor integrated circuit according to claim 5, wherein the current limiting element has a gate and a drain commonly connected to the first connection point, and a source connected to the first end of the current limiting element. And a back gate connected to the second power supply.

According to claim 8 of the present invention,
The semiconductor integrated circuit according to claim 1, wherein the first end connected to the second power supply and the second end connected to the first connection point
A first resistor including an end and a first resistor connected to the connection point
The power supply circuit further includes a second resistor including an end and a second end to which the reference potential is applied. When the second power supply is turned on before the first power supply, the potential obtained from the connection point realizes the first power supply system.

According to claim 9 of the present invention,
The semiconductor integrated circuit according to claim 2, wherein the power supply circuit includes a cathode connected to the connection point and an anode connected to the second connection point. It further has a limiting diode.

A tenth aspect of the present invention is the semiconductor integrated circuit according to any one of the second, fifth and eighth aspects, wherein the reference potential and the reference potential with respect to It further comprises an internal circuit driven by a potential having a potential difference of one. The first circuit and the second circuit function as peripheral circuits for the internal circuit, and the internal circuit is supplied with a third power source separately from the first power source.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit with a signal level converting function according to a first embodiment of the present invention.

An internal circuit is connected to the input / output terminal 1 via an input buffer 10. Further, the input / output terminal 1 is connected via an output buffer 9 to a control terminal 2 which receives the control signal IN1 from the internal circuit and an input terminal 3 which receives the output signal IN2 from the internal circuit. Further, an electrostatic protection circuit 11 is connected to the input / output terminal 1.

The electrostatic protection circuit 11 is in a low impedance state when a high potential external input signal is input from the input / output terminal 1, and is in a high impedance state when a low potential or operating voltage external input signal is input. By doing so, it works to protect the input / output circuit from electrostatic damage. The electrostatic protection circuit 11 includes, for example, a junction diode on a substrate,
It is formed with a structure in which a diffusion region and a resistance element using a polysilicon layer are combined.

In FIG. 1, “VDD1 ←” indicates the range of the circuit driven by the first power supply potential VDD1 which is the power supply voltage of the internal circuit, and “VDD2 →” indicates the range of the circuit driven by the second power supply potential VDD2. . The power supply potential point 42 is the second
Power supply potential VDD2 is supplied, and ground potential point 5 is ground potential G
Supply ND. Here, VDD2>VDD1> GND.

The input buffer circuit 10 has a second power supply potential V
"H" level, "L" by DD2 and ground potential GND
An external input signal whose level is regulated is supplied to the first power supply potential VD.
A circuit for converting the signal level into a signal whose "H" level and "L" level are defined by D1 and the ground potential GND;
It is composed of an input driver circuit.

The output buffer 9 comprises an input / output control circuit 6, a signal level conversion circuit 7 and a buffer circuit 8a, and the control terminal 2 and the input terminal 3 are connected to the input / output control circuit 6.

The input / output control circuit 6 includes inverter gates G1, G2, G3 and 2-input NOR gates G4, 2
The input NAND gate G5 constitutes a tri-state type input / output control circuit.

The input ends of the inverter gates G1 and G2 are
Each is connected to the control terminal 2 and the input terminal 3. The input end of the inverter gate G3 is connected to the output end of the inverter gate G1. The first and second input ends of the NOR gate G4 are respectively connected to the inverter gate G
3 is connected to the output end of the inverter gate G2. The first and second input ends of the NAND gate G5 are connected to the output end of the inverter gate G1 and the output end of the inverter gate G2, respectively.

The signal level conversion circuit 7 includes inverter gates G6 to G11 and PMOS transistors Q1 and Q.
2, Q5, Q6 and NMOS transistors Q3, Q4
Q7 and Q8 form a latch type signal level conversion circuit.

The input ends of the inverter gates G6 and G7 are connected to the output end of the NOR gate G4, and the input end of the inverter gate G8 is connected to the output end of the inverter gate G6.

The input ends of both the inverter gates G9 and G10 are connected to the output end of the NAND gate G5, and the input end of the inverter gate G11 is connected to the output end of the inverter gate G9.

The source electrode of the PMOS transistor Q1 is connected to the power supply potential point 42, the gate electrode thereof is connected to the connection point N13, and the drain electrode thereof is connected to the drain electrode of the NMOS transistor Q3. PMOS transistor Q
The source electrode of 2 is the power supply potential point 42, and the gate electrode is NM
The drain electrode of the OS transistor Q3 is connected to the connection point N13. NMOS
The source electrode of the transistor Q3 is connected to the ground potential point 5, the gate electrode is connected to the output terminal of the inverter gate G8 via the connection point N11, and the drain electrode is connected to the drain electrode of the PMOS transistor Q1. The source electrode of the NMOS transistor Q4 is connected to the ground potential point 5, the gate electrode is connected to the output terminal of the inverter gate G7 via the connection point N12, and the drain electrode is connected to the connection point N13.

The source electrode of the PMOS transistor Q5 is connected to the power supply potential point 42, the gate electrode thereof is connected to the connection point N23, and the drain electrode thereof is connected to the drain electrode of the NMOS transistor Q7. PMOS transistor Q
The source electrode of 6 is the power supply potential point 42, and the gate electrode is NM.
The drain electrode of the OS transistor Q7 is connected to the connection point N23, respectively. NMOS
The source electrode of the transistor Q7 is connected to the ground potential point 5, and the gate electrode is connected to the inverter gate G11 via the connection point N21.
The drain electrode is connected to the output terminal of the PMOS transistor Q5
Are respectively connected to the drain electrodes of. NMOS
The source electrode of the transistor Q8 is connected to the ground potential point 5, and the gate electrode is connected to the inverter gate G10 via the connection point N22.
The drain electrode is connected to the connection point N23 at the output end of each.

The first half of the input / output control circuit 6 and the signal level conversion circuit 7 (the portion composed of the inverter gates G6 to G11) operates by being supplied with the first power supply potential VDD1 and the ground potential GND. Although omitted for the sake of simplicity, the power supply potential point 41 and the ground potential point 5 are connected to all of the gates G1 to G11, and their functions are exhibited.

On the other hand, the latter half of the signal level conversion circuit 7 (M
The second power supply potential VDD2 and the ground potential GND are applied to the portion constituted by the OS transistors Q1 to Q8) and the buffer circuit 8a to operate.

Inverter gates G1 to G3 and G6 to G1
1 has a CMOS structure and is driven by the first power supply potential VDD1 and the ground potential GND. MOS transistor Q1
Q8 is driven by the second power supply potential VDD2 and the ground potential GND. Inverter gate G to avoid dielectric breakdown
1 to G3, G6 to G11, and MOS transistors Q1 to Q8, rather than the gate insulating films of the MOS transistors.
The gate insulating film is thicker.

The buffer circuit 8a is composed of a push-pull circuit having inverter gates G12 to G18 having a CMOS structure and a final stage composed of NMOS transistors Q9a and Q10.

The input end of the inverter gate G12 is connected to the signal level conversion circuit 7 via a connection point N13.
The input end of the inverter gate G14 is connected to the output end of the inverter gate G12 via a connection point N14. The input end of the inverter gate G16 is connected to the output end of the inverter gate G14 via a connection point N15. The input end of the inverter gate G18 is connected to the output end of the inverter gate G16 via a connection point N16. The output end of the inverter gate G18 is connected to the gate electrode of the NMOS transistor Q9a. That is, the connection point N13 and NMO
An even number of stages of inverter gates are interposed between the gate electrode of the S transistor Q9a and the potential corresponding to the same logic as the potential applied to the connection point N13 is NM.
It is applied to the gate electrode of the OS transistor Q9a.

The input end of the inverter gate G13 is connected to the signal level conversion circuit 7 via a connection point N23.
The input end of the inverter gate G15 is connected to the output end of the inverter gate G13 via a connection point N24. The input end of the inverter gate G17 is connected to the output end of the inverter gate G15 via a connection point N25. The output terminal of the inverter gate G17 is an NMOS transistor Q10.
Connected to the gate electrode of. That is, the connection points N23 and N
An odd number of stages of inverter gates are interposed between the gate electrode of the MOS transistor Q10 and a potential corresponding to the logic complementary to the potential applied to the connection point N23 is applied to the gate electrode of the NMOS transistor Q10. Will be done.

The final stage of the buffer circuit 8a is composed of an NMOS push-pull buffer. The source electrode of the NMOS transistor Q9a is the input / output terminal 1, the gate electrode is the connection point N17, and the drain electrode is the power supply potential point 42.
, Respectively. NMOS transistor Q10
Has a source electrode at a ground potential point 5 and a gate electrode at a connection point N.
26, and the drain electrode is connected to the input / output terminal 1.

In order to avoid dielectric breakdown, the gates G1 to G
MOS forming the inverter gates G12 to G18 rather than the gate insulating film of the MOS transistor forming 11
The gate insulating films of the transistors and the MOS transistors Q9a and Q10 are thicker.

The bypass power supply circuit 12 is provided between the power supply potential points 41 and 42, and is composed of diodes D1 and D2 connected in series between them. You. That is, the cathode of the diode D2 is at the power supply potential point 41, and the anode of the diode D1 is at the power supply potential point 42.
The anode of the diode D2 is connected to the cathode of the diode D1.

The operation of the circuit configured as described above will be described. The semiconductor integrated circuit shown in FIG. 1 transmits a signal from an internal circuit of the LSI to a device outside the LSI while converting the signal level. That is, the level of the signal supplied from the internal circuit of the LSI operating in the first power supply system to which the first power supply potential VDD1 and the ground potential GND are supplied is converted, and the second power supply potential VDD2 and the ground potential GND are supplied. To a device external to the LSI that operates in the second power supply system.

In the normal operating state, the first power supply potential VDD
Both 1 and the second power supply potential VDD2 are applied. Therefore, the operation of the circuit shown in FIG.

First, the case where the control signal IN1 is at the "L" level will be described. When the output signal IN2 is at "L" level, both the NOR gate 4 and the NAND gate G5 of the input / output control circuit 6 output "L" level. Therefore, the NMOS transistors Q3 and Q7 are turned off, and the NMOS transistors Q4 and Q8 are turned on. Therefore, the PMOS transistor Q1 is on, the PMOS transistor Q2 is off, the PMOS transistor Q5 is on,
The PMOS transistor Q6 turns off.

When the transistors are turned on and off, the connection points N13 and N23 are both provided with the "L" level. Therefore, the connection points N17 and N26 are supplied with "L" level and "H" level, respectively, and the NMO
S transistor Q9a is off, NMOS transistor Q
10 is turned on, and the "L" level is given to the input / output terminal 1.

Next, the case where the control signal IN1 is at "L" level and the output signal IN2 is at "H" level will be described. The NOR gate 4 and the NAND gate G5 of the input / output control circuit 6 both output "H" level. Therefore, the NMOS transistors Q3 and Q7 are turned on and the NMOS transistors Q4 and Q8 are turned off. Therefore, the PMOS transistor Q1 is off, the PMOS transistor Q2 is on, the PMOS transistor Q5 is off,
The PMOS transistor Q6 turns on.

When the transistors are turned on and off, the connection points N13 and N23 are both provided with the "H" level. Therefore, "H" level and "L" level are given to the connection points N17 and N26, respectively, and the NMO
S transistor Q9a is on, NMOS transistor Q
10 is turned off, and the "H" level is applied to the input / output terminal 1.

As described above, when the control signal IN1 is at "L" level, the same logic level as the output signal IN2 is output to the input / output terminal 1.

On the other hand, when the control signal IN1 is at "H" level, the NOR gate 4 and the NAND of the input / output control circuit 6 are irrespective of whether the output signal IN2 is at "H" level or "L" level. The gate G5 outputs "L" level and "H" level, respectively. Therefore, the NMOS transistors Q4 and Q7 are turned on, and the NMO
The S transistors Q3 and Q8 are turned off. Because of this PMO
S transistor Q1 is on, PMOS transistor Q2
Is off, the PMOS transistor Q5 is off, and the PMOS transistor Q6 is on.

By turning on and off these transistors, the connection points N13 and N23 are supplied with "L" level and "H" level, respectively. Therefore, the connection point N1
"L" level is given to both 7 and N26, and NM
Both the OS transistors Q9a and Q10 are turned off, and the input / output terminals are in a high impedance state as seen from the external circuit.

If the second power supply potential VDD2 is applied without the first power supply potential VDD1 being applied, the first
While the logic levels of the first half of the input / output control circuit 6 and the signal level conversion circuit 7 operating in the power supply system are not determined, the second half of the signal level conversion circuit 7 operating in the second power supply system sets the logic level to the buffer circuit 8a. Will be communicated.

At this time, a set of logic levels given to the connection points N13 and N23 is ("H", "H"), ("L",
There is no problem if it is either "L") or ("L" level, "H" level), but there is a possibility that it will be ("H", "L"). In this case, the NMOS transistor Q9a, Q
As described above, the problem that a through current flows through 10 occurs.

In order to avoid such a state, the bypass power supply circuit 12 lowers the second power supply potential VDD2 applied to the power supply potential point 42 and applies a predetermined voltage to the power supply potential point 41.

For example, the first power supply potential VDD1 is 3.3V
The second power supply potential VDD2 is selected to be 5V. When the second power supply potential VDD2 is applied without the first power supply potential VDD1 being applied, the diodes D1, D
A current flows from the power supply potential point 42 to the power supply potential point 41 in the bypass power supply circuit 12 that is a serial connection of the two. Since the inverter gates G1 to G3 and G6 to G11 have a CMOS structure, ideally no current flows, but a leak current (transient shoot-through current, subthreshold current,
A small amount of junction leakage current will flow.

By the flow of this current, the diodes D1 and D2 both support the voltage VB of about 0.7V, and about 3.6V is applied to the power supply potential point 41 even if the first power supply potential VDD1 is not applied. The electric potential of will be given.
Normally, as a recommended operating condition for the first power supply potential VDD1, the value is a reference voltage (here, 3.3 V) ±
Since it is 10%, the value of 3.6V is within the recommended range.

Therefore, the logic level internal circuits in the first half of the input / output control circuit 6 and the signal level conversion circuit 7 operate normally, and the problem that a through current flows through the transistors Q9a and Q10 can be avoided.

Embodiment 2 In the first embodiment, the circuit of the first power supply system operates normally even after the first power supply potential VDD1 (3.3 V) is applied to the power supply potential point 41. However, due to the functions of the diodes D1 and D2, the power supply potential point 4
It is also conceivable that a current will flow through the bypass power supply circuit 12 in an attempt to apply the potential of 3.6 V to 1. This causes unnecessary current to flow, which is not desirable in terms of power consumption. The second embodiment excludes such a possibility.

FIG. 2 is a circuit diagram showing the configuration of the input / output circuit of the semiconductor integrated circuit with a signal level converting function according to the second embodiment of the present invention. The circuit shown here is the bypass power supply circuit 12 of the circuit shown in the first embodiment.
Is replaced with the bypass power supply circuit 13.

The bypass power supply circuit 13 has a structure in which a PMOS transistor Q11 is added to the bypass power supply circuit 12. That is, the drain and source of the transistor Q11 are connected to the power supply potential point 41 and the cathode of the diode D2, respectively, the gate is connected to its drain, and the back gate is connected to the power supply potential point 42.
In order to avoid dielectric breakdown, the gate insulating film of the MOS transistor Q11 is thicker than the gate insulating film of the MOS transistors forming the inverter gates G1 to G11.

When the second power supply potential VDD2 is applied without the first power supply potential VDD1 being applied, the gate potential of the transistor Q11 is sufficiently low and the transistor Q11 is turned on. Therefore, the bypass power supply circuit 13 is the bypass power supply circuit 1
Similarly to the second power source potential point 41, the second power source potential V
A predetermined voltage can be applied to the power supply potential point 41 by stepping down from DD2.

After that, when the first power supply potential VDD1 is applied to the power supply potential point 41, the gate potential becomes the first potential.
It rises to the power supply potential VDD1. Moreover, the diode D
Due to the series connection of 1 and D2, the back gate of the transistor Q11 is supplied with a potential higher than the source by a voltage of 2VB, and the absolute value of the threshold voltage of the transistor Q11 increases. Therefore, the transistor Q11 is turned off, and it is possible to prevent unnecessary current from flowing through the bypass power supply circuit 13.

Embodiment 3 3 is a circuit diagram showing a configuration of an input / output circuit of a semiconductor integrated circuit with a signal level converting function according to a third embodiment of the present invention. The circuit shown here has a configuration in which the bypass power supply circuit 12 of the circuit shown in the first embodiment is replaced with a bypass power supply circuit 14.

The bypass power supply circuit 14 has a structure in which a resistor R1 is added in series to the bypass power supply circuit 12. Therefore, when the second power supply potential VDD2 is turned on without the first power supply potential VDD1 being turned on, a voltage drop of 2VB occurs due to the diodes D1 and D2, and a voltage drop due to the current flowing through the resistor R1 also occurs. can get. In other words, the resistor R1 controls the amount of current flowing through the bypass power supply circuit 14, and thus controls VB.

By adjusting the value of the resistor R1 according to the leak current generated in the circuit of the first power supply system, the potential applied to the power supply potential point 41 by the bypass power supply circuit 14 is lower than the first power supply potential VDD1. It can be set higher than 0.9VDD1 (10% lower than the reference value). As a result, even if the first power supply potential VDD1 is not turned on, the circuit of the first power supply system is normally operated, and if the first power supply potential VDD1 is turned on thereafter, the bypass power supply circuit 14 is not required. It is possible to prevent current from flowing.

Embodiment 4 Fourth Embodiment FIG. 4 is a circuit diagram showing a configuration of an input / output circuit of a semiconductor integrated circuit with a signal level converting function according to a fourth embodiment of the present invention. The circuit shown here has a configuration in which the bypass power supply circuit 12 of the circuit shown in the first embodiment is replaced with a bypass power supply circuit 15.

The bypass power supply circuit 15 is composed of diodes D1 to Dn connected in series in the same direction. The anode of the diode D1 is connected to the power supply potential point 42, and the cathode of the diode Dn is connected to the ground potential point 5, respectively.

Then, the kth diode Dk and the (k + 1) th diode D (k
The power supply potential point 41 is connected at a connection point N40 with (+1).

The operation of the bypass power supply circuit 14 presented in the third embodiment depends on the current flowing in the bypass power supply circuit 14 (that is, the leak current in the circuit of the first power supply system), and the value of the resistor R1. Is adjusted to control the potential applied to the power supply potential point 41. In other words, once the value of the resistor R1 is fixed, the potential applied to the power supply potential point 41 is unlikely to be constant depending on the circuit of the first power supply system.

However, most of the current flowing in the bypass power supply circuit 15 is the current Is flowing between the power supply potential point 42 and the ground potential point 5, the amount of which is controlled by the number n of diodes, It hardly depends on the leak current of the power supply circuit.

Therefore, if the number n of diodes is determined, the magnitude of the voltage supported by each of the diodes D1 to Dn becomes constant, and the potential applied to the power supply potential point 41 can also be made constant.

Of course, it is desirable that the potential applied to the power supply potential point 41 be set lower than the first power supply potential VDD1. This is to prevent unnecessary current from flowing to the bypass power supply circuit 15 when the first power supply potential VDD1 is applied to the power supply potential point 41. Also, 0.9VDD1
A value higher than (a value 10% lower than the reference value) is desirable for normal operation of the circuit of the first power supply system.

If the number of diodes n is increased,
It is possible to reduce the current Is to suppress power consumption, reduce the voltage VB, and finely control the potential applied to the power supply potential point 41. However, if the current Is is made too small, the operation of the bypass power supply circuit 15 is affected by the leak current of the circuit of the first power supply system, which is not desirable. Therefore, it is desirable to set an appropriate number n.

Embodiment 5 5 is a circuit diagram showing a configuration of an input / output circuit of a semiconductor integrated circuit with a signal level converting function according to a fifth embodiment of the present invention. The circuit shown here has a configuration in which the bypass power supply circuit 12 of the circuit shown in the first embodiment is replaced with a bypass power supply circuit 16.

The bypass power supply circuit 16 has a structure in which the diodes D (k + 1) to Dn of the bypass power supply circuit 15 are replaced with a resistor R2.

It is obvious that the bypass power supply circuit 16 having such a configuration can also perform the same operation as the bypass power supply circuit 15. Moreover, the number of diodes required for the configuration can be reduced.

By controlling the value of the resistor R2, the amount of current flowing through the bypass power supply circuit 16 can be adjusted. The desired level of the potential applied to the power supply potential point 41 is the same as in the fifth embodiment.

Sixth Embodiment 6 is a circuit diagram showing a configuration of an input / output circuit of a semiconductor integrated circuit with a signal level converting function according to a sixth embodiment of the present invention. The circuit shown here has a configuration in which the bypass power supply circuit 12 of the circuit shown in the first embodiment is replaced with a bypass power supply circuit 17.

The bypass power supply circuit 17 has a structure in which the diodes D (k + 1) to Dn of the bypass power supply circuit 15 are replaced with a resistor R2 and the diodes D1 to Dk are replaced with a resistor R3.

In the bypass power supply circuit 17, the resistance R
2 and R3, the second power supply potential VDD2 and the ground potential GN
It is possible to divide the voltage between D and D to give a predetermined potential to the power supply potential point 41. Since the voltage is divided by resistance,
Compared to the case where a diode is used, the potential applied to the power supply potential point 41 can be easily controlled, and the degree of freedom in design can be increased.

By controlling the sum of the values of the resistors R2 and R3, the amount of current flowing through the bypass power supply circuit 17 can be adjusted. The desired level of the potential applied to the power supply potential point 41 is the same as in the fifth embodiment.

Embodiment 7 7 is a circuit diagram showing a configuration of an input / output circuit of a semiconductor integrated circuit with a signal level converting function according to a seventh embodiment of the present invention. The circuit shown here has a configuration in which the bypass power supply circuit 12 of the circuit shown in the first embodiment is replaced with a bypass power supply circuit 18.

The bypass power supply circuit 18 is composed of a diode DR and a bypass power supply circuit 19 connected in series. The anode of the diode DR is an LSI
An external power supply 20 that is provided outside and supplies the potential VDD1
Connected to 0. The cathode of the diode DR is connected to the power supply potential point 42 via the bypass power supply circuit 19. Further, the cathode of the diode DR is directly connected to the power supply potential point 41.

Bypass power supply circuit 19 may be any of bypass power supply circuits 12 to 17 disclosed in the first to sixth embodiments. When the bypass power supply circuits 15 to 17 are used as the bypass power supply circuit 19, the connection point N40 is connected to the anode of the diode DR.

Only by using the bypass power supply circuit 19 between the power supply potential points 41 and 42, the external power supply 2
When the second power source potential VDD2 is turned on without the first power source potential VDD1 to be turned on by 00, the lower the output impedance of the external power source 200, the more the power source potential point 42 from the power source potential point 42 via the bypass power source supply circuit 19. The current flowing to the external power supply 200 increases. When this current increases, the potential applied to the power supply potential point 41 decreases.

In the present embodiment, by providing diode DR in the direction of suppressing this current, the potential applied to power supply potential point 41 can be maintained at the level required by the circuit of the first power supply system.

Embodiment 8 FIG. FIG. 8 is a conceptual diagram illustrating the configuration of a semiconductor integrated circuit. Usually, the internal circuit 20 is surrounded by the input / output circuit 30. As the input / output circuit 30, a circuit including the output buffer 9 and the input buffer 10 can be adopted.

A power supply main trunk 31 is laid above the input / output circuit 30 (in the direction perpendicular to the plane of the drawing), and the input / output circuit 3 is provided therethrough.
A power supply potential point 41 is connected to 0. The internal circuit 20 is also connected to the power supply potential point 41 via the power supply master 31. In order to avoid complication, here, the power supply potential point 42
Is not shown in the figure.

When the bypass power supply circuit 19 (or 18) is added to the semiconductor integrated circuit having such a structure, the following problems remain.

Normally, regarding the input / output circuit 30, the potential to be applied to the power supply potential point is, for example, ± 1 with respect to the reference potential.
A range of about 0% is allowed. Therefore, the power supply potential point 41
0.9VDD1 (for example, 2.97V) is applied to
1.1 VDD2 (for example, 5.5 V) at the power supply potential point 42
Is allowed for the input / output circuit 30 itself.

However, in that case, the voltage applied to the bypass power supply circuit 19 (or 18) becomes large,
Even when a normal (permissible range) potential is applied not only to the power source potential point 42 but also to the power source potential point 41, the current flowing therethrough becomes large. This makes the potential of the power supply potential point 41 unstable.

Since not only the input / output circuit 30 but also the internal circuit 20 is connected to the power supply potential point 41 via the power supply main point 31, fluctuations in the potential of the power supply potential point 41 make the operation of the internal circuit 20 unstable. There is a possibility.

FIG. 9 is a conceptual diagram showing the structure of a semiconductor integrated circuit according to the eighth embodiment of the present invention. Here, the power supply potential points 41a and 41b are both the first power supply potential VDD1.
Are supplied separately.

The input / output circuit 30 is connected to the power supply potential point 41a via the power supply master 31 and the internal circuit 20 is connected to the power supply potential point 41b. The bypass power supply circuit 19 (or 18) is provided between the power supply potential points 42 and 41a.

Therefore, even if the current flowing through the bypass power supply circuit 19 (or 18) increases and the potential of the power supply potential point 41a becomes unstable, the influence is transmitted to the internal circuit 20 via the power supply master 31. Therefore, the above problems can be avoided.

[0103]

EXAMPLES In the first to fifth embodiments described above, the diode can be realized by diode connection of the MOS transistor. In order to avoid dielectric breakdown, the gate insulating film of the MOS transistor used at this time is a MOS that constitutes the inverter gates G1 to G3 and G6 to G11.
It is desirable to make the thickness thicker than the gate insulating film of the transistor.

10 to 16 show modifications of Embodiments 1 to 7 of the present invention, respectively. 10 to 1
The circuit shown by 6 has a configuration in which the buffer circuit 8a of the circuits shown in FIGS. 1 to 7 in the first to seventh embodiments is replaced with a buffer circuit 8b.
The buffer circuit 8b is different only in that the inverter gate G18 and the NMOS transistor Q9a of the buffer circuit 8a are replaced with a PMOS transistor Q9b. Therefore, even if such modifications are performed, the same effects as those of the first to seventh embodiments can be obtained.

[0105]

According to the first aspect of the present invention, the first circuit outputs a normal logical value even when the second power source is turned on before the first power source. . Therefore, it is possible to avoid a failure caused by giving an abnormal logic value to the second circuit.

According to the second aspect of the present invention, since the diode supports a predetermined voltage, the voltage can be dropped from the second power supply.

According to the third aspect of the present invention, the current flowing in the power supply circuit is substantially regulated by the first and second diode groups. Therefore, a desired potential can be applied to the connection point without depending on the leak current of the first circuit or the like.

According to the fourth aspect of the present invention, the current flowing through the power supply circuit is substantially regulated by the resistor and the first diode group. Therefore, a desired potential can be applied to the connection point without depending on the leak current of the first circuit or the like.

According to the fifth aspect of the present invention, when the first power source is turned on after the second power source is turned on, unnecessary current flowing in the power supply circuit is suppressed by the current limiting element. To be done.

According to the sixth aspect of the present invention, the resistor controls the amount of current flowing through the power supply circuit, thereby controlling the voltage supported by the diode.

According to the seventh aspect of the present invention, when the first power source is turned on after the second power source is turned on, the PMOS transistor is turned off and an unnecessary current is supplied to the power supply circuit. Does not flow.

According to the eighth aspect of the present invention, by configuring the power supply circuit with the resistor, it is possible to increase the degree of freedom in design for realizing the first power supply system.

According to the ninth aspect of the present invention, the current flowing to the first power supply through the power supply circuit is suppressed by the current limiting diode, and the potential required for realizing the first power supply system is lowered. Can be avoided.

According to the tenth aspect of the present invention, even if the current flowing in the power supply circuit increases and the potential required to realize the first power supply system for the peripheral circuits becomes unstable, Since the third power supply is separately provided, the operation of the internal circuit does not become unstable.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a sixth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a seventh embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of an eighth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a structure of an eighth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 11 is a circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 12 is a circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 13 is a circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 14 is a circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 15 is a circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 16 is a circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 17 is a circuit diagram showing a conventional technique.

FIG. 18 is a cross-sectional view showing a conventional technique.

FIG. 19 is a circuit diagram showing a conventional technique.

FIG. 20 is a sectional view showing a conventional technique.

[Explanation of symbols]

41, 41a, 41b, 42 power supply potential point, 5 ground potential point, 6 input / output control circuit, 7 signal level conversion circuit, 8a, 8b buffer circuit, 12 to 17 bypass power supply circuit, D1 to Dn diode, R1 to R3
resistance.

Claims (10)

[Claims] 1. A first power supply system is required for driving, a first circuit that outputs at least one logical value, and a second power supply system is required for driving, and an output of the first circuit A second circuit that receives the logical value and performs logical processing, the first power supply system being realized by a first power supply having a first potential difference with respect to a reference potential, and the second power supply system being the reference power source. It is realized by a second power source having a second potential difference larger than the first potential difference with respect to a potential, and the first power source system is configured to operate when the second power source is turned on before the first power source. A semiconductor integrated circuit realized also by a potential stepped down from a second power supply. 2. A power supply circuit having a first diode group including at least one diode connected in series in the same direction, further comprising an anode of one of the first diode groups closest to the second power source. When the second power supply is connected to the second power supply, the cathode of the one of the first diode group farthest from the second power supply is connected to the connection point, and the second power supply is turned on before the first power supply. Depending on the potential obtained from the connection point
The semiconductor integrated circuit according to claim 1, wherein a power supply system is realized. 3. The power supply circuit further includes a second diode group including at least one diode connected in the same direction as the first diode group, and the second power source of the second diode group is the most second power source. 3. The semiconductor integrated circuit according to claim 2, wherein the anode of the one closest to the second connection point is connected to the first connection point, and the reference potential is applied to the cathode of the one of the second diode groups farthest from the second power supply. 4. The semiconductor integrated circuit according to claim 2, wherein the power supply circuit further includes a resistor including one end connected to the first connection point and the other end to which the reference potential is applied. 5. A power supply circuit having a first diode group including at least one diode connected in series in the same direction, further comprising: an anode of one of the first diode groups closest to the second power source. The second power supply is connected to the second power supply, and the power supply circuit has a first end connected to the cathode of one of the first diode groups farthest from the second power supply and a second end connected to a connection point. Further comprising a current limiting element including, when the second power source is turned on before the first power source, by the potential obtained from the connection point, the first
The semiconductor integrated circuit according to claim 1, wherein a power supply system is realized. 6. The semiconductor integrated circuit according to claim 5, wherein the current limiting element is a resistor. 7. The current limiting element is connected to a gate and a drain commonly connected to the first connection point, a source connected to the first end of the current limiting element, and a second power supply. 6. The semiconductor integrated circuit according to claim 5, which is a PMOS transistor having a back gate. 8. A first end connected to the second power supply,
A first resistor including a second end connected to the first connection point;
It further comprises a power supply circuit having a second resistance including a first end connected to the connection point and a second end to which the reference potential is applied, and the second power supply is ahead of the first power supply. When it is turned on, the electric potential obtained from the connection point causes
The semiconductor integrated circuit according to claim 1, wherein a power supply system is realized. 9. The power supply circuit according to claim 2, further comprising a current limiting diode including a cathode connected to the connection point and an anode connected to the first power supply. The semiconductor integrated circuit according to 1. 10. An internal circuit driven by the reference potential and a potential having the first potential difference with respect to the reference potential, wherein the first circuit and the second circuit function as peripheral circuits for the internal circuit. The semiconductor integrated circuit according to claim 2, wherein a third power supply is applied to the internal circuit separately from the first power supply.