JP2001274675A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a semiconductor integrated circuit that includes a level conversion circuit having a high degree of permissibility of an element characteristic with low power consumption that converts a very small logic level such as about 0.5 V into about 1 V to 3 V being a conventional logic level. SOLUTION: The level conversion circuit is provided with a P-channel latch consisting of common gate P-channel MOSFETs 100, 101 and N-channel MOSFETs 102, 103 that receive complementary signals 10A, 10B from a logic circuit and of P-channel MOSFETs 104, 105 and with an N-channel latch consisting of N-channel MOSFETs 106, 107. Leading an output of the logic circuit operated at a low voltage and its inverted logic output to each latch via a common gate circuit can drive two FETs configuring each latch by complementary inputs so as to enhance the gain characteristic of each latch.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit which operates using a plurality of power supplies.

[0002]

2. Description of the Related Art In recent years, the degree of integration of semiconductor integrated circuits has been remarkably improved. In a gigabit-class semiconductor memory, hundreds of millions of semiconductor elements per chip, and in a 64-bit microprocessor, several million to one million chips per chip. Ten million semiconductor elements have been integrated. Improvement in the degree of integration is achieved by miniaturization of elements, and 1 Gbit DRAMs (Dynam
ic Random Access Memory), a MO with a gate length of 0.15 μm is used.
When an S transistor is used and the degree of integration is further increased, a value of 0.1 is obtained.
MOS transistors having a gate length of 1 micron or less will be used.

In such a fine MOS transistor, deterioration of transistor characteristics due to generation of hot carriers and TDDB (Time Dependent Diode) are considered.
Insulation film breakdown due to electric breakdown occurs. In addition, in order to suppress a decrease in threshold voltage due to a shortened channel length, when the impurity concentration in the substrate region or the channel region is increased, the junction voltage between the source and the drain is reduced. In order to maintain the reliability of these fine elements, it is effective to lower the power supply voltage. That is, generation of hot carriers is prevented by weakening the horizontal electric field between the source and the drain, and TDDB is prevented by weakening the vertical electric field between the gate and the bulk. Further, by lowering the power supply voltage, the reverse bias applied to the junction between the source and the bulk and the junction between the drain and the bulk is reduced to cope with the reduction in the withstand voltage.

[0004] In recent years, the market for portable information devices has been remarkably expanding. 2. Description of the Related Art In portable information devices, lightweight and high energy density power supplies represented by lithium ion batteries are mainly used. However, a lithium ion battery has a voltage of about 3 V, which is higher than the withstand voltage of the above-mentioned micro MOS transistor, and when applied to a circuit using such a micro transistor, it is necessary to lower the voltage by a power supply voltage conversion circuit. Further, the power consumption of a CMOS circuit used in a logic circuit during operation is proportional to the operating frequency and proportional to the square of the power supply voltage. Therefore, lowering the power supply voltage has a remarkable effect on lowering chip power consumption. .

Therefore, in order to use portable equipment for a longer time, a battery with a high energy density, a high-efficiency power conversion transformer, and an integrated circuit operating at a low voltage are required. It is desirable to use the stepped-down power supply voltage for a microprocessor and a baseband LSI which consume particularly large power from the viewpoint of reducing the power consumption of the LSI.

On the other hand, in a portable information device, a storage element such as a DRAM or an SRAM is essential in addition to the above-described logic circuit. In the DRAM, however, an SRAM is required to secure a sufficient amount of electric charge in a cell and to improve soft error resistance. In order to avoid the speed degradation at the time of low power supply voltage operation, a remarkable reduction in power consumption as seen in a logic circuit has not been made.
Elements having a power supply voltage of about 5 V have been put to practical use. However, since a logic circuit and a power supply voltage are greatly different, it is considered that an LSI in which a storage circuit and a logic circuit are mixed has a multi-power supply configuration for supplying various power supply voltages at present and in the future.

FIG. 4 shows a configuration of a semiconductor integrated circuit 405 for portable information equipment in which a storage circuit and a logic circuit are integrated on the same chip, and a power supply system thereof. It comprises a lithium battery (lithium ion secondary battery) 400, a power supply voltage conversion circuit 401, a logic circuit 402, an on-chip storage circuit 403, and a level conversion circuit 404. The power supply voltage converter 401 converts the 3V output power supply voltage of the lithium battery 400 to a 0.5V voltage, and supplies a 0.5V power supply to the logic circuit 402. On the other hand, the on-chip storage circuit 403 requires a power supply voltage of 1 V or more for its operation.
00 is supplied as it is. Further, a 3V power supply and a 0.5V power supply are supplied to the level conversion circuit 404 for connecting the storage circuit 403 and the logic circuit 402.

In the configuration shown in FIG. 4, power consumption during operation can be reduced by setting the power supply voltage of the logic circuit 402 to 0.5 V. However, if the power supply voltage of a general CMOS circuit that operates at a power supply voltage of 3 V to 2 V is simply reduced, there is a problem that the operation speed of the element is reduced or the device does not operate.
To solve this, it is necessary to lower the threshold voltage of the MOS transistor as the power supply voltage decreases. For example, 0.5V
To configure a logic circuit that operates with a low power supply voltage,
It is necessary to use an FET having a threshold voltage of about 0.1 to 0.2 V in absolute value and about 1/3 of the threshold voltage of the conventional FET.

However, at such a low threshold voltage, F
Since the off-leak current of the ET greatly increases, and as a result, the power consumption of the device during standby increases significantly, it is not suitable as a semiconductor integrated circuit for portable information devices as it is.

FIG. 5 is a view in view of the above problem, and supplies four types of power including ground to the semiconductor integrated circuit 506.
The logic circuit 502 integrated on-chip in the semiconductor integrated circuit 506 includes, in addition to the 3V power supply (VDD) and ground (VSS) supplied from the lithium battery 500, VD1 supplied from the power supply voltage conversion circuit 501. And VS1 are connected. Here, the potential difference between the logic circuit power supply VD1 and the logic circuit ground VS1 is set to 0.5V. In such a configuration, the logic circuit 502 is configured by using two power supplies, VD1 and VS1, to reduce power consumption during operation, and to perform p-channel MOSFET 5
09, the p-channel MOSFET 507 is turned on to change from VDD1 to VDD, and the n-channel MOS
The well potential of the FET 510 is changed to the n-channel MOSFET 5
08 to the ON state and change from VS1 to VSS,
Power consumption during standby can be reduced by increasing the absolute value of the threshold voltage of the MOSFETs 509 and 510 in the logic circuit during standby and reducing the leakage current during OFF.

Next, the on-chip storage circuits 503 and 50
The power supplies 4505 are 1) a chip power supply VDD and a chip ground VS supplied from a lithium battery.
S, 2) using the logic circuit power supply VDD and the chip ground VSS, and 3) using the chip power supply VDD and the logic circuit ground VS1. From the viewpoint of power consumption, there are three possible configurations. 2) or 3) wins,
Ultimately, it is determined in consideration of the operating voltage range of the storage circuit. As described above, when the semiconductor integrated circuit 506 is viewed, the logic circuit 502 has the high level VD1 and the low level VS1, and the storage circuit 503 has the high level VD1.
D, low level VSS, high level VDD and low level VSS in the storage circuit 504, high level VDD and low level VS1 in the storage circuit 505, and various logic amplitudes and various logic levels are mixed.

FIG. 6 also considers the problem of leakage current at the time of turning off, and supplies three types of power to the semiconductor integrated circuit 605 and integrates the logic circuit integrated on-chip in the semiconductor integrated circuit 605. A power supply (VD: 1.2 V (3 V for a lithium ion secondary battery)) supplied from a nickel hydrogen secondary battery or a lithium ion secondary battery 600 to 602
D) and the ground (VSS), the logic circuit power supply VD1 (0.5 V) supplied from the power supply voltage conversion circuit 601 is connected to the pseudo power supply line VDDV of the logic circuit via the p-channel MOSFET 603 having a large threshold value. I have.

In this configuration, during standby, necessary information in the logic circuit is saved to the storage circuit 604, and then the gate voltage of the p-channel MOSFET 603 is set to VDD and the MO
The SFET 603 is turned off. At this time, the leakage current is extremely small because it is determined by the off characteristic of the p-channel MOSFET 603 having a large threshold. However, since it is difficult to operate the memory circuit 604 with a power supply of about 0.5 V, the memory circuit 604 is driven by VDD and VSS.
SS, high level VDD and low level VS in the storage circuit
The two types of logical levels S are mixed.

As described above, a power supply system with multiple power supplies is indispensable for an LSI for portable equipment, and a level conversion circuit that converts these different logic levels and consumes low power is required. First, in order to transmit a signal from a semiconductor integrated circuit having a large logic amplitude to a logic circuit having a small logic amplitude, the gate breakdown voltage VBD must be equal to the logic amplitude (VDD−V
By using a MOSFET larger than SS) and using a normal CMOS circuit as shown in FIG. 7, the level conversion can be performed without any problem.

However, it is difficult to convert the signal level of a logic circuit having an extremely low logic amplitude (0.5 V in this example) such as (VD1-VS1) into a large logic amplitude for a storage circuit. Normal C showing
In the MOS inverter circuit, for example, (VDD, VSS), (VD1, VSS), (V
There are various problems in performing sufficient level conversion to DD, VS1). That is, 1) complete level conversion is not performed in a single-stage CMOS inverter, and 2) p-channel MOSFET, n
Since any channel MOSFET cannot be cut off and operates in an on state like a class A amplifier, a steady through current is generated from the power supply to the ground. 3) Multi-stage CM
When the OS inverter is used, power consumption increases, and so on. As another method, using a differential amplifier circuit,
There is also a method of using an intermediate value between VD1 and VS1 as a reference voltage, but 1) a current source is required for a differential amplifier circuit,
2) A CMOS inverter for amplifying the output of the differential amplifier circuit is required, and current consumption is increased in the CMOS inverter stage.

To address this problem, 0.5V to 1V
Document (Sub-1-V Swing Bus Architectur) as a level conversion circuit that converts a logic amplitude of about V to a logic amplitude of about 2 V
e for Future Low-Power ULSIs by Nakagome et.Al., 1
A level conversion circuit (see FIG. 8) shown in 992 VLSI Circuit Symposium, 9-2) has been proposed and has obtained low power consumption characteristics.

The level conversion circuit of this configuration has a common source M
OSFETs 800 and 801 and two identical channel MOs
Although each of the SFETs is composed of crossed latches connecting the gate and the drain of the SFET, the logic amplitude of the gate voltage input between the same channel MOSFETs of each crossed latch is greatly different. When a latch is formed, the driving capabilities of these MOSFETs are greatly different as a result, and it becomes difficult to invert the MOSFET with a weak driving capability. Therefore, in each intersection latch, it is necessary to determine the size of the two MOSFETs in consideration of the driving capability of the two MOSFETs.

As another problem, in the case of this configuration, there is a low tolerance for element characteristics of the level conversion circuit. That is, the element characteristics of the p-channel MOSFET 800 and the n-channel MOSFET 801 are strict, and in order to perform a desired level conversion, for example, a MOSFET having a threshold voltage of about 0 to 0.05 V is required.
1) The necessity of such a special threshold FET complicates the process steps, and 2) the process window is extremely narrow as 100 mV, so that strict process control is required. Increases the cost of the semiconductor integrated circuit.

[0019]

As described above, when an attempt is made to realize a logic LSI including an on-chip memory circuit, which consumes low power during operation and standby (standby) of a portable device, the logic circuit requires The power supply voltage is set as low as about 0.5 V to reduce power consumption by reducing the logic amplitude during operation, and the absolute value of the threshold voltage of the MOSFET in the logic circuit is changed by changing the substrate potential during standby. A configuration in which the leakage current is increased to increase the leakage current or a configuration in which the power supply of the logic circuit is connected to the power supply line through a p-channel MOSFET having a large threshold is used, but the on-chip storage circuit does not operate with the power supply voltage operated by the logic circuit. Therefore, another larger power supply voltage such as using a battery power supply is required.

In this case, various level conversion circuits are required in order to logically connect these circuits. However, the logic amplitude of about 0.5 V is changed to a sufficient logic amplitude for operating the storage circuit. In order to perform the conversion, 1) sufficient level conversion cannot be performed by one stage of the CMOS inverter, 2) C
In a circuit using a plurality of MOS inverters, level conversion is performed, but power consumption is increased. 3) In another level conversion circuit, level conversion is performed, but strict element characteristic management and additional process steps are required. As a result, there is a problem that the cost of the integrated circuit increases.

The present invention has been made in view of the above circumstances, and has as its object to reduce the power consumption of converting a very small logic level of about 0.5 V from a normal logic level of 1 V to about 3 V. Accordingly, an object of the present invention is to provide a semiconductor integrated circuit for realizing a level conversion circuit having a large tolerance for element characteristics.

[0022]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention relates to a semiconductor integrated circuit having first and second power supplies having different levels from each other. One end of each is connected to a second logic output that is an inverted signal, and each gate is connected to one of the first and second power supplies.
And a second FET, and third and fourth FETs of a second conductivity type, one end of which is connected to the other of the first and second power supplies, and the other end of which is connected to the gate of the other. And the other end of each of the first and second FETs of the first conductivity type is connected to the other end of each of the third and fourth FETs of the second conductivity type. 3 or 4
The first characteristic is that the signal at the other end of the FET is output as an output signal.

Further, according to the present invention, the first potential including the ground whose potential levels satisfy the relationship of V1 ≧ V2> V3 ≧ V4 is provided.
To a fourth integrated circuit including a logic circuit section using the second and third power supplies, a source is connected to a first logic output of the logic circuit section, and a gate is connected to the second logic output section. A first n-channel FET connected to the power supply of
A first p-channel FET having a source connected to the first logic output and a gate connected to the third power supply; and a source connected to a second logic output which is an inverted signal of the first logic output. And a second gate whose gate is connected to the second power supply.
And a second p-channel FET having a source connected to the second logic output and a gate connected to the third power supply.
A channel FET, third and fourth p-channel FETs each having a source connected to the first power source and a drain connected to the other gate, and a source connected to the fourth power source. Third and fourth n-channel FETs connected to each other and having their drains connected to a counterpart gate, wherein the first n-channel FE
The drain of T is connected to the drain of the third p-channel FET, the drain of the second n-channel FET is connected to the drain of the fourth p-channel FET, and the drain of the first p-channel FET is connected. Connected to the drain of the third n-channel FET;
The drain of ET is connected to the drain of the fourth n-channel FET, and the two terminals of the drains of the third and fourth p-channel FETs are output as a first level, and the third and fourth n-channel FETs are output. Connect the two drain terminals of the FET to the second
A second feature is that a level conversion circuit for outputting the level is output.

As described above, the output of the low-voltage operation logic circuit and its logically inverted output are respectively connected to the gate-grounded FET.
, And by using the configuration in which the output is connected to two outputs of a cross latch constituted by cross connection of two FETs, the gain characteristics of the cross latch can be improved. The size can be increased, and the power consumption of the circuit can be reduced. In addition, since the circuit margin can be increased by using complementary inputs, restrictions on element characteristics are relaxed.

It is preferable that a buffer circuit that operates with a power supply having a large level difference be provided at an output stage of a cross latch constituted by cross connection of two FETs. As the buffer circuit, in the above-described semiconductor integrated circuit according to the first aspect of the present invention, the other of the first and second power supplies and the third power supply are supplied as operation power supplies,
Alternatively, by using a buffer circuit that outputs an output signal corresponding to a signal at the other end of the fourth FET, for example, a large logic amplitude corresponding to a difference between the first or second power supply and the third power supply can be obtained. Becomes possible. In this case, two n-channel FETs whose source and drain current paths are connected in series between the first or second power supply and the third power supply are used, and the gates of these two n-channel FETs are connected to the respective gates. It is practically preferable to connect the other ends of the third and fourth FETs respectively.

According to a second aspect of the present invention, in a semiconductor integrated circuit, a p-channel FET in which a current path between a source and a drain is connected in series between the first power supply and the fourth power supply. And a buffer circuit including an n-channel FET and one of a first level output and a second level output of the level conversion circuit, the p-channel FET and the n-channel FET constituting the buffer circuit.
By using a configuration commonly connected to the gates of the
It is possible to obtain a large logic amplitude corresponding to the difference between the first power supply and the fourth power supply.

Further, by setting the absolute value of the threshold voltage of each FET in the buffer circuit larger than the absolute value of the threshold voltage of each FET in the level conversion circuit,
Even when the buffer circuit is configured with a large-sized FET, it is possible to suppress the leakage current during standby.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a level conversion circuit provided in a semiconductor integrated circuit according to the first embodiment of the present invention. This semiconductor integrated circuit has a configuration in which a logic circuit operating at a low voltage and a storage circuit operating at a higher voltage than the logic circuit are integrated on one chip, and the level conversion shown in FIG. A circuit will be provided.

This level conversion circuit is provided with a .0 signal from a logic circuit.
This is for converting a logic output level of about 5 V to a level of about 3 V from 1 V and outputting the same to the storage circuit, and inputs p-channel MOSFETs 100 and 101 of grounded gate type to receive complementary signals 10 A and 10 B from the logic circuit, respectively.
And n-channel MOSFETs 102 and 103, a p-channel cross latch composed of p-channel MOSFETs 104 and 105, and an n-channel cross latch composed of n-channel MOSFETs 106 and 107.

The gates of the p-channel MOSFETs 100 and 101 are connected to VS1 which is the ground power supply of the logic circuit, and the gates of the n-channel MOSFETs 102 and 103 are connected to VD1 which is the positive power supply of the logic circuit.
S1 is satisfied. Also, p-channel MOSFET
The sources of 104 and 105 are VDD (VDD ≧ VDD1)
, And the sources of the n-channel MOSFETs 106 and 107 are connected to VSS (VSS ≦ VS1).
The drains of the p-channel MOSFETs 104 and 105 are connected to their respective gates, and similarly, the drains of the
The drains of the channel MOSFETs 106 and 107 are also connected to their respective gates. Level-converted complementary outputs are obtained at the outputs 10C, 10D, 10E, and 10F of the respective cross latches.

According to this level conversion circuit, the input terminal 10
A, V, which is the logic level of the logic circuit input to 10B
D1 and VS1 are level-converted as follows.

10A goes from VS1 to VD1 and 10B goes to V
Consider a case where D1 changes to VS1. n channel M
OSFET 102 is the MOSF in the p-channel crossing latch.
Since the drain of the ET 104 is on until the drain of the ET 104 becomes VD1, when 10A changes from VS1 to VD1, p
The drain of MOSFET 104 in the channel crossing latch changes towards VD1. On the other hand, n-channel MOS
Although FET 103 was off, 10B changes from VD1 to VS1 and turns on, with the result that the drain of MOSFET 105 in the p-channel crossing latch changes toward VS1.

Eventually, when the drain voltage of MOSFET 104 rises to a value near VD1, MOSFE
Since T102 is turned off and separated from the buffer circuit in the logic circuit, the output 10C eventually rises to VDD which is the power supply voltage of the cross latch. In addition, MOSFE
Since T103 is on, 10D which is the drain voltage of the MOSFET 105 becomes VS1.

Therefore, the n-channel MO having the common gate structure is
SFET102,103 and p-channel MOSFET10
4 and 105, using logic levels VD1, VS1 to VDD, VS1.
That is, the level conversion to has been performed. At this time MO
Since the SFET 105 is off, the MOSFET 1
05 consumes almost no current and MOSFET 1
The current consumption via the common gate n-channel MOSF
Since the ET 102 is in the off state, the value is very small, and the static power consumption is almost zero.

Further, as shown in FIG. 1, a first output comprising n-channel MOSFETs 108 and 109 connected in series between VDD and VS1 is provided at each output stage of the p-channel cross latch and the n-channel cross latch. A buffer and a second buffer of opposite phase output composed of n-channel MOSFETs 110 and 111 connected in series between VD1 and VSS are provided. The outputs 10D and 10C are connected to the gates of the n-channel MOSFETs 108 and 109, respectively.
An output out3 having a logic amplitude corresponding to the difference between D and VS1 is obtained.

Here, an n-channel M having a grounded gate structure is used.
OSFET102,103 and p-channel MOSFET1
The level conversion on the side of the cross latch by the transistors 04 and 105 has been described.
T100, 101 and n-channel MOSFET 106, 1
The level conversion from the logic levels VD1 and VS1 to VD1 and VSS is performed by the same function on the side of the crossing latch 07. Further, since the outputs 10E and 10F are respectively connected to the gates of the n-channel MOSFETs 110 and 111, an output out4 having a logical amplitude corresponding to the difference between VD1 and VSS is obtained from the second output buffer in a phase opposite to that of out3. can get.

As described above, the output of the logic circuit operating at a low voltage and its logically inverted output are led to the respective cross latches via the common gate circuit, thereby forming each cross latch.
One FET can be driven by the complementary input, and the gain characteristic of the cross latch can be improved.
P-channel MOSFET 10 constituting a grounded gate circuit
Since 0 and 101 operate complementarily to each other, and the n-channel MOSFETs 102 and 103 constituting the grounded gate circuit operate complementarily to each other, the operation margin of the circuit can be increased, and the restrictions on the element characteristics of the FETs are moderate. Become.

FIG. 2 is a diagram showing a level conversion circuit according to a second embodiment of the present invention. Complementary signal 2 from logic circuit
0A and 20B are input to the same level conversion circuit 20 as in FIG.
0, p-channel MOSFETs 201 and 202, and n-channel MOSFETs 203 and 204, and outputs are obtained from 20G and 20H. p-channel MOSFET
CMO consisting of 201 and n-channel MOSFET 203
The S inverter is used as a first output buffer, and similarly, a p-channel MOSFET 202 and an n-channel MOS
The CMOS inverter composed of the FET 204 is used as a second output buffer having an output opposite in phase to the first output buffer.

First, the complementary outputs 20C, 20D and VD1, V whose level has been converted from logic levels VD1, VS1 to VD1, VSS by the same level conversion circuit 200 as in FIG.
Complementary outputs 20E, 20 having undergone level conversion to SS
F is obtained. Therefore, since 20C and 20E are logically the same, the logic level of VDD or VSS is output to the output terminal 20G by inputting 20C to the gate of the p-channel MOSFET 201 and 20E to the gate of the n-channel MOSFET 203. And level conversion is performed.

Similarly, 20D is a p-channel MOS
20F is connected to the gate of the FET 202 by an n-channel MOSF.
By inputting to the gate of the ET 204, a logically inverted output of the output terminal 20G is obtained from 20H.

Therefore, it is possible to obtain a larger logic amplitude according to the difference between VDD and VSS.

The circuit of the present invention relating to FIGS. 1 and 2 will be specifically described. Here, a description will be given of the results of a study based on a 0.25 μm CMOS process. First, VDD, VDD1, VS1, and VSS are set to 3 V, respectively, as power supply voltages.
1.75V, 1.25V, and 0V. The effective power supply voltage VD1-VS1 of the internal logic circuit is 0.5V, and therefore, the logic amplitude of 0.5V is converted to 3V. Here, the output of the logic circuit is a CMOS inverter output, and the gate width of the p-channel MOSFET is 120 μm.
It is assumed that the gate width of the n-channel MOSFET is 60 μm and the level conversion of the output of the inverter circuit is performed.

First, a gate-grounded p-channel MOSFET 1
The gate width of 00 and 101 is 30 μm, and the gate width of n-channel MOSFETs 102 and 103 is 15 μm.
μm and a p-channel MOSFET in the cross latch
The gate width of each of 104 and 105 is 6 μm, and n-channel MOS
The gate width of the FETs 106 and 107 is 3 μm, the gate width of each of the n-channel MOSFETs 108 to 111 in the output buffer of FIG. 1 is 3 μm, and the gate width of the p-channel MOSFETs 201 and 202 in the output buffer of FIG. The gate width of each of the MOSFETs 203 and 204 is 3 μm. The design center of the threshold voltage of the FET at the time of the study is the same as the internal logic circuit for the MOSFETs 100 to 107 (Vtp1 for the p-channel).
= -0.5V, Vtn1 = 0.15 for n channels
V) and the n-channel MOSF in the output buffer of FIG.
ET 108-111 and M in the output buffer of FIG.
OSFETs 201 to 204 have a slightly larger absolute value (Vtp) for the purpose of reducing the leakage power in the 3V power supply.
2 = -0.5V, Vtn2 = 0.5V).

P-channel MOSFET and n-channel MO
The operation was examined when a 100 MHz signal was input using the threshold voltage of the SFET as a parameter. At this time, as shown in FIG. 3, the substrate potential (well potential) of the gate-grounded MOSFETs 100 to 103 is made equal to the gate potential in order to perform the data inversion in the cross latch at high speed. This is to make the gate-grounded MOSFETs 100 to 103 more likely to be turned off. In practice, the well potential of the MOSFET in the CMOS process or the body potential of the MOSFET in the SOI process should be the same as the gate voltage. Means

As a result, the driving capability of the gate ground circuit for driving the cross latch can be increased with a small element size, and the p-channel MOSFETs 100 and 101 can be formed in the same n-well.
Since the ETs 102 and 103 can be formed in the same p well, the circuit area can be reduced.

The threshold voltage (| Vtp1 |,
Vtn1) was changed from 0 V, which is more than the fluctuation width of the actual process, to 0.25 V, and (| Vtp2 |, Vtn2) was changed from 0.3 V to 0.7 V. However, the speed of the internal logic circuit of the 0.5 V power supply was increased. It becomes a problem (Vtp1, Vtn1)
= 100 except when = (-0.25V, 0.25V)
It was confirmed that it was operating without any problem despite its high-speed operation at MHz. The operating characteristics are Vtp2, Vtn2
It was also found that they hardly depended on. On the other hand, in the conventional circuit shown in FIG.
The threshold voltage of the FETs 701 and 702 is from 0 V to 0.05 V
Only the extremely narrow region was confirmed, and the superiority over the prior art was confirmed from the viewpoint of the allowance for the device characteristics.

The power supply voltage is not limited to the case of four power supplies, but is the case of three power supplies shown in FIG. 6, ie, VDD = 3.
V, VD1 = 0.5V, VSI = 0V, VSS = 0V, VDD = 1.2V, VD1 = 0.5V, VS
Consider the case of I = 0V and VSS = 0V,
It works without any problems.

Each of the circuits shown in FIGS. 1, 2 and 3 is one example. For example, 1) VDD ≧ VDD
1> VS1 ≧ VSS, and 2) a single-phase output as an output circuit 3) or this circuit is applied to an input / output circuit 3) A well potential or a body potential in a grounded gate circuit is a source Various configurations such as making the potential equal to the potential can be used.

In FIG. 1, the level conversion is performed for each of the positive side and the negative side. However, grounded n-channel MOSFETs 102 and 103 and a p-channel
Only the positive-side level conversion is performed using a p-channel crossing latch composed of SFETs 104 and 105, or p-channel MOSFETs 100 and 101 of a grounded gate type.
And n composed of n-channel MOSFETs 106 and 107
A configuration in which only the negative-side level conversion is performed using a channel crossing latch may be employed. In addition, CM as an output buffer
If an OS inverter is used, it is also possible to use a configuration in which only one of the complementary output signals of the cross latch is supplied to the output buffer as an input signal.

Further, in FIG. 2, two output buffers having mutually complementary outputs are used, but a configuration in which only one of the output buffers is provided may be used. Also,
Insulated gate type FETs may be used for each FET.
It goes without saying that an MIS type FET may be used instead of the MOS.

[0051]

As described above in detail, according to the semiconductor integrated circuit of the present invention, the gain characteristic of the cross latch is improved by driving the cross latch using the grounded gate circuit of the complementary input. In addition, a large output can be realized by a cross latch, and the power consumption of the circuit can be reduced. Further, by using complementary inputs, a circuit margin can be increased, and a level conversion circuit with a moderate restriction on element characteristics can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a level conversion circuit used in a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a level conversion circuit used in a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram showing details of a gate ground circuit provided in the level conversion circuit according to the first or second embodiment.

FIG. 4 is a block diagram illustrating a configuration of a semiconductor integrated circuit that supplies a plurality of power supplies and a power supply system thereof.

FIG. 5 is a block diagram showing a configuration of a semiconductor integrated circuit having a logic circuit operating at a low voltage and supplying a plurality of power supplies, and a power supply system thereof;

FIG. 6 is a block diagram showing a configuration of a semiconductor integrated circuit having a logic circuit operating at a low voltage and supplying a plurality of power supplies, and a power supply system thereof;

FIG. 7 is a circuit diagram of a conventional level conversion circuit using a CMOS inverter.

FIG. 8 is a circuit diagram of a conventional level conversion circuit using a cross latch.

[Explanation of symbols]

100, 101 Common-gate p-channel MOSFET 102, 103 Common-gate n-channel MOSFET 104, 105 p-channel M constituting crossing latch
OSFETs 106 and 107 n-channel M constituting crossing latch
OSFET 10A, 10B Complementary signal 10C, 10D from logic circuit Complementary signal 10E, 10F outputting level 1 Complementary signal outputting level 2 200 Level conversion circuit 201, 202 p-channel MOSFET 203, 204 n-channel MOSFET 20A, 20B logic Complementary signals from the circuit 20C, 20D Complementary signals 20E, 20F outputting level 1 Complementary signals 20G, 20H outputting level 2 Complementary signals outputting level 3 400 Lithium ion secondary battery 401 Power supply voltage conversion circuit 402 Logic circuit 403 On-chip storage circuit 404 Level conversion circuit 500 Lithium ion secondary battery 501 Power supply voltage conversion circuit 502 Logic circuit 503 On-chip storage circuit 504 On-chip storage circuit 505 On-chip storage circuit 506 Semiconductor integrated circuit 507 p-channel MOSFET 508 n-channel MOSFET 600 NiH secondary battery 601 power supply voltage conversion circuit 602 logic circuit 603 p-channel MOSFET 604 on-chip storage circuit 605 semiconductor integrated circuit 700 CMOS inverter circuit 800 gate-grounded p-channel MOSFET 801 gate-grounded n-channel MOSFET 802 Cross latch with p-channel MOSFET 803 Cross latch with n-channel MOSFET

Continuing on the front page (72) Inventor Kazunori Ouchi 1 Toshiba-cho, Komukai Toshiba-cho, Saitama-ku, Kawasaki City, Kanagawa Prefecture (72) Masako Yoshida Inventor 1 Masako Yoshida 1 Address F-term in Toshiba R & D Center (reference) 5B024 AA01 BA29 CA07 5F038 BG03 BG10 BH07 BH19 EZ20 5J056 AA32 BB01 BB17 BB49 CC00 CC21 DD13 DD28 DD29 EE06 FF09 GG06

Claims (8)

[Claims] 1. A semiconductor integrated circuit having first and second power supplies having different levels from each other, one end of each of which is connected to a first logic output from a logic circuit unit and a second logic output which is an inverted signal thereof. And first and second FETs of the first conductivity type, each having a gate connected to one of the first and second power supplies, and one end connected to the other of the first and second power supplies. And a third and fourth FET of the second conductivity type having the other end connected to the gate of the other party, and the other end of the first and second FETs of the first conductivity type, respectively. A semiconductor connected to the other end of each of the third and fourth FETs of the second conductivity type, and outputting a signal at the other end of the third or fourth FET of the second conductivity type as an output signal; Integrated circuit. 2. The first power supply is a power supply having a higher level than the second power supply. Each of the first and second FETs is an n-channel type having a gate connected to the second power supply. 2. The semiconductor integrated circuit according to claim 1, wherein each of said third and fourth FETs is a p-channel FET whose source is connected to said first power supply. A third power supply having a different level from the first and second power supplies, wherein the other of the first and second power supplies and the third power supply are supplied as operation power supplies; 2. The semiconductor integrated circuit according to claim 1, further comprising a buffer circuit that outputs an output signal according to a signal at the other end of the third or fourth FET. 4. Each potential level is V1 ≧ V2> V
A semiconductor integrated circuit including first to fourth power supplies including a ground satisfying a relationship of 3 ≧ V4 and including a logic circuit unit using the second and third power supplies; A first n-channel F having a source connected to the logic output and a gate connected to the second power supply
ET and a first p-channel FET having a source connected to the first logic output and a gate connected to the third power supply
A second n-channel FET having a source connected to a second logic output, which is an inverted signal of the first logic output, and a gate connected to the second power supply; and a source connected to the second logic output. And a second p-channel FET having a gate connected to the third power supply, a third p-channel FET having a source connected to the first power supply, and a drain connected to a counterpart gate. Fourth p-channel FET
And a third source in which each source is connected to the fourth power source and each drain is connected to the gate of the other.
And a fourth n-channel FET, wherein the drain of the first n-channel FET is connected to the third p-channel FET.
, The drain of the second n-channel FET is connected to the drain of the fourth p-channel FET, and the drain of the first p-channel FET is connected to the third
And the drain of the second p-channel FET
The drain of the channel FET is connected to the fourth n-channel FE
T, the drain of the third and fourth p-channel FETs are output as a first level, and the drain of the third and fourth n-channel FETs is output as a first level.
A semiconductor integrated circuit comprising a level conversion circuit that outputs a terminal as a second level. 5. A buffer circuit comprising a p-channel FET and an n-channel FET in which a current path between a source and a drain is connected in series between the first power supply and the fourth power supply, 5. The semiconductor integrated circuit according to claim 4, wherein one of the first level output and the second level output of the conversion circuit is commonly connected to gates of a p-channel FET and an n-channel FET constituting the buffer circuit. 6. The method according to claim 1, wherein the well potentials of the first and second p-channel FETs are equal to the third power supply, and the well potentials of the first and second n-channel FETs are equal to the second power supply. The semiconductor integrated circuit according to claim 4 or 5, wherein: 7. The first and second p-channel FETs are formed in the same n-type well, and the first and second n-channel FETs are formed in the same p-type well. 7. The method according to claim 4, wherein
13. A semiconductor integrated circuit according to claim 1. 8. An absolute value of a threshold voltage of each FET in the buffer circuit is set to be larger than an absolute value of a threshold voltage of each FET in the level conversion circuit. Semiconductor integrated circuit.