JP2000124788A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the generation of input leakage even when a voltage equal to or more than a high potential side power source is applied to an input/ output pin. SOLUTION: In this semiconductor device, two output transistors composed of serially connected P channel type MOS transistor 26 and N channel type MOS transistor 27 are provided, the MOS transistors 26 and 27 are alternately ON/OFF controlled based on input data IN and reverse IN and output data are outputted from the input/output pin 28 connected between both MOS transistors 26 and 27. In this case, the N type well of the P channel type MOS transistor 26 is biased to be equal to or more than the high potential side power source applied to the source electrode 26S of the P channel type MOS transistor 26 (Vpp, for instance).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technique for improving characteristics (suppression of input leak) in an output buffer circuit.

[0002]

2. Description of the Related Art In recent years, high integration and high speed of semiconductor devices have been promoted. Further, in order to reduce power consumption, the driving voltage is being reduced. On the other hand, there is a semiconductor device having a high driving voltage which is not reduced to a low driving voltage. Therefore, when these semiconductor devices are connected to each other, a signal output from the high-drive voltage semiconductor device may damage the output buffer circuit of the low-drive voltage semiconductor device. Therefore, in a semiconductor device with a low driving voltage, an output buffer circuit that can be connected to the semiconductor device with a high driving voltage is required.

FIG. 3 is a circuit diagram of an output buffer circuit constituting a part of a conventional semiconductor device.

The output buffer circuit 1 includes inverter circuits 2 and 3, NAND circuits 4 and 5, a P-channel MOS transistor (hereinafter, referred to as a PMOS transistor) 6.
And an N-channel MOS transistor (hereinafter referred to as NMOS
It is called a transistor. 7). 8 is an input / output pin. Input data IN from an internal circuit (not shown) is input to one input terminal of the NAND circuit 5, and is input to one input terminal of the NAND circuit 5 by the inverter 2 to one input terminal of the NAND circuit 4. An input data bar IN (hereinafter referred to as / IN), which is the input data IN inverted, is input. The other input terminals of the NAND circuits 4 and 5 are connected to each other and also receive an output enable signal OE.

The output terminal of the NAND circuit 4 is connected to the P
The output terminal of the NAND circuit 5 is connected to the gate electrode 7G of the NMOS transistor 7 via the inverter 3.

The source electrode 6S of the PMOS transistor 6 is connected to the high potential power supply Vcc,
The source electrode 7S of the transistor 7 is connected to the lower potential power supply Vss. The drain electrode 6D of the PMOS transistor 6 and the drain electrode 7D of the NMOS transistor 7 are connected to each other, and
It is connected to the.

Here, when the output enable signal OE is at H level, the gate electrode 6 of the PMOS transistor 6
G is applied with inverted input data / IN via the NAND circuit 4, and the gate electrode 7 of the NMOS transistor 7 is
Input data IN is applied to G via a NAND circuit 5 and an inverter 3.

That is, the input data IN is at the H level,
When the inverted input data / IN is at L level, both M
H is applied to the gate electrodes 6G and 7G of the OS transistors 6 and 7.
A level signal is applied. Then, the PMOS transistor 6 is turned off and the NMOS transistor 7 is turned on. As a result, the L-level output data Vout is output from the input / output pin 8.

When input data IN is at L level,
When the inverted input data / IN is at the H level, both M
The gate electrodes 6G and 7G of the OS transistors 6 and 7 have L
A level signal is applied. Then, the PMOS transistor 6 turns on and the NMOS transistor 7 turns off. As a result, H-level output data Vout is output from the input / output pin 8.

On the other hand, when the output enable signal OE is at L level, the NAND circuits 4 and 5 apply the input data I
N, output terminal is H regardless of inverted input data / IN
To level. Therefore, an H-level signal is applied to the gate electrode 6G of the PMOS transistor 6, and an L-level signal is applied to the gate electrode 7G of the NMOS transistor 7. As a result, the PMOS transistor 6 and the NMO
The S transistors 7 are both turned off, and the input / output pin 8 enters a high impedance state.

[0011]

In order to obtain the output level of the TTL interface as described above, the PMOS transistor 6 is used for the pull-up driver of the output buffer circuit 1.

Here, the PMOS transistor 6 comprises:
As shown in FIG. 4, P-type diffusion layers 6D and 6S are formed in a region adjacent to the gate electrode 6G in the N-type well 11, and the P-type diffusion layer 1 for fixing (Vcc) the potential of the N-type well 11 is formed.
2 are formed.

When such a PMOS transistor 6 is used, for example, when a voltage of Vcc or more (for example, Vcc + Vtp, where Vtp is the threshold voltage of the PMOS transistor 6) is applied to the input / output pin 8, Next, the PN junction is turned on in the pull-up driver section (FIG. 4)
A forward bias is applied to the parasitic diode formed by the P-type diffusion layer 6D forming the drain electrode of the PMOS transistor 6 and the N-type well 11, as shown in FIG. 11
, The current I flows into the high-potential-side power supply Vcc (input leakage occurs).

Therefore, there is a problem that the input voltage level is limited so as not to be higher than the high potential side power supply Vcc.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device which suppresses the occurrence of input leakage even when a voltage higher than the high potential power supply Vcc is applied to the input / output pins.

[0016]

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above-mentioned problems, and has been made in consideration of the above-mentioned problems. As shown in FIG. 1, two output transistors comprising a P-channel MOS transistor 26 and an N-channel MOS transistor 27 connected in series are provided. And on / off control of the MOS transistors 26 and 27 alternately based on the input data IN and / IN,
Input / output pin 2 connected between S transistors 26 and 27
8 outputs the output data Vout from the N-type well 31 of the P-channel MOS transistor 26 to the high potential side power supply Vcc applied to the source electrode 26S of the P-channel MOS transistor 26 (for example, Vpp ).

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the semiconductor device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an output buffer circuit constituting a part of the semiconductor device of the present invention.

The output buffer circuit 21 includes inverter circuits 22 and 23, NAND circuits 24 and 25, a P-channel type M
An OS transistor (hereinafter, referred to as a PMOS transistor) 26 and an N-channel MOS transistor (hereinafter, referred to as an NMOS transistor) 27 are provided. 28 is an input / output pin. Input data IN from an internal circuit (not shown) is input to one input terminal of the NAND circuit 25, and is input to one input terminal of the NAND circuit 25 by the inverter 22 to one input terminal of the NAND circuit 24. The input data IN
Are input to the input data bar IN (hereinafter referred to as / IN). Further, the NAND circuit 2
The other input terminals 4 and 25 are connected to each other and receive an output enable signal OE.

The output terminal of the NAND circuit 24 is connected to the gate electrode 26G of the PMOS transistor 26, and the output terminal of the NAND circuit 25 is connected to the inverter 2
3 is connected to the gate electrode 27G of the NMOS transistor 27.

The source electrode 26S of the PMOS transistor 26 is connected to a high-potential-side power supply Vcc.
The source electrode 27S of the OS transistor 27 is connected to the lower potential power supply Vss. Further, the drain electrode 26D of the PMOS transistor 26 and the NMOS transistor 27
Are connected to each other and to the input / output pin 28.

Further, the N-type well 31 of the P-channel MOS transistor 26, which is a feature of the present invention, is connected to the high potential side power supply Vcc (for example, Vpp) applied to the source electrode 26S of the P-channel MOS transistor 26. Biased.

Here, when the output enable signal OE is at H level, the inverted input data /
IN is applied, and input data IN is applied to the gate electrode 27G of the NMOS transistor 27 via the NAND circuit 25 and the inverter 23.

That is, the input data IN is at the H level,
When the inverted input data / IN is at L level, both M
Gate electrodes 26G, 27 of OS transistors 26, 27
An H level signal is applied to G. Then, PMOS
The transistor 26 turns off and the NMOS transistor 27 turns on. As a result, the L-level output data Vout is output from the input / output pin 28.

When input data IN is at L level,
When the inverted input data / IN is at the H level, both M
Gate electrodes 26G, 27 of OS transistors 26, 27
An L level signal is applied to G. Then, PMOS
The transistor 26 turns on and the NMOS transistor 27 turns off. As a result, H-level output data Vout is output from the input / output pin 28.

On the other hand, when the output enable signal OE is at L level, the NAND circuits 4 and 5 apply the input data I
N, output terminal is H regardless of inverted input data / IN
To level. Therefore, an H level signal is applied to the gate electrode 26G of the PMOS transistor 26, and the NMO
An L-level signal is applied to the gate electrode 27G of the S transistor 27. As a result, the PMOS transistor 2
6 and the NMOS transistor 27 are both turned off, and the input / output pin 28 enters a high impedance state.

As described above, according to the present invention, in order to obtain the output level of the TTL interface, the output buffer circuit 2
PMOS transistor 26 for pull-up driver 1
Is used, the N-type well 31 of the PMOS transistor 26 of the output buffer circuit 21 is biased to Vpp (> Vcc), so that the input / output pin 28 has a voltage of Vcc or more (for example, Vcc + Vtp, Here, even when a voltage of Vtp is applied to the threshold voltage of the PMOS transistor 26), the PN junction is turned on in the pull-up driver section, so that the drain electrode 26D is connected to the high potential side via the N-type well 31. It is possible to suppress the current from flowing into the power supply Vcc (the occurrence of input leakage).

[0028]

According to the present invention, the output buffer circuit P
By biasing the N-type well of the channel type MOS transistor to Vcc or more, it is possible to suppress the problem that input leakage occurs due to turning on of the PN junction in the pull-up driver unit as in the conventional case.

[Brief description of the drawings]

FIG. 1 is a partial circuit diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a partial cross-sectional view of a semiconductor device according to one embodiment of the present invention.

FIG. 3 is a partial circuit diagram of a conventional semiconductor device.

FIG. 4 is a partial cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 21 ... Buffer circuit 26 ... P-channel type MOS transistor 27 ... N-channel type MOS transistor 28 ... Input / output pin 31 ... N-type well

Claims (2)

[Claims] 1. Two output transistors comprising a P-channel type MOS transistor and an N-channel type MOS transistor connected in series, and said output transistors being alternately turned on / off based on input data, and said two output transistors In a semiconductor device for outputting output data from an input / output pin connected therebetween, an N-type well of the P-channel type MOS transistor is biased to be higher than a high potential side power supply applied to a source electrode of the P-channel type MOS transistor. A semiconductor device characterized by the above-mentioned. 2. A P-channel MOS transistor whose source electrode is connected to a high-potential-side power supply and whose N-type well is biased above the high-potential-side power supply, and whose source electrode is connected to a low-potential-side power supply Vss The drain electrode has an N-channel MOS transistor connected to the drain electrode of the PMOS transistor, and an input / output pin connected between the P-channel MOS transistor and the N-channel MOS transistor. Semiconductor device.