JP2001060863A - Semi-conductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress current consumption in the case of stand-by without requiring a special control circuit and also reduce power consumption by means of a sub-threshold current when an integrated circuit is operated by constituting the semi-conductor integrated circuit of a low threshold voltage electric field- effect transistor(FET) and a low sub-threshold current FET. SOLUTION: In an inverter circuit, a P channel MOSFETMP is constituted of a low sub-threshold current MOSFET and N channel MOSFETMN is of a low threshold value voltage MOSFET. In the case of stand-by, a circuit is constituted to fix an input signal to an H level so that FETMN is made to be an on-state and FETMP is made to be an off-state. A leakage current between a power source and the ground is decided by the leakage current of FETMP so that current consumption in the case of stand-by is saved. In the case of an operation state, the leakage current when an input signal is the H level and an output signal is a L level is restricted by the sub-threshold current of FETMP.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having reduced standby current consumption.

[0002]

2. Description of the Related Art In recent semiconductor integrated circuits, the processing dimensions have been reduced due to advances in fine processing technology. Accordingly, field-effect transistors (FE)
The channel length of T) has become shorter and the threshold voltage has also become lower. However, when the gate-source voltage becomes equal to or lower than the threshold voltage, that is, when the channel of the FET is in an off state, the channel leak current (sub-threshold current) is increasing. As described above, with the advance of fine processing technology, miniaturized FET
In this case, the sub-threshold current tends to increase, and in particular, the current consumption during the standby operation (non-operation) of the semiconductor integrated circuit largely controls and increases. This is a major problem in recent years, particularly for semiconductor integrated circuits used in small battery-driven devices.

Conventionally, various measures have been taken to suppress such an increase in current consumption during standby due to an increase in subthreshold current. FIG. 8 shows an example of a conventional countermeasure. This is disclosed in Japanese Unexamined Patent Publication No.
This is disclosed in Japanese Patent Publication No. In this example, Ci (i = 1? N) is a logic circuit configured using CMOS, and for example, C1 is a CMOS inverter. VC is a power supply terminal, and VS is a ground (GND) terminal. Then, a switch circuit S1 is inserted between the logic circuit Ci and the power supply terminal VC. T1 is a control terminal of the switch circuit S1. This switch circuit S1 has M
An OS transistor, a bipolar transistor, or the like is used. N1 is a power supply terminal of the logic circuit section Ci, and N2 is a ground terminal.

In this circuit, during an initial standby, all inputs Ii of the logic circuit Ci are at Hi level (= VC), and all outputs Oi are at Lo level (= VS). At this time, all the P-channel MOSFETs are off, and all the N-channel MOSFETs are on. However, as described above, the FE
Leakage current when T is off (subthreshold current)
Comes into question. When the switch circuit S1 is not provided, the standby current is, when the output Oi is Lo, the subthreshold current of the P-channel MOSFET in the off state is changed to the power supply terminal VC through the N-channel MOSFET in the on state.
To the ground terminal VS. In this circuit, in order to suppress the subthreshold current, the control terminal T1 of the N-channel MOSFET of the switch circuit S1 is set to the Lo level, and the MOSFET is turned off. At this time, the off-state leakage current (subthreshold current) of the switch circuit S1 is set small. As a result, the current flowing from the power supply terminal VC to the logic circuit Ci is reduced to
Even if the FET of the logic circuit Ci is set to a low threshold voltage at which the subthreshold current becomes large for low-voltage operation, the leakage current flowing through the logic circuit Ci is determined by the switch circuit. It is limited to the leakage current of S1, and current consumption during standby is suppressed. At this time, the sub-threshold current of the switch circuit S1 is set smaller than the sum of the sub-threshold currents of the logic circuits from C1 to Cn, and the potential of the common power supply terminal N1 gradually decreases. P-channel type MO of logic circuit Ci
In the SFET, since the gate voltage is VC and the source voltage is lower than VC, the P-channel MOSFET is turned off strongly and the subthreshold current is greatly reduced.

Next, during operation, the control terminal T1 goes high, and the N-channel MOSFET of the switch circuit S1 is turned on.
When T is turned on, the switch circuit S1 enters a state where it supplies a current necessary for charging the output of the logic circuit Ci, and the circuit operates normally. At this time, the logic circuit Ci operates with a MOSFET having a low threshold voltage, and realizes operation at a low voltage.

[0006]

However, in such a conventional circuit, it is possible to reduce the current consumption during non-operation (standby time) in which the subthreshold current is dominant. Restrictions occur.

One of the reasons is that it is necessary to control the switching of the mode between operation and non-operation. The control terminal T1 must be controlled to set the operation and non-operation. Need.

In the conventional circuit, the state of the logic circuit cannot be held in the standby state by disconnecting the logic circuit Ci from the power supply VC by the switch circuit S1 during the standby state. During standby, there is no problem if the application is such that the circuit operation is completely stopped and the values of the logic circuits are all reset. However, in the standby state of many logic circuits, the standby state (operation Does not stop completely and does not operate logically, but changes in the logic signal from the outside cause it to respond immediately and wait for operation.
(The state of the logic circuit is also held until the signal changes.)

In operation, the logic circuit Ci
When the state is determined, that is, when there is no change in the logic signal, the above-described leak current (sub-threshold current) as current consumption is consumed. This may be smaller than the current consumption of the logic circuit at the time of signal transition, but due to the high integration with recent microfabrication, the subthreshold current present at the time of operation is no longer negligible. Therefore, in the conventional method, the sum of the sub-threshold currents due to the high integration increases, and the current consumption during operation cannot be further reduced.

The present invention solves such a problem and suppresses the current consumption during standby without requiring a special control circuit, and holds logical information. Further, a sub-threshold current at the time of circuit operation is reduced, and power consumption due to the sub-threshold current at the time of operation, which increases due to high integration, can be reduced.

[0011]

A semiconductor integrated circuit according to the present invention (first invention) includes a first field-effect transistor and a second field-effect transistor connected in series between a power supply and a ground. In the semiconductor integrated circuit, one of the first and second field-effect transistors is constituted by a low threshold voltage field-effect transistor,
The other is constituted by a low subthreshold current field effect transistor.

Further, the semiconductor integrated circuit of the present invention (second invention) has a first P-channel field-effect transistor having a source connected to a power supply, and a second P-channel type field-effect transistor having a source connected to a power supply. A field-effect transistor, wherein a gate of the first P-channel field-effect transistor and a drain of the second P-channel field-effect transistor are connected to each other; The gate of the transistor is connected to the drain of the first P-channel field-effect transistor, and an input signal is applied to the gate between the drain of the first P-channel field-effect transistor and ground. A first N-channel field effect transistor to be connected is connected, and a gate is connected between the drain of the second P-channel field effect transistor and the ground. A second N-channel field-effect transistor to which an inverted signal of the input signal (inverted input signal) is applied, is connected to the drain of the first N-channel field-effect transistor and the first N-channel field-effect transistor. Of the P-channel field-effect transistor of
A connection point between the gate of the P-channel field-effect transistor and the drain of the second N-channel field-effect transistor and the second P-channel field-effect transistor. In a semiconductor integrated circuit in which a connection point between a drain of a transistor and a gate of the first P-channel field-effect transistor is used as an inverted signal output terminal of the inverted input signal, the first P-channel field-effect transistor And the second N
A channel-type field-effect transistor (or the first N-channel-type field-effect transistor and the second P-type field-effect transistor).
The channel-type field-effect transistor is composed of a low threshold voltage field-effect transistor, and the second P-channel field-effect transistor and the first N-channel field-effect transistor (or the first (P-channel field-effect transistor and the second N-channel field-effect transistor) are constituted by low-subthreshold current field-effect transistors.

Further, in the semiconductor integrated circuit according to the present invention (third invention), in the semiconductor integrated circuit according to the second invention, different input signals are respectively applied to the gate of the first N-channel type field effect transistor. M applied (M:
2 or more natural numbers) N-channel field-effect transistors, wherein a predetermined logical operation result signal for the M input signals is obtained at the drain of the first P-channel field-effect transistor. In addition to replacing the M N-channel field-effect transistors connected in series, parallel, or series-parallel with each other, different inverted input signals are applied to the gates of the second N-channel field-effect transistors. M N-channel field effect transistors to be connected in parallel and in series such that an inverted signal of the predetermined logic operation result signal is obtained at the drain of the second P-channel field effect transistor. Characterized by being replaced by M N-channel field-effect transistors connected or connected in series / parallel.

The semiconductor integrated circuit of the present invention (fourth invention) is the semiconductor integrated circuit of the first to third inventions, wherein the low sub-threshold current field effect transistor is replaced by the low threshold voltage field effect transistor. And a high threshold voltage field effect transistor having a threshold voltage set higher than that of the transistor.

The semiconductor integrated circuit of the present invention (fifth invention) is the semiconductor integrated circuit of the first to third inventions, wherein the low sub-threshold current field effect transistor is replaced by the low threshold voltage field effect transistor. It is characterized by being constituted by a field effect transistor whose channel length is set longer or its channel width is set narrower than that of the transistor.

Further, the semiconductor integrated circuit according to the present invention (sixth invention) is the semiconductor integrated circuit according to the first to third inventions, wherein the low sub-threshold current field effect transistor has a plurality of gates connected in common. And a series-connected structure of field-effect transistors.

According to the semiconductor integrated circuit of the present invention,
There is always a field effect transistor with a low subthreshold current in the current path from the power supply to the ground, thereby reducing the subthreshold current flowing between the power supply and the ground regardless of whether the semiconductor integrated circuit is operating or in a standby state. Therefore, current consumption can be reduced. Further, no special control signal is required in the transition between the operation and the standby state, and therefore, a control circuit for generating the control signal is not required at all. Further, even in the standby state, power can be supplied to the circuit, so that the standby state can be achieved while the logical state is maintained.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments of the present invention.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

In this embodiment, the present invention is embodied in an inverter circuit. In the drawings, MP is a P-channel MOSFET, and MN is an N-channel MOSFET.
That is, the P-channel MOSFET MP is configured by a low subthreshold current MOSFET, and the N-channel MOSFET MN is configured by a low threshold voltage MOSFET. VC is a power supply terminal, V
S is a ground terminal, IN is a signal input terminal to which an input signal is applied, and OUT is a signal output terminal to which an output signal is output.

In the above configuration, the low sub-threshold current MOSFET can be constituted by, for example, a high threshold voltage MOSFET whose threshold voltage is set higher than that of the low threshold voltage MOSFET.

Alternatively, the low sub-threshold current M
The OSFET is more than the low threshold voltage MOSFET described above.
It can be constituted by a MOSFET whose channel length is set long or whose channel width is set narrow.

Further, the low sub-threshold current M
The OSFET has a plurality of MOs whose gates are commonly connected.
It can be constituted by a series connection structure of SFETs. FIG. 2 shows the configuration in this case.

Further, this configuration is referred to as SOI (Silico).
FIG. 3 shows a structural diagram realized by an (n On Insulator) structure. In the figure, SUB is a silicon substrate, S
iO2 is a silicon oxide layer, p is a P-type silicon layer (source, drain), n is an N-type silicon layer (channel),
S, G and D are a source electrode, a gate electrode,
And a drain electrode. With the recent development of technology, S
Low voltage devices with OI structures have been realized. S
Also in the OI, the above-mentioned increase in the subthreshold current becomes a problem by setting the threshold value to a low value. To prevent this, use vertically stacked MOSFETs as shown in FIG.
When the subthreshold current is reduced, the parasitic capacitance is extremely small as compared with the case of a normal bulk MOSFET, and the performance degradation due to the vertical stacking can be made smaller than in the case of the bulk, which is effective.

In the circuit configuration of this embodiment, a case where the input signal is fixed at the Hi level and is in the standby state will be considered. In this case, since the input signal is at the Hi level, the N-channel MOSFET MN is on and the P-channel MOSFET MP is off. The leakage current between the power supply and the ground in this state is determined by the leakage current of the low-subthreshold current MOSFETMP. However, since this current value is set low, it is possible to reduce current consumption during standby. is there. Further, the logic state is also kept continuously.

Next, consider a case where the apparatus is in a standby state with the input signal fixed at the Lo level. In this case, since the input signal is at the Lo level, the N-channel type M
OSFETMN is off, P-channel MOSFET
MP is on. The leakage current between the power supply and the ground in this state is determined by the leakage current of the low threshold voltage MOSFET MN. Therefore, in this case, the effect of reducing current consumption during standby cannot be obtained.

Therefore, when the circuit of this embodiment is used, the current consumption during standby can be reduced by adopting a circuit configuration in which the input signal is fixed to Hi level during standby.

Next, when the circuit of this embodiment shifts from the standby state to the operating state and the input signal changes from Hi level to Lo level, the N-channel MOSFET MN is turned off and the P-channel MOSFET MP is turned on. As a result, a Hi-level output signal is output. When the input signal changes from the Lo level to the Hi level, the N-channel MOSFET MN is turned on, and the P-channel MOSFET MN is turned on.
The SFETMP is turned off, and an output signal of Lo level is output. Thereafter, in the operating state, an inverted signal thereof is output according to the input signal.

In this operating state, the input signal is high.
When the output signal is at the i level and the output signal is at the Lo level, the leakage current is low sub-threshold current MOSFETM
Limited by the P subthreshold current,
The value is extremely small, and the current consumption can be reduced. Note that the leakage current when the input signal is at the Lo level and the output signal is at the Hi level is determined by the sub-threshold current of the low threshold voltage MOSFET MN. Therefore, the effect of reducing the current consumption can be obtained during this period. Not something.

Thereafter, when shifting to the standby state again, the input signal is fixed at the Hi level, and the operation shifts to the standby state.

This is the end of the description of the first embodiment.

Next, a second embodiment of the present invention will be described.

FIG. 4 is a circuit diagram of a second embodiment of the present invention.

In this embodiment, as in the first embodiment, the present invention is embodied in an inverter circuit. In the drawing, MP ′ is a P-channel MOSFET,
MN ′ is an N-channel MOSFET. The N-channel MOSFET MN ′ is connected to a low sub-threshold current M
OSFET, P-channel MOSFETM
P ′ is constituted by a low threshold voltage MOSFET. VC is a power supply terminal, VS is a ground terminal, IN 'is a signal input terminal to which an input signal is applied, and O'
UT 'is a signal output terminal from which an output signal is output.

In such a configuration, it is assumed that the input signal is fixed at Lo level and is in a standby state. In this case, since the input signal is at the Lo level, the P-channel MOSFET MP 'is on and the N-channel MOSFET MN' is off. The leakage current between the power supply and the ground in this state is determined by the leakage current of the low subthreshold current MOSFET MN '. Since this current value is set low, it is possible to reduce current consumption during standby. It is. Further, the logic state is also kept continuously.

Next, consider a case where the input signal is fixed at the Hi level and is in the standby state. In this case, since the input signal is at the Hi level, the N-channel type M
OSFET MN 'is on, P-channel MOSFET
TMP 'is off. Power supply in this state
The leakage current between the ground and the low threshold voltage MOSFETM
It is determined by the leakage current of P '. So, in this case,
The effect of reducing the current consumption during standby cannot be obtained.

Therefore, when the circuit of this embodiment is used, the current consumption during standby can be reduced by adopting a circuit configuration in which the input signal is fixed at the Lo level during standby.

Next, when the circuit of this embodiment shifts from the standby state to the operating state and the input signal changes from the Lo level to the Hi level, the P-channel MOSFET MP 'is turned off and the N-channel MOSFET MN' is turned off. When turned on, an output signal of Lo level is output. When the input signal changes from the Hi level to the Lo level, the P-channel MOSFET MP 'is turned on, the N-channel MOSFET MN' is turned off, and the Hi-level output signal is output. Thereafter, in the operating state, an inverted signal thereof is output according to the input signal.

In this operating state, the input signal is low.
o level, and the leakage current when the output signal is at the Hi level is a low subthreshold current MOSFETM.
Is limited by the N subthreshold current,
The value is extremely small, and the current consumption can be reduced. Note that the leakage current when the input signal is at the Hi level and the output signal is at the Lo level is determined by the sub-threshold current of the low threshold voltage MOSFET MP. Therefore, the effect of reducing the current consumption can be obtained during this period. Not something.

Thereafter, when shifting to the standby state again, the input signal is fixed at the Lo level, and then the standby state is set.

This is the end of the description of the second embodiment.

Next, a third embodiment of the present invention will be described.

FIG. 5 is a circuit diagram of a third embodiment of the present invention.

In the present embodiment, the first and the second
The present invention is embodied in an inverter circuit as in the embodiment.

In the figure, M1 is a P-channel MOSFET with a low threshold voltage, M2 is a P-channel MOSFET with a low subthreshold current, M3 is an N-channel MOSFET with a low subthreshold current, and M4 is a low threshold voltage N-channel type MOSFET. The sources of the P-channel MOSFETs M1 and M2 are at the power supply terminal VC.
And a P-channel MOSFET M
1 is connected to the drain of the P-channel MOSFET M2, and the gate of the P-channel MOSFET M2 is connected to the drain of the P-channel MOSFET M1. The N-channel MOSFET M3 is connected between the drain of the P-channel MOSFET M1 and the ground terminal VS, and has a gate connected to the signal input terminal 1 to which an input signal is applied. Also, N-channel type MO
The SFET M4 is connected between the drain of the P-channel MOSFET M2 and the ground terminal VS, and its gate is connected to the inverted signal input terminal 2 to which an inverted signal of the input signal (inverted input signal) is applied. Reference numeral 3 denotes a signal output terminal from which an inverted signal of the input signal is output.
Is an inverted signal output terminal for outputting an inverted signal of the inverted input signal.

In the inverter circuit of the present embodiment having the above-described configuration, it is assumed that the input signal does not change and its level is fixed during standby operation. First,
At the time of standby, a case where the input signal of the signal input terminal 1 is at the Lo level (= GND) and the inversion input signal of the inverted signal input terminal 2 is at the Hi level (= VC) and the standby operation is performed is considered. In this case, since the inverted input signal of the inverted signal input terminal 2 is Hi, the MOSFET M4 is turned on, and the inverted signal of the inverted signal output terminal 4 (the inverted signal of the inverted input signal) is set to Lo level. At this time, M
OSFET M1 is turned on, and MOSFET M
3 is off because the input signal of the signal input terminal 1 is at the Lo level, and the inverted signal of the signal output terminal 3 (the inverted signal of the input signal) is at the Hi level. Also,
When the inverted signal output terminal 3 becomes Hi level, M
OSFET M2 is turned off. When the standby operation is performed in such a state, a leakage current path from the power supply terminal VC to the ground terminal VS of the circuit includes a path flowing through the MOSFETs M1 and M3 connected in series and a MOSFET M2 similarly connected in series. And a path flowing through M4. At this time, the first M1 and M3
In the path of (3), since M3 is a MOSFET with a low subthreshold current, the leakage current
Limited by the subthreshold current of ETM3.
In the path between M2 and M4, since M2 is a MOSFET having a low subthreshold current, the leakage current is limited by the subthreshold current of the MOSFET M2. Therefore, the leakage current can be extremely small in any of the paths, and according to the circuit of the present embodiment, the leakage current during standby can be reduced. At this time, since the circuit is still supplied with power, the logic state is also maintained.

Next, in the inverter circuit of the present embodiment having the above configuration, during standby, the input signal of the signal input terminal 1 is at Hi level (= VC), and the inverted input signal of the inverted signal input terminal 2 is at Lo level. Consider the case where the standby operation is performed in the state of (= GND). In this case, since the input signal of the signal input terminal 1 is at the Hi level, the MOSFE
TM3 is turned on, and the inverted signal of the signal output terminal 3 (the inverted signal of the input signal) is set to Lo level. At this time, the MOSFET M2 is turned on, and the MOSF
The ETM4 is such that the inverted input signal of the inverted signal input terminal 2 is Lo.
Level, the signal is off, and therefore the inverted signal of the inverted signal output terminal 4 (the inverted signal of the inverted input signal) is H
i-level. Further, when the inverted signal output terminal 4 becomes Hi, the MOSFET M1 is turned off. When the standby operation is performed in such a state, a leakage current path from the power supply terminal VC to the ground terminal VS of the circuit includes a path flowing through the MOSFETs M1 and M3 connected in series and a MOSFET M1 connected in series.
2 and a path that flows through M4. At this time, in the first path of M1 and M3, the leakage current is determined by the sub-threshold current of the low threshold voltage MOSFET M1. Also, in the path of M2 and M4, the leakage current is low threshold voltage MOSFET M4.
Is determined by the subthreshold current of Therefore,
In this case, the effect of reducing the leak current cannot be obtained.

Therefore, when the circuit of this embodiment is used, the current consumption in the standby mode can be reduced by adopting a circuit configuration in which the input signal is fixed to the Lo level in the standby mode.

Next, when the circuit of this embodiment shifts from the standby state to the operating state and the input signal changes from Lo level to Hi level, the inverted input signal changes from Hi level to Lo level. Thereby, the N-channel type MOSFE
TM4 is turned off, and N-channel MOSFET M3 is turned on. Therefore, the inverted signal of the signal output terminal 3 (the inverted signal of the input signal) becomes Lo level, and
As a result, the P-channel MOSFET M2 is turned on, and the inverted signal of the inverted signal output terminal 4 (the inverted signal of the inverted input signal) becomes Hi level. When the inverted signal output terminal 4 becomes Hi level, the MOSFET
M1 is turned off.

When the input signal changes from the Hi level to the Lo level, the same operation is performed to output an inverted signal (Hi level) of the input signal from the signal output terminal 3 and output the inverted signal from the inverted signal output terminal 4. Inverted signal of input signal (Lo
Level) is output.

As described above, in the operating state,
According to the input signal, an inverted signal of the input signal and the inverted input signal are output from the signal output terminal 3 and the inverted signal output terminal 4, respectively.

Thereafter, when shifting to the standby state again, the input signal is fixed at the Lo level, and the operation shifts to the standby state.

The description of the third embodiment has been completed.

Next, a fourth embodiment of the present invention will be described.

FIG. 6 is a circuit diagram of a fourth embodiment of the present invention.

In this embodiment, as in the first, second and third embodiments described above, the present invention is implemented in an inverter circuit.

In the figure, M1 'is a P-channel MOSFET with a low subthreshold current, M2' is a P-channel MOSFET with a low threshold voltage, M3 'is an N-channel MOSFET with a low threshold voltage, and M4' This is an N-channel MOSFET with a low subthreshold current.
The sources of the P-channel MOSFETs M1 'and M2' are connected to the power supply terminal VC.
The gate of OSFET M1 'is a P-channel MOSFET
A P-channel MOSFET M2 is connected to the drain of M2 '.
The gate of 'is connected to the drain of the P-channel MOSFET M1', respectively. N-channel MOS
The FET M3 'is connected between the drain of the P-channel MOSFET M1' and the ground terminal VS, and has its gate connected to the signal input terminal 1 'to which an input signal is applied. The N-channel MOSFET M4 'is connected to the drain of the P-channel MOSFET M2' and the ground terminal VS.
The gate is connected to an inverted signal input terminal 2 to which an inverted signal of the input signal (inverted input signal) is applied.
'It is connected to the. 3 'is a signal output terminal for outputting an inverted signal of the input signal, and 4' is an inverted signal output terminal for outputting an inverted signal of the inverted input signal.

In the inverter circuit of the present embodiment having the above-described configuration, a case will be considered in which the input signal does not change and its level is fixed during standby operation, that is, when the input signal does not change. First,
During standby, consider a case where the input signal of the signal input terminal 1 'is at the Hi level (= VC) and the inverting input signal of the inverted signal input terminal 2' is at the Lo level (= GND) to perform standby operation. . In this case, since the input signal of the signal input terminal 1 'is Hi, the MOSFET M3' is turned on, and the inverted signal of the signal output terminal 3 '(the inverted signal of the input signal) is set to Lo level. At this time, MOSF
ETM2 'is turned on and MOSFET M4
'Is off because the inverted input signal of the inverted signal input terminal 2' is at the Lo level, and the inverted signal (inverted signal of the inverted input signal) of the inverted signal output terminal 4 'is Hi.
Level. When the inverted signal output terminal 4 'goes high, the MOSFET M1' is turned off. When the standby operation is performed in such a state, a leakage current path from the power supply terminal VC to the ground terminal VS of the circuit includes MOSFETs M1 ′ and M3 connected in series.
'And the MO connected in series
There are paths flowing through SFETs M2 'and M4'. At this time, in the first path of M1 'and M3', M1 'is a MOSFET having a low sub-threshold current.
Therefore, the leakage current is limited by the subthreshold current of the MOSFET M1 '. Also, M2
In the path between 'and M4', since M4 'is a MOSFET with a low subthreshold current, the leakage current is
It is limited by the sub-threshold current of MOSFET M4 '. Therefore, the leakage current can be extremely small in any of the paths.
According to the circuit of the present embodiment, it is possible to reduce the leakage current during standby. At this time, since the circuit is still supplied with power, the logic state is also maintained.

Next, in the inverter circuit of the present embodiment having the above configuration, during standby, the input signal of the signal input terminal 1 'is at the Lo level (= GND), and the inverted input signal of the inverted signal input terminal 2' is A case where the standby operation is performed in the state of the Hi level (= VC) will be considered. In this case, since the inverted input signal of the inverted signal input terminal 2 'is at the Hi level, the MOSFET M4' is turned on, and the inverted signal of the inverted signal output terminal 4 '(the inverted signal of the inverted input signal) is set to the Lo level. . At this time, the MOSFET M1 '
The MOSFET M3 'is turned on, and the MOSFET M3' is off because the input signal of the signal input terminal 1 'is at the Lo level. Therefore, the inverted signal of the signal output terminal 3' (the inverted signal of the input signal) is at the Hi level. . Further, when the signal output terminal 3 'becomes Hi, the MOSFET M2' is turned off. When the standby operation is performed in such a state, a leakage current path from the power supply terminal VC to the ground terminal VS of the circuit includes a MOSFET M connected in series.
There is a path flowing through 1 'and M3' and a path flowing through MOSFETs M2 'and M4' also connected in series. At this time, in the first path of M1 ′ and M3 ′, the leakage current is low threshold voltage MOSF
It is determined by the subthreshold current of ETM3 '. Also, in the paths of M2 ′ and M4 ′, the leak current is
It is determined by the sub-threshold current of the low threshold voltage MOSFET M2 '. Therefore, in this case, the effect of reducing the leak current cannot be obtained.

Therefore, when the circuit of this embodiment is used, the current consumption during standby can be reduced by adopting a circuit configuration in which the input signal is fixed to Hi level during standby.

Next, when the circuit of this embodiment shifts from the standby state to the operating state and the input signal changes from Hi level to Lo level, the inverted input signal changes from Lo level to Hi level. Thereby, the N-channel type MOSFE
TM3 'is turned off and N-channel MOSFET M4
'Is turned on. Therefore, the inverted signal output terminal 4
The inverted signal (the inverted signal of the inverted input signal) of the P 'is at the Lo level.
Since M1 'is turned on, the inverted signal of the signal output terminal 3' (the inverted signal of the input signal) is at the Hi level. Also,
When the signal output terminal 3 ′ becomes Hi level, the MO
SFET M2 'is turned off.

When the input signal changes from the Lo level to the Hi level, the same operation is performed to output an inverted signal (Lo level) of the input signal from the signal output terminal 3 'and output the inverted signal from the inverted signal output terminal 4'. Inverted signal (H
i level) is output.

As described above, in the operating state,
In accordance with the input signal, an input signal and an inverted signal of the inverted input signal are output from the signal output terminal 3 'and the inverted signal output terminal 4', respectively.

Thereafter, when shifting to the standby state again, the input signal is fixed at the Hi level, and the processing shifts to the standby state.

The description of the fourth embodiment has been completed.

Next, a fifth embodiment of the present invention will be described.

FIG. 7 is a circuit diagram of a fifth embodiment of the present invention.

This embodiment is an embodiment in which the present invention is implemented in a two-input NAND circuit. In the inverter circuit of the fourth embodiment, a low threshold voltage N-channel type M
The OSFET M3 'is replaced with two low threshold voltage N-channel MOSFETs M13 and M14 connected in series, and a low sub-threshold current N-channel MOSFET M4' is replaced with two parallel-connected N-channel MOSFETs M4 and M4.
N-channel MOSFET with low subthreshold current
By replacing M15 and M16, a two-input NAND circuit is formed.

In the figure, M11 is a P-channel MOSFET with a low subthreshold current, M12 is a P-channel MOSFET with a low threshold voltage, and M13 and M14.
Is a low threshold voltage N-channel MOSFET, M15
And M16 are N-channel MOSFETs with a low subthreshold current. P-channel type MOSFET M11
And the source of M12 is connected to the power supply terminal VC,
The gate of the P-channel MOSFET M11 is connected to the drain of the P-channel MOSFET M12, and the gate of the P-channel MOSFET M12 is connected to the P-channel MOSFET M12.
Each is connected to the drain of ETM11.
The N-channel MOSFETs M13 and M14 are connected in series between the drain of the P-channel MOSFET M11 and the ground terminal VS, and their gates are connected to signal input terminals 11 and 12, respectively, to which respective input signals are applied. I have. N-channel MOSFETs M15 and M15
16 is connected in parallel between the drain of the P-channel MOSFET M12 and the ground terminal VS, and its gate has an inverted signal input terminal 13 to which an inverted signal (inverted input signal) of each of the above input signals is applied, and 14. Reference numeral 15 denotes a signal output terminal from which the inverted AND signal of each of the input signals is output, and reference numeral 16 denotes an inverted signal from which the inverted OR signal of each of the inverted input signals (the inverted signal of the inverted AND signal) is output. Signal output terminal.

In the two-input NAND circuit of the present embodiment having the above-described configuration, a case will be considered in which the input signal does not change and its level is fixed during standby operation. First,
During standby, the input signals of the signal input terminals 11 and 12 are at the Hi level (= VC), and the inverted input signals of the inverted signal input terminals 13 and 14 are at the Lo level (= GND).
Let's consider a standby operation in the state of. In this case, since the input signals of the signal input terminals 11 and 12 are Hi, both the MOSFETs M13 and M14 are turned on, and the NAND output signal of the signal output terminal 15 is changed to Lo.
Level. At this time, the MOSFET M12 is turned on, and the MOSFETs M15 and M16 are both turned off because the inverted input signals of the inverted signal input terminals 13 and 14 are at the Lo level. Therefore, the inverted signals of the inverted signal output terminal 16 are turned off. Becomes Hi level. When the inverted signal output terminal 16 becomes Hi level, M
OSFET M11 is turned off. When the standby operation is performed in such a state, as a leakage current path from the power supply terminal VC to the ground terminal VS of the circuit, a path flowing through the MOSFETs M11 and M13 and M14 connected in series and a path connected in series are also used. MOSFET M1
2 and the path flowing through M15, and MOSFET M1
2 and a path flowing through MOSFET M16. At this time, in the first path of M11, M13, and M14, M11 has a low subthreshold current of M11.
Since it is an OSFET, the leakage current is
Limited by the subthreshold current of TM11.
In the paths of M12 and M15 and the path of M12 and M16, M15 and M16 are MOSFETs with low subthreshold currents, respectively. Therefore, the leakage current is limited by the subthreshold currents of the MOSFETs M15 and M16. You. Therefore, the leakage current can be extremely small in any of the paths, and according to the circuit of the present embodiment, the leakage current during standby can be reduced. At this time,
Since power is supplied to the circuit, the logic state is also maintained.

Therefore, when the circuit of this embodiment is used, the current consumption during standby can be reduced by adopting a circuit configuration in which both input signals are fixed at the Hi level during standby. is there.

Next, when the circuit of this embodiment shifts from the standby state to the operating state and the input signal changes, the output signal corresponding to the input signal and its inverted signal are output to the signal output terminal 15 and the inverted signal, respectively. Output to the output terminal 16.

Thereafter, when shifting to the standby state again, the two input signals are both fixed at the Hi level, and the operation shifts to the standby state.

The description of the fifth embodiment has been completed.

In the fifth embodiment, the present invention is implemented in a two-input NAND circuit. For example, in the inverter circuit of the fourth embodiment, a low threshold voltage N-channel MOSFET M3 'is used. Are connected to two N-channel MOSFETs of low threshold voltage which are connected in parallel.
T and a low-subthreshold current N-channel MOSFET M4 '
N-channel MOS with low subthreshold current
By replacing with an FET, a two-input NOR circuit can be configured.

Similarly, the low threshold voltage N-channel MOSFET in the inverter circuit of the fourth embodiment is similar to that of the fourth embodiment.
TM3 'is an M (M: natural number of 2 or more) low threshold voltage N-channel MOSFETs each having a gate to which a different input signal is applied, and a predetermined threshold voltage corresponding to the M input signals. In order to obtain a logical operation result signal at the signal output terminal 3 ', the N-channel MOSFET is replaced with M-series connected, parallel-connected, or series-parallel-connected N-channel MOSFETs M4' having a low subthreshold current. Are M low-subthreshold current N-channel MOSFETs each having a gate to which a different inverted input signal is applied, wherein the inverted signal of the predetermined logical operation result signal is the inverted signal output terminal 4 ′ By replacing with M N-channel MOSFETs connected in parallel, in series, or in series / parallel, A desired logic circuit can be formed.

[0077]

As described above in detail, according to the semiconductor integrated circuit of the present invention, a field effect transistor having a low sub-threshold current always exists in the current path from the power supply to the ground. The subthreshold current flowing between the power supply and the ground can be reduced regardless of whether the integrated circuit is in an operation state or a standby state, so that current consumption can be reduced. Further, no special control signal is required in the transition between the operation and the standby state, and therefore, a control circuit for generating the control signal is not required at all. Further, even in the standby state, power can be supplied to the circuit, so that the standby state can be achieved while the logical state is maintained.

As described above, according to the present invention, an extremely useful semiconductor integrated circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an inverter circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram showing a configuration example of a MOSFET having a low subthreshold current according to the first embodiment;

FIG. 3 is a structural diagram when the series circuit of the MOSFETs shown in FIG. 2 is realized by an SOI structure.

FIG. 4 is a circuit configuration diagram of an inverter circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of an inverter circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit configuration diagram of an inverter circuit according to a fourth embodiment of the present invention.

FIG. 7 is a circuit configuration diagram of a two-input NAND circuit according to a fifth embodiment of the present invention.

FIG. 8 is a circuit configuration diagram of a conventional semiconductor integrated logic circuit.

[Explanation of symbols]

MP P-channel MOSFET with low subthreshold current MN N-channel MO with low threshold voltage
SFET MP 'P-channel MO with low threshold voltage
SFET MN 'Low subthreshold current N-channel MOSFET IN, IN' Signal input terminal OUT, OUT 'Signal output terminal VC Power supply terminal VS Ground terminal M1, M2' Low threshold voltage P-channel MO
SFETs M2, M1 'Low-subthreshold current P-channel MOSFET M3, M4' Low-subthreshold current N-channel MOSFET M4, M3 'Low-threshold voltage N-channel MOSFET
SFET 1,1 'signal input terminal 2,2' inverted signal input terminal 3,3 'signal output terminal 4,4' inverted signal output terminal M11 P-channel MOSFET with low sub-threshold current M12 P-channel MOSFET with low threshold voltage Type MO
SFET M13, M14 Low threshold voltage N-channel type MO
SFET M15, M16 N-channel type MOSFET with low subthreshold current 11, 12 Signal input terminal 13, 14 Inverted signal input terminal 15 Signal output terminal 16 Inverted signal output terminal

Claims (6)

[Claims] 1. A semiconductor integrated circuit comprising a first field-effect transistor and a second field-effect transistor connected in series between a power supply and a ground, wherein the first or second field-effect transistor is A semiconductor integrated circuit, wherein one of the transistors is constituted by a low threshold voltage field effect transistor, and the other is constituted by a low subthreshold current field effect transistor. A first P-channel field-effect transistor having a source connected to a power supply; and a second P-channel field-effect transistor having a source connected to a power supply. The gate of the P-channel field-effect transistor is connected to the drain of the second P-channel field-effect transistor, and the gate of the second P-channel field-effect transistor is connected to the first P-channel field-effect transistor. Connected to the drain of the effect transistor,
Further, a first N-channel field-effect transistor having a gate to which an input signal is applied is connected between the drain of the first P-channel field-effect transistor and the ground, and is connected to the second P-channel field-effect transistor. A second N-channel field effect transistor having a gate to which an inverted signal of the input signal (inverted input signal) is applied is connected between the drain of the field effect transistor and the ground, and the first N
A connection point between the drain of the channel-type field-effect transistor, the drain of the first P-channel-type field-effect transistor, and the gate of the second P-channel-type field-effect transistor is connected to an inverted signal output terminal of the input signal. The connection point between the drain of the second N-channel field-effect transistor, the drain of the second P-channel field-effect transistor, and the gate of the first P-channel field-effect transistor is In a semiconductor integrated circuit serving as an inverted signal output terminal of an inverted input signal, the first P-channel field-effect transistor and the second N-channel field-effect transistor (or
The first N-channel field-effect transistor and the second P-channel field-effect transistor) are constituted by low threshold voltage field-effect transistors, and the second P-channel field-effect transistor and The first N-channel field-effect transistor (or the first P-channel field-effect transistor and the second N-channel field-effect transistor) is composed of a low subthreshold current field-effect transistor. A semiconductor integrated circuit, comprising: 3. The semiconductor integrated circuit according to claim 2, wherein said first N-channel field-effect transistor has M gates to which different input signals are applied (M: a natural number of 2 or more). ), The series connection and the parallel connection so that a predetermined logical operation result signal for the M input signals is obtained at the drain of the first P-channel field-effect transistor. The second N-channel field-effect transistor is replaced or connected in series or in parallel, and the second N-channel field-effect transistor is replaced with M gates each having a different inverted input signal applied to its gate. Wherein the inverted signal of the predetermined logical operation result signal is transmitted to the second P-channel field-effect transistor. A semiconductor integrated circuit characterized by being replaced by M N-channel field-effect transistors connected in parallel, in series, or in series / parallel to obtain a drain of a transistor. 4. The semiconductor integrated circuit according to claim 1, wherein the low sub-threshold current field effect transistor has a higher threshold voltage than the low threshold voltage field effect transistor. A semiconductor integrated circuit comprising a high threshold voltage field effect transistor. 5. The semiconductor integrated circuit according to claim 1, wherein the low sub-threshold current field effect transistor has a longer channel length than the low threshold voltage field effect transistor. Or a field effect transistor whose channel width is set to be narrow. 6. The semiconductor integrated circuit according to claim 1, wherein said low sub-threshold current field effect transistor is formed by a series connection structure of a plurality of field effect transistors having their gates connected in common. A semiconductor integrated circuit characterized by being constituted.