JP2001093285A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory in which single end of a write bit line can be realized suppressing the increase of the number of transistors added when the number of the write ports is increased and regions for wiring and connection of wires. SOLUTION: This device has a pair of inverter 101, a pull-down nMOS 102, a pull-down element 103, two nMOS pass transistors 104. 105, a write word line 106, and a write bit line 107. Write data is supplied from the write bit line 107, and is supplied to a node 108 of one side of the pair of inverter 101 through the nMOS pass transistor 104 of which a gate is connected to the write word line 106. A drain of the pull-down nMOS 102 of which agate terminal is connected to the write bit line 107 a source is connected to GND is connected to the other side of a node 109 of the pair of inverter 101 through the pass transistor 105 of which a gate is connected to the word line 106, and the pull- down element 103 is arranged at a gate of the pull-down nMOS 102.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a plurality of (many) write ports and a single-ended write bit line.

[0002]

2. Description of the Related Art Generally, in a semiconductor memory device, various improvements have been made in order to improve the degree of integration. In particular, the number of elements and the area for wiring are reduced. In particular, in a semiconductor memory device having many write ports according to the present invention, since the area is remarkably increased, the read bit line is made single-ended as an improvement.

That is, in recent years, with the increase in the number of arithmetic units on a chip, the number of ports has been further increased, and a further reduction in the area has been demanded. To meet such a demand, for example, “S. Hesley, et al. ., ”A 7th-Generation x86 Mic
roprocessor ”, 1999 IEEE International Solid-State
Circuits Conference Digest of technical Papers, p
p.92-93, 1999, it has been proposed to make the bit line of the write port single-ended.

In the technique disclosed in this prior art document, as shown in FIG. 10, one write bit line 107 is connected to an n-channel MOS pass transistor 104 having a write word line 106 connected to a gate terminal. Simultaneously, by connecting the gate terminal of the pull-down n-channel MOS transistor 102 and the drain terminal of the pull-down transistor 102 to the n-channel MOS pass transistor 105 whose write word line 106 is connected to the gate terminal, A differential light is realized.

In FIG. 10, a pass transistor 104 is provided between one node 108 of a storage portion 101 composed of a pair of inverters and a write bit line 107, and the other is connected between a node 109 and a drain of a pull-down transistor 102. A pass transistor 105 is provided between the two pass transistors 104 and 10.
The gate of No. 5 is connected to the write word line 106.
The write bit line 107 is connected to the gate of the pull-down transistor 102.

In such a configuration, the write bit line 10
7 is low level, the word line 1
06 is set to the high level, a low level is written to one node 108 via the pass transistor 104, and when the write data of the write bit line 107 is at the high level, the word line 106 is set to the high level, so that the pull-down is performed. The low level is written to the other node 109 via the transistor 102 and the pass transistor 105.

[0007]

However, in this conventional technique, one pull-down transistor (102) and two pass transistors (104, 10) are provided at each write port.
5), a total of three transistors are required. Therefore, when the number of write ports increases, as shown in FIG.
2, 204, 205), and the area for wiring and connection also increases. Note that reference numerals 206 and 207 denote write word lines and write bit lines added by increasing the number of write ports.

When the number of write ports further increases, the transistor area and the wiring area and connection area greatly increase accordingly. Therefore, the effect of reducing the area of the multi-port semiconductor memory device due to the single-ended write bit line is small. Problem. This becomes more remarkable as the number of wiring processes increases. Further, since the lengths of the word lines and the bit lines are determined from the area of the semiconductor memory device, if the area reduction effect is small, the wiring length reduction effect is small. For this reason, there is also a problem that the delay reduction effect is reduced.

An object of the present invention is to provide a semiconductor memory device in which the area increases little even if the number of write ports increases.

[0010]

According to the present invention, there is provided a semiconductor memory device in which write bit line data is written into a storage portion composed of an inverter pair by controlling a word line. A pass transistor provided between a node and the write bit line and having a gate connected to the word line; a pull-down transistor provided between the other node of the inverter pair and a ground potential; A pass transistor provided between a gate and the write bit line and having a gate connected to the word line; and a pull-down element provided between the gate of the pull-down transistor and a ground potential. A semiconductor memory device is obtained.

Then, in response to the addition of the write port,
A pass transistor having a gate connected to an added word line is added between the one node and the added write bit line, and a pass transistor is added between the gate of the pull-down transistor and the added write bit line. And a pass transistor having a gate connected to the added word line.

The pull-down element may be a resistor, an n-channel transistor whose gate is connected to a power supply potential, and a p-channel transistor whose gate is supplied with the output of an inverter whose word line is connected to the input. Alternatively, a parallel circuit configuration of an n-channel transistor whose gate is connected to the power supply potential and a p-channel transistor whose gate is connected to the word line may be used.

The operation of the present invention will be described. In the write portion of the semiconductor memory circuit, an operation of inputting a signal selected by a plurality of write port pass transistors to a gate of a pull-down transistor for generating inverted data of a write bit line is executed. Therefore, it is not necessary to prepare a pull-down transistor every time a write port is added, and only the addition of two pass transistors is sufficient.
The effect of suppressing an increase in the transistor region and the wiring connection region can be obtained.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to clarify the objects, features and advantages of the present invention, embodiments of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention, and the same parts as those in FIG. 10 are denoted by the same reference numerals. FIG. 1 shows a semiconductor memory device having one write port (a read port is omitted) as an embodiment of the present invention.

The present semiconductor memory device comprises an inverter pair 10
1, pull-down nMOS transistor 102, pull-down element 103, nMOS pass transistors 104 and 10
5, a write word line 106 and a write bit line 107. The write data is supplied from the write bit line 107, and is connected to one node 1 of the inverter pair 101.
08, n whose gate is connected to the write word line 106
It is supplied via a MOS pass transistor 104.

Another node 1 of inverter pair 101
09 and a ground potential, a pull-down nMOS transistor 102 is provided.
The write bit line 107 is connected to the gate of the write bit line 107 through the pass transistor 105 whose word line 106 is connected to the gate.
Is connected, and a pull-down element 103 is arranged between the gate of the transistor 102 and the ground potential.

When the write data on the write bit line 107 is at a low level, a low level is written to the node 108 via the pass transistor 104 and the write bit line 10
When the write data of No. 7 is at the high level, the low level is written to the other node 109 via the pull-down transistor 102 via the pass transistor 105.
The pull-down element 103 connected to the gate of the pull-down transistor 102 is a pull-down transistor 1
This prevents the erroneous writing of the gate 02 as a floating node. The resistance value of the pull-down element 103 may be high, and the influence on the write operation is small.

Referring to FIG. 2, there is shown a semiconductor memory device having two write ports (a read port is omitted) as another embodiment of the present invention. This semiconductor memory device is different from the semiconductor memory device of FIG. 1 in that nMOS pass transistors 204 and 205 and a write word line 206 are provided.
And a write bit line 207 are added.

The pass transistor 204 has a gate connected to a write word line 206 between the write bit line 207 and one node 108 of the inverter pair 101. Further, the pass transistor 205 includes the write bit line 207 and the pull-down transistor 102.
Between the gate and the write word line 20
6 are connected and arranged. In this way, when adding a write port, an element is simply added by adding two transistors.

Referring to FIG. 3, there is shown an example of the pull-down element 103 of FIG. That is, this is an example in which the resistor 110 is used as the pull-down element 103 in FIG. Thus, the above-described processing is executed. The illustrated inverter pair 101 is well known to those skilled in the art and is not directly related to the present invention. Also, the read port circuit is omitted from the figure because it is not mentioned here.

Hereinafter, the operation of the present embodiment will be described. First, the write operation when the resistor 110 is used as the pull-down element 103 will be described with reference to the timing chart of FIG. Since this is a pseudo differential operation, the operation differs depending on whether the write data is at a high level or a low level. When the data on the write bit line 107 is at a high level,
When the word line 106 goes high, the inverter pair 1
01 is pulled up to a high level via the pass transistor 104, and the other node 10
9 passes the pass transistor 105, turns on the pull-down transistor 102, and is pulled down to a low level.

One node 108 is a pass transistor 1
Since the voltage passes through the transistor 04, so-called Vt drops by the threshold value of the transistor, and the high level is hardly written. However, the low level is written to the other node 109, and the high level is attained. When the word line 106 becomes low level, the gate of the pull-down transistor 102 is gradually pulled down to low level by the pull-down resistor 110, and the pull-down transistor is turned off.

When the word line 106 goes high when the data on the write bit line 107 is low, one node 108 of the inverter pair 101 is pulled down to the low level via the pass transistor 104 and the other is pulled down. The transistor 102 remains off and a low level is written. When the word line 106 goes low, the inverter pair 101 is disconnected from the bit line 107 and holds data.

Similarly, when the data on the bit line 107 changes when the word line 106 is at the high level, writing is performed according to the change on the bit line 107. Bit line 10
7 is high level, the pass transistor 10
The high level of the signal after passing through 4,105 drops by the so-called Vt. The gate of the pull-down transistor 102 that has passed through the pass transistor 105 is further reduced by the pull-down resistor 110 from Vdd dropped by Vt.
1 contributes to the lowering of the other node 109, and a high level is written.

When the data on bit line 107 is at a low level, one node 10 after passing through pass transistor 104
8 is pulled down to low level and the pass transistor 105
After passing, the gate of the pull-down transistor 102 is pulled down to a low level and turned off, and the low level is written. Obviously, the writing is performed by the same operation in the case of adding the write port in FIG.

In another embodiment of the present invention, the basic configuration is as described above, but the pull-down element 103 is further devised. The configuration is shown in FIG. Referring to FIG. 5, the pull-down element 103 of FIG. 1 is configured as follows. That is, the nMOS transistor 111 has a gate connected to Vdd. This can be easily realized as compared with the case where a high-resistance element is produced with high accuracy. The same processing as described above is executed, and the timing chart is the same as that in FIG.

The pull-down element 103 shown in FIG.
It is also configured as follows. That is, the write word line 10
6 is an nMOS transistor 111 whose output terminal of the inverter 112 connected to the input terminal is connected to the gate. When the word line is at a high level, the pull-down resistance increases and the influence on the write operation can be reduced. When the word line is at a low level, the pull-down resistance decreases and the hold effect can be increased.

The operation of this embodiment is performed according to the timing chart of FIG. That is, the word line 106
Is at a high level, the inverter 112 outputs a low level, the pull-down transistor 111 is turned off,
When the word line 106 is at a low level, the inverter 112
Outputs a high level, and the pull-down transistor 111
Turns on.

As described above, since the driving force for pulling down the gate terminal of the pull-down transistor 102 during the writing of the word line 106 at the high level is suppressed, the pull-down transistor is more activated when the data of the word bit line 107 is at the high level. The gate terminal voltage of 102 increases. Therefore, high-level writing can be performed at a higher speed, the power supply voltage can be further reduced, and power consumption can be reduced. Moreover,
In this embodiment, since the driving force for pulling down the gate of the pull-down transistor 102 is increased when the word line 106 is held at a low level, erroneous writing due to noise or the like can be further prevented.

In this embodiment, the effects of further reducing the write delay and improving the noise margin can be obtained. In this example, when a port is added, the write word line 106 is also added, and in that case, the inverter 112 may be a multi-input NOR gate.

In the configuration shown in FIG.
3 (inverter 112 + nMOS transistor 111)
Is also configured as shown in FIG. In FIG. 8, a pull-down element 103 includes a pMOS transistor 113 having a write word line 106 connected to the gate, and a Vdd
Are connected in parallel with the nMOS transistor 111 to which the NMOS transistor 111 is connected. In addition to the effect similar to that of FIG. 6, the inverter 112 can be omitted by using pMOS. The nMOS transistor 111 connected in parallel serves as the pMOS transistor 113 which cannot realize the ground (GND) level due to the drop in Vt.

In this example, when a write port is added, each additional write word line may be connected to each input of the OR gate by using a multi-input OR gate in the gate of the transistor 113.

FIG. 9 is a diagram showing the effect of the present invention, and summarizes the relationship between the number of write ports and the number of write elements.
When the number of write ports increases, the present invention can suppress an increase in the number of transistors, and can also suppress an increase in the number of wirings and an increase in the area for connection. It should be noted that the present invention is not limited to the above embodiments, and it is apparent that each embodiment can be appropriately modified within the scope of the technical idea of the present invention.

[0034]

As described above, according to the present invention,
Increase the number of transistors when adding a write port by 2
In the case of supporting a large number of write ports, the number of transistors can be remarkably reduced, so that the dedicated area can be significantly reduced, and conversely, an improvement in the degree of integration can be expected. This has the effect.

[Brief description of the drawings]

FIG. 1 is a circuit diagram according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of a pull-down element in the circuit of FIG.

FIG. 4 is a time chart for explaining the operation of the present invention.

FIG. 5 is a circuit diagram showing another example of the pull-down element in the circuit of FIG. 1;

FIG. 6 is a circuit diagram showing still another example of the pull-down element in the circuit of FIG.

FIG. 7 is a time chart for explaining the operation of FIG. 6;

FIG. 8 is a circuit diagram showing another example of the pull-down element in the circuit of FIG.

FIG. 9 is a table showing the effect of suppressing an increase in the number of elements according to the present invention.

FIG. 10 is a circuit diagram of a conventional embodiment.

FIG. 11 is a circuit diagram of another conventional embodiment.

[Explanation of symbols]

Reference Signs List 101 inverter pair 102 pull-down nMOS transistor 103 pull-down element 104, 105, 204, 205 nMOS pass transistor 106, 206 write word line 107, 207 write bit line 108 one node of inverter pair 109 the other node of inverter pair 110 pull-down resistor 111 pull-down nMOS transistor 112 inverter 113 pull-down pMOS transistor

Claims (6)

[Claims] 1. A semiconductor memory device in which write bit line data is written into a storage portion composed of an inverter pair by controlling word lines, wherein a write bit line data is written between one node of the inverter pair and the write bit line. A pass transistor having a gate connected to the word line, a pull-down transistor provided between the other node of the inverter pair and a ground potential, and a pass transistor provided between the gate of the pull-down transistor and the write bit line. A pass transistor provided with a gate connected to the word line;
A semiconductor memory device comprising: a pull-down element provided between a gate of the pull-down transistor and a ground potential. 2. In response to the addition of a write port, a pass transistor having a gate connected to an added word line is added between said one node and an added write bit line, and 2. The semiconductor memory device according to claim 1, further comprising a pass transistor having a gate connected to the added word line, between the gate of the transistor and the added write bit line. 3. The semiconductor memory device according to claim 1, wherein said pull-down element is a resistor. 4. The semiconductor memory device according to claim 1, wherein said pull-down element is an n-channel transistor having a gate connected to a power supply potential. 5. The semiconductor memory device according to claim 1, wherein said pull-down element is a p-channel transistor whose gate is supplied with an output of an inverter having said word line connected to an input. 6. The pull-down element according to claim 1, wherein an n-channel transistor having a gate connected to a power supply potential and a p-channel transistor having a gate connected to the word line are arranged in parallel. Or the semiconductor memory device according to 2.