JP2007149207A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a differential amplifier circuit, wherein a voltage reduction and high speed operation are attained. <P>SOLUTION: 1st, 2nd amplifier sections are constituted by respectively setting 1st, 2nd capacity means and 1st, 2nd conductivity-type 1st, 2nd current source MOSFET, to a first common source of 1st, 2nd conductivity type 1st, 2nd differential MOSFET couple, in which respective gates are connected to a pair of a 1st input terminal. Next, 1st, 2nd output sections are constituted of 1st, 2nd conductivity type 3rd, 4th MOSFET couple arrayed in serial to each of the 1st, 2nd conductivity-type 1st, 2nd MOSFET couple for respectively supplying a current flowing into the 1st, 2nd differential MOSFET couple. Then, drains corresponding to the above 3rd MOSFET couple and 4th MOSFET couple are connected each other to make a pair of output terminals, and a bias voltage is supplied to the gates of 1st, 2nd current source MOSFETs and 1st to 4th MOSFETs. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique that is effective when used in a device having a memory circuit such as a static RAM.

There is a rail-to-rail (rail to rail is a registered trademark of Motorola, USA) circuit that can perform an amplification operation even when an input signal is shifted to a power supply voltage or a circuit ground potential. This differential amplifier circuit requires biases P1, P2, N1, and N2, and DCP and DCN, and considers process variations of elements, such as variations in the mutual conductance ratio between the P-channel MOSFET and the N-channel MOSFET, and a shift in the input voltage Vin Then, it is difficult to use as it is as a small amplitude high speed input circuit. As an example of a differential amplifier circuit obtained by improving the rail-to-rail circuit, there is JP-A-2003-249829.
U.S. Pat. No. 4,958,133 JP 2003-249829 A

  FIG. 7 shows an amplifying circuit obtained by improving the differential amplifying circuit shown in Patent Document 2 for further low voltage operation, and FIG. 8 shows a bias circuit for generating the bias voltage. The differential amplifier circuit of FIG. 7 and the bias circuit of FIG. 8 are configured by the same circuit. In the bias circuit, the reference voltage VREF is supplied to a pair of input terminals, and the differential output is also connected in common to the bias voltage. BIAS is formed. In the circuit shown in Patent Document 2, one bias voltage VB is used. However, in the circuits of FIGS. 7 and 8 improved for low voltage operation, a series configuration for taking out an output signal is used. Of the four MOSFETs to be connected, MOSFETs Q8, Q9 and Q10, Q11 connected to the output node side use bias voltages BIASP and BIASN having an offset with respect to the bias voltage BIAS.

  The bias voltages BIASP and BIASN are formed by dividing the power supply voltage VDD by the resistors R1 to R3. The bias voltage BIASP supplied to the gates of the P-channel MOSFETs Q8 and Q9 is a voltage that is lower by −ΔV (large in absolute value) than the bias voltage BIAS set near the midpoint voltage. The bias voltage BIASN supplied to the gates of the N-channel MOSFETs Q10 and Q11 is a voltage that is higher by + ΔV (large in absolute value) than the bias voltage BIAS set near the midpoint voltage. Thereby, it is possible to compensate for an increase in effective threshold voltage due to the substrate effect due to a decrease in the source potential of MOSFETs Q8 and Q9 by the voltage drop in MOSFETs Q6 and Q7. Further, it is possible to compensate for an increase in effective threshold voltage due to the substrate effect due to the source potential of the MOSFETs Q10 and Q11 increasing by the voltage drop in the MOSFETs Q12 and Q13. As a result, the power supply voltage VDD can be lowered without considering an increase in effective threshold voltage due to the substrate effect.

  However, the inventor of the present application has found that the circuit of FIG. 8 has the following problems to be solved. FIG. 9 shows an operation explanatory diagram when the input signal IN transits from a high level to a low level. For example, the high level of the input signal IN is set to 0.95V, and the low level is set to 0.55V. In the P-channel type differential circuit section (Q2, Q3), the common source COMP is suddenly lowered at the same time as the input voltage IN is lowered. Since the common source COMP is about 1.5V and the threshold voltages of the MOSFETs Q2 and Q3 are about 0.5 to 0.6V, the MOSFET Q2 has a threshold voltage when the input signal IN is at a high level. It is turned on weekly in the vicinity, and the potential of the common source COMP is lowered as the gate voltage is lowered. Therefore, if the input signal IN does not decrease to the point where it crosses the reference voltage VREF, the difference between the gate voltages of the differential MOSFETs Q2 and Q3 does not increase and the rise time of the output signal OT is delayed.

  FIG. 10 shows an operation explanatory diagram when the input signal IN transits from a low level to a high level. In the N-channel type differential circuit section (Q4, Q5), the input voltage IN rises and the common source COMN rises rapidly. Since the common source COMN is about 0.2V and the threshold voltages of the MOSFETs Q4 and Q5 are about 0.5 to 0.6V, a voltage of about 0.3 to 0.4V can be obtained even at the low level. As the gate voltage rises, it is turned on weekly and raises the potential of the common source COMN. Therefore, if the input signal IN does not rise to the vicinity where it crosses the reference voltage VREF, the difference between the gate voltages of the differential MOSFETs Q4 and Q5 does not increase and the fall time of the output signal OT is delayed.

  Although measures can be taken to increase the speed by adding an implantation mask in the input differential MOSFETs Q2 and Q3 and Q4 and Q5 to lower the threshold voltage, there is a problem of an increase in cost due to an increase in the number of processes. Although measures can be conceived to increase the gate widths of the MOSFETs Q0 and Q1 to suppress the potential fluctuation amount of the common sources COMP and COMN, side effects such as an increase in the amount of current consumption in the input circuit and a deterioration in the DC operation margin occur.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device including a differential amplifier circuit that realizes low voltage and high speed operation. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. A first conductivity type first differential MOSFET pair having a gate connected to a pair of first input terminals, a first capacitor means and a first conductivity type provided in a first common source of the first differential MOSFET pair. The first current source MOSFET constitutes a first amplifying unit. A second differential MOSFET pair of the second conductivity type having a gate connected to the pair of first input terminals, a second capacitor means provided in a second common source of the first differential MOSFET pair, and a second conductivity A second amplifying unit is constituted by a second current source MOSFET of the type. A first output unit is configured by a second conductivity type first MOSFET pair for supplying current flowing through the first differential MOSFET pair and a second conductivity type third MOSFET pair in series with each of the first MOSFET pair. . A second output unit is configured by a first conductivity type second MOSFET pair for supplying a current flowing through the second differential MOSFET pair and a first conductivity type fourth MOSFET pair in series with each of the second MOSFET pair. . The corresponding drains of the third MOSFET pair and the fourth MOSFET pair are connected to form a pair of output terminals, and a bias voltage is supplied to the first and second current source MOSFETs and the gates of the first to fourth MOSFETs.

  The first capacitor means and the second capacitor means can delay the change corresponding to the input signal IN of the first and second common nodes, and speed up the transition of the output signal.

  FIG. 1 is a circuit diagram showing one embodiment of an input circuit provided in a semiconductor integrated circuit device according to the present invention. Each circuit element in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. The circuit shown in the figure is constituted by a CMOS circuit composed of an N-channel MOSFET and a P-channel MOSFET, and the P-channel MOSFET is distinguished from the N-channel MOSFET by attaching an arrow to its back gate (channel) portion.

  As the input circuit of this embodiment, the rail-to-rail circuit improved for lowering the voltage as shown in FIG. 7 is used. That is, P-channel type differential MOSFETs Q2 and Q3, a first amplifying unit composed of a P-channel type current source MOSFET Q0 that forms the operating current thereof, N-channel differential MOSFETs Q4 and Q5, and an N-channel type that conducts the operating current The second amplifying unit is configured by the current source MOSFET Q1. The source of the P-channel type current source MOSFET Q0 is supplied with the power supply voltage VDD, and the source of the N-channel type current source MOSFET Q1 is supplied with the circuit ground potential (0 V).

  The gates of one of the differential MOSFETs Q2 and Q4 of the first amplifying unit and the second amplifying unit are connected to the first input terminal IN. The gates of the other differential MOSFETs Q3 and Q5 of the first amplifying unit and the second amplifying unit are connected to the reference voltage terminal VREF as a second input terminal. A small amplitude input signal is supplied to the input terminal IN from the outside, and a reference voltage for identifying the high level and low level of the input signal is supplied to the reference voltage terminal VREF. NBT degradation of the differential MOSFETs Q2 and Q3 can be prevented by connecting the substrates of the differential MOSFETs Q2 and Q3 to the source.

  A first output unit including N-channel MOSFETs Q10 to Q13 is provided for the first differential unit, and a second output unit including P-channel MOSFETs Q6 to Q9 is provided for the second differential unit. In the first output section, MOSFETs Q12 and Q13 for supplying drain currents of the differential MOSFETs Q2 and Q3 and MOSFETs Q10 and Q11 for extracting output signals are connected in series. Similarly, in the second output section, MOSFETs Q6 and Q7 for flowing the drain currents of the differential MOSFETs Q4 and Q5 and MOSFETs Q8 and Q9 for extracting output signals are connected in series. The MOSFETs Q6, Q8 and Q10, Q12 which are one of the first and second output units are connected in a cascode (series) form between the power supply voltage VDD and the ground potential of the circuit. The MOSFETs Q7, Q9 and Q11, Q13, which are the other of the first and second output units, are connected in a cascode form between the power supply voltage VDD and the circuit ground potential VSS.

  One MOSFET Q10 of the first output section and one MOSFET Q8 of the second output section operate as a so-called source-input, grounded-gate amplification MOSFET, and have their drains connected to the first output terminal OT. Similarly, the other MOSFET Q11 of the first output section and one MOSFET Q9 of the second output section operate as amplification MOSFETs similarly to the above, and their drains are connected to the second output terminal. In this embodiment, although not particularly limited, the signal OT at the first output terminal is transmitted through the inverter circuits IV1 and IV2 as output amplifier circuits, and is used as a CMOS level internal signal. The inverter circuit IV1 operates at the power supply voltage VDD, and the inverter circuit IV2 operates at an internal voltage VDDI lower than the inverter circuit IV2 to form a CMOS level internal signal corresponding to the internal voltage VDDI.

  In this embodiment, the current source MOSFETs Q0 and Q1 of the first amplifying unit and the second amplifying unit, and the MOSFETs Q6, 7 and Q12 of the first output unit and the second output unit by the bias circuit as described in FIG. , Q13 are commonly supplied with a bias voltage BIAS. Further, for the low voltage operation as described above, the gates of the MOSFETs Q8 and Q9 of the first output unit and the second output unit are offset in the negative direction (−ΔV) with respect to the bias voltage BIAS. A bias voltage BIASP is supplied. A bias voltage BIASN having an offset (+ ΔV) in the positive direction with respect to the bias voltage BIAS is supplied to the gates of the MOSFETs Q10 and Q11 of the first output unit and the second output unit.

  Since the bias circuit shown in FIG. 8 is composed of a circuit similar to the input circuit of FIG. 1, the corresponding circuit elements are given the same circuit symbols. The difference from the input circuit is that the first output terminal and the second output terminal are connected to each other and used to generate the bias voltage BIAS. Complementary output terminals are connected to each other, the same reference voltage VREF is supplied to the input terminals, and the corresponding output voltage is supplied to the bias circuit itself and the input circuit as the bias voltage BIAS.

  In this configuration, in the signal transmission operation that determines the level of the output signal in the input circuit, the negative feedback operation for forming the bias voltage BIAS is not performed, so that the input circuit corresponds to the input signals input from the input terminals IN and VREF. The signal transmission operation for forming the output signal OT can be performed at high speed.

  In such a bias circuit for forming the bias voltage BIAS supplied to the input circuit using the reference voltage VREF, the same reference voltage VREF is supplied to the pair of input terminals if there is no variation in the elements. The signal should be the same, but in reality, the offset in the differential pair element and the output MOSFET have the same offset, so that a bias voltage BIAS is formed to compensate for the offset, and this is the same as that of the input circuit. Supplied to the corresponding MOSFET. As a result, it is possible to realize speeding up and stabilization of the operation of the single configuration input circuit.

  In this embodiment, a capacitive element C1 is connected to the common source COMP of the differential MOSFETs Q2 and Q3 of the first differential section for high speed operation of the input circuit. Although not particularly limited, the capacitor C1 uses a MOS capacitor having a gate connected to the common source COMP and a source and a drain connected to a ground potential point of the circuit. Similarly, the capacitive element C2 is also connected to the common source COMN of the differential MOSFETs Q4 and Q5 of the second differential section. This capacitive element C2 also uses a MOS capacitor having a gate connected to the common source COMP and a source and drain connected to a ground potential point of the circuit.

  FIG. 2 shows an operation explanatory diagram when the input signal IN transitions from a high level to a low level. For example, the high level of the input signal IN is set to 1.05V, and the low level is set to 0.65V. In the P-channel type differential circuit section (Q2, Q3), the input voltage IN decreases, and at the same time, the common source COMP tends to rapidly decrease as shown by the dotted line. Since the voltage of about 1.4V of the common source COMP is held in the capacitive element C1, it acts to prevent the potential drop of the common source COMP accompanying the decrease of the input signal IN. The holding voltage of the capacitive element C1 gradually decreases according to the increase in current flowing through the MOSFETs Q2 and Q3. For this reason, as the input signal IN decreases, the gate-source voltage Vgs of the MOSFET Q2 increases and the rise time of the output signal OT is increased.

  FIG. 3 shows an operation explanatory diagram when the input signal IN transits from a low level to a high level. In the N-channel type differential circuit section (Q4, Q5), at the same time as the input voltage IN rises, the capacitive element C2 prevents the common source COMN from rising sharply as shown by the dotted line. For example, the common source COMN is about 0.2 V, and the voltage is held by the capacitive element C2. The holding voltage of the capacitive element C2 rises gradually according to the increase in current flowing through the MOSFETs Q4 and Q5. For this reason, as the input signal IN rises, the gate-source voltage Vgs of the MOSFET Q4 increases, and the fall time of the output signal OT is increased.

  FIG. 4 is a circuit diagram showing one embodiment of an input circuit provided in the semiconductor integrated circuit device according to the present invention. In this embodiment, in order to stabilize the bias voltages BIAS, BIASP, and BIASN, capacitive elements C3 to C6 are added to circuit nodes to which the bias voltages BIAS, BIASP, and BIASN are supplied. That is, the capacitance elements C3 and C4 are connected to the gates of the constant current source MOSFETs Q0 and Q1, respectively, so as to prevent the potential fluctuation due to kickback or the like when the input circuit is operated. A capacitive element C5 is connected to stabilize the bias voltage BIASP, and a capacitive element C6 is connected to stabilize the bias voltage BIASN. The capacitive elements provided in the first differential section and the second differential section are divided into two capacitive elements C1 and C1 ′ and C2 and C2 ′ in order to balance the differential operation, which will be described later. Thus, the element layout is arranged so as to be symmetrical.

  The control signal EN is provided for selecting operation / non-operation of the input circuit. For example, the operation of the input circuit is not required when the semiconductor integrated circuit device is left in a standby state for a long time. Therefore, the function of reducing the current consumption of the input circuit in the standby state is realized by the control signal EN. A CMOS switch (Q19, Q18) for transmitting the bias voltage BIAS when the control signal EN is in a high-level standby state using the control signal EN and an inverted signal formed by a CMOS inverter circuit constituted by MOSFETs Q30 and Q31. And (Q20, Q21) is turned off to stop the supply of the bias voltage BIAS. In the standby state, the pull-up P-channel MOSFET Q26 is turned on, the P-channel MOSFETs Q0, Q6, Q7 are turned off, the pull-down N-channel MOSFET Q27 is turned on, and the N-channel MOSFETs Q1, Q12, Q13 are turned on. Is turned off. By such an operation, the current flowing through the input circuit is interrupted to reduce power consumption.

  In addition to the low power consumption in the standby state for a long period of time as described above, the input signal EN has, for example, a static RAM described later and an input data configuration of x36 (36 bit parallel input / output) operation and x When an 18-bit (18-bit parallel input / output) operation is to be realized with the same memory chip, the input circuit for the data input signal Din that is not used in the x18 configuration is used when the input signal EN is at a low level and the x18 configuration is used. When the data input signals Din and x36 are configured, the input signal EN is fixed at a high level. These changes are made by bonding options.

  In this embodiment, low-threshold MOSFETs are used as the MOSFETs Q0, Q1, and Q6, Q7, Q12, and Q13 marked with * for low voltage operation. This embodiment is used as an input circuit of a semiconductor integrated circuit device, operates with a large power supply voltage VDD with respect to an internal circuit, and is connected to an external terminal, so that it is higher than a MOSFET constituting the internal circuit. It is composed of a MOSFET with a value voltage (high withstand voltage). The MOSFETs Q0, Q1 and Q6, Q7 and Q12, Q13 have a small voltage applied between the gate and the source, and thus enable a low voltage operation using a low threshold voltage.

  Between the gates and sources of P-channel differential MOSFETs Q2 and Q3 whose gates are connected to the external terminals IN and VREF, N-channel MOSFETs Q22 and Q23 having gate-drain paths connected as an electrostatic breakdown protection device are provided. It is done. The ground potential of the circuit is supplied to the gates of these MOSFETs Q22 and Q23. Similarly, N-channel MOSFETs Q24 and Q25 having gate-drain paths connected as an electrostatic breakdown protection element are also connected between the gates and sources of N-channel differential MOSFETs Q4 and Q5 whose gates are connected to the external terminals IN and VREF. Is provided. These MOSFETs Q22 to Q25 are turned on to prevent gate breakdown of the differential MOSFETs Q2 to Q5 when a high voltage due to static electricity is generated at the external terminals IN and VREF.

  FIG. 5 shows an element layout diagram of an embodiment of the input circuit shown in FIG. In the figure, only the wirings constituting the common sources COMP and CMPN related to the present invention among the layout patterns of the circuit elements and the wirings connecting them are shown by bold lines. As shown in the figure, each circuit of the differential circuit section is arranged symmetrically in the vertical direction with the P-channel type differential MOSFET Q2 / Q3 and the N-channel type differential MOSFET Q4 / Q5 as the center. That is, the capacitive elements C1 and C1 ′, C2 and C2 ′, MOSFETs Q6 and Q7, Q8 and Q9, Q10 and Q11, Q12 and Q13, Q23 and Q24, Q25 and Q26, which are composed of two elements, are up and down. Arranged symmetrically. Similarly, the MOSFETs Q0 and Q1 and the capacitive elements C4 and C6 formed of one element are also vertically symmetrical corresponding to the differential MOSFETs Q2 / Q3 and Q4 / Q5.

  The circuits controlled by the control signal EN and the MOSFETs Q19 to 30 and Q14 to Q17 constituting the inverter circuit for forming the output signal are not directly involved in the differential operation, and are therefore distributed in the vertical direction. Is done. The capacitive element C1 is desirably arranged at a position that is not so far away from the MOSFETs Q0, Q2, and Q3 in order to suppress the parasitic resistance of the wiring. Further, since the capacitive element C1 is composed of an N-channel MOSFET, it is efficient to place it in the same element row as the same N-channel MOSFET in order to eliminate a useless region for well separation. Further, in order to maintain the left-right symmetry of the differential circuit, the capacitive element C1 is divided into two like C1 and C1 '. On the other hand, the capacitive element C2 added to the common source line COMN on the N-channel MOSFET side is also divided and arranged on both sides of the capacitive element C4. However, there is no particular problem even if the positions of C2, C, C2 ′, and C4 are switched. .

  FIG. 6 is a block diagram showing an embodiment of a static RAM to which the present invention is applied. The static RAM of this embodiment is formed on a single semiconductor substrate such as single crystal silicon by a known CMOS integrated circuit manufacturing technique.

  The static RAM has an address space with a plurality of bits m and n of address signals AX and AY. The data input signal Din is input from the terminal 3. The output signal DQ is output from the terminal 3. The data input signal Din and the output signal DQ are composed of, for example, 36 bits, and reading and writing are performed in parallel through the terminal 3. In the memory array, static memory cells are arranged in a matrix at intersections of word lines and complementary bit lines. The X address signal AX supplied from the terminal 3 is taken into the address latch 2 through the input circuit 1 constituting the address buffer. The Y address signal AX supplied from the terminal 3 is taken into the address latch 2 through the input circuit 1 constituting the address buffer. The clock signal CLK is taken in through the input circuit 1 constituting the clock buffer. Control signals / R, / W for read / write control are taken in through the input circuit 1 constituting the control buffer. These input circuits 1 take in the respective input signals AX, AY, Din, CLK, / R, / W using the reference voltage VREF input from the terminal 3. The input circuit of the above embodiment is applied to these various input circuits 1.

  The address latch 2 takes in an n-bit X address signal and transmits it to the X decoder. The address latch 2 takes in an m-bit Y address signal and transmits it to the Y decoder. The X decoder and Y decoder select the memory cell of the memory array by decoding the address signal. During the read operation, the sense amplifier 7 operates to sense the storage information of the selected memory cell and read the output signal DQ from the terminal 3 through the output control circuit 8 and the output circuit 9. In the write operation, the write driver 6 operates to write the write signal Din taken into the latch circuit 2 into the selected memory cell of the memory array. The control circuit 4 forms a capture timing signal of the latch circuit 2 and a timing signal corresponding to the read operation and write operation.

  In this embodiment, the high-speed operation in the input circuit 1 as described above improves the setup / hold margin in the latch (register) 2 that takes in the address signals AX and AY and the data input signal Din, and the data output signal DQ The clock access time can be improved.

  The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, when a differential amplifier circuit is used as an input circuit, a complementary input signal may be supplied to the input circuit. A complementary output signal may be obtained from the input circuit. In addition to such an input circuit, the differential amplifier circuit of the above embodiment can also be used as a comparator such as a voltage comparison circuit. N-channel MOSFET differential input circuit, P-channel MOSFET differential input circuit, or an input circuit combining an N-channel MOSFET differential input circuit and a P-channel MOSFET differential input circuit as shown in FIG. Is possible. The present invention includes a high-speed memory circuit such as the static RAM as described above, an input circuit such as various digital integrated circuits that require high-speed operation, or a differential amplifier circuit that constitutes the voltage comparison circuit or the like. It can be widely used for semiconductor integrated circuit devices.

1 is a circuit diagram showing an embodiment of an input circuit provided in a semiconductor integrated circuit device according to the present invention. FIG. 2 is an operation explanatory diagram of one circuit of FIG. 1. FIG. 6 is another operation explanatory diagram of the circuit of FIG. 1. 1 is a circuit diagram showing one embodiment of an input circuit provided in a semiconductor integrated circuit device according to the present invention. FIG. FIG. 5 is an element layout diagram of an embodiment of the input circuit shown in FIG. 4. 1 is a block diagram showing an embodiment of a static RAM to which the present invention is applied. It is a circuit diagram of the amplifier circuit examined prior to the present invention. FIG. 8 is a circuit diagram of a bias circuit used in the amplifier circuit of FIG. 7. FIG. 9 is an operation explanatory diagram of one circuit of FIG. 8. FIG. 9 is another operation explanatory diagram of the circuit of FIG. 8.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Input circuit, 2 ... Latch circuit, 3 ... Terminal, 4 ... Control circuit, 5 ... Decoder, 6 ... Write driver, 7 ... Sense amplifier, 8 ... Output control circuit, 9 ... Output circuit, Q0-Q31 ... MOSFET, C1 to C6: Capacitance elements.

Claims (5)

A first conductivity type first differential MOSFET pair having a gate connected to a pair of first input terminals, a first capacitor means and a first conductivity type provided in a first common source of the first differential MOSFET pair. A first amplifying unit having a first current source MOSFET;
A second differential MOSFET pair of the second conductivity type having a gate connected to the pair of first input terminals, a second capacitor means provided in a second common source of the first differential MOSFET pair, and a second conductivity A second amplifier having a second current source MOSFET of the type;
A first output unit including a second conductivity type first MOSFET pair for supplying a current flowing through the first differential MOSFET pair and a second conductivity type third MOSFET pair in series with each of the first MOSFET pair;
A first output type second MOSFET pair for supplying a current flowing through the second differential MOSFET pair, and a second output unit including a first conductivity type fourth MOSFET pair in series with each of the second MOSFET pair. Including
The corresponding drains of the third MOSFET pair and the fourth MOSFET pair are connected to form a pair of output terminals,
A semiconductor integrated circuit device comprising a differential amplifier circuit that supplies a bias voltage to the gates of the first and second current source MOSFETs and the first to fourth MOSFETs. In claim 1,
A first conductivity type third differential MOSFET pair whose gates are connected to a pair of second input terminals, respectively, and a first conductivity type third current source MOSFET provided in a common source of the third differential MOSFET; A third amplification unit;
A second conductivity type fourth differential MOSFET pair having a gate connected to the pair of second input terminals, respectively, and a second conductivity type fourth current source MOSFET provided in a common source of the fourth differential MOSFET; A fourth amplification unit having
A third output section having a second conductivity type fifth MOSFET pair for supplying a current flowing through the third differential MOSFET pair and a second conductivity type seventh MOSFET pair in series with each of the fifth MOSFET pair;
A fourth output section having a first conductivity type sixth MOSFET pair for supplying a current flowing through the fourth differential MOSFET pair and a second conductivity type eighth MOSFET pair in series with each of the sixth MOSFET pair; ,
The drains of the seventh MOSFET pair and the eighth MOSFET pair, the gate of the third current source MOSFET, the gate of the fourth current source MOSFET, the gate of the fifth MOSFET pair, and the gate of the sixth MOSFET pair are connected in common. A bias circuit for generating the first Bayesian voltage,
The first bias voltage is applied to the gate of the first current source MOSFET, the gate of the second current source MOSFET, the gate of the first MOSFET pair, and the gate of the second MOSFET pair of the differential amplifier circuit. A semiconductor integrated circuit device. In claim 2,
A voltage dividing circuit that divides the operating voltage and generates second and third bias voltages that are respectively absolutely larger than the first bias voltage corresponding to the conductivity type of the MOSFET;
The second baice voltage is supplied to the gate of the third MOSFET pair and the gate of the seventh MOSFET pair of the second conductivity type,
The semiconductor integrated circuit device, wherein the third bias voltage is supplied to a gate of the fourth MOSFET pair of the first conductivity type and a gate of the eighth MOSFET pair of the bias circuit. In claim 3,
A semiconductor integrated circuit device, wherein a capacitance element is added to a circuit node to which the first to third bias voltages are applied. In claim 4,
The differential amplifier circuit is an input circuit, and the pair of first input terminals are connected to external terminals,
The input circuit further includes an electrostatic protection circuit,
The electrostatic protection circuit is
A source-drain path of the first protection MOSFET of the second conductivity type is connected between the gate and source of the first differential MOSFET pair,
A source-drain path of a second protection MOSFET of the first conductivity type is connected between the gate and source of the second differential MOSFET pair,
The semiconductor integrated circuit device, wherein the gates of the first protection MOSFET and the second protection MOSFET are connected to a circuit ground potential.

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