JP3698929B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a plurality of (many) write ports and a single-ended write bit line.
[0002]
[Prior art]
In general, various improvements have been made in a semiconductor memory device in order to improve the degree of integration, and in particular, a reduction in the number of elements, a reduction in the area for wiring, and the like. In particular, in a semiconductor memory device having many write ports according to the present invention, since the area is remarkably increased, a read bit line is made single-ended as an improvement.
[0003]
That is, in recent years, with the increase in the number of arithmetic units on a chip, the number of ports has further increased, and further reduction in area has been demanded. To meet such a demand, for example, “S. Hesley, et al.,” A 7th-Generation x86 Microprocessor ", 1999 IEEE International Solid-State Circuits Conference Digest of technical Papers, pp.92-93, 1999" Has been.
[0004]
As shown in FIG. 10, the technique disclosed in this prior art document connects one write bit line 107 to an n-channel MOS pass transistor 104 having a write word line 106 connected to the gate terminal, and pull-down. By connecting to the gate terminal of the n-channel MOS transistor 102 and connecting the drain terminal of the pull-down transistor 102 to the n-channel MOS pass transistor 105 to which the write word line 106 is connected to the gate terminal, pseudo differential writing is performed. Is realized.
[0005]
In FIG. 10, a pass transistor 104 is provided between one node 108 and a write bit line 107 of the memory portion 101 by a pair of inverters, and a path is provided between the other node 109 and the drain of the pull-down transistor 102. A transistor 105 is provided, and the gates of both the pass transistors 104 and 105 are connected to the write word line 106. The write bit line 107 is connected to the gate of the pull-down transistor 102.
[0006]
In such a configuration, when the write data of the write bit line 107 is at low level, the word line 106 is set to high level, whereby the low level is written to one node 108 via the pass transistor 104 and the write bit line 107 is written. When the data is at the high level, the low level is written to the other node 109 through the pull-down transistor 102 and the pass transistor 105 by setting the word line 106 to the high level.
[0007]
[Problems to be solved by the invention]
However, this conventional technique requires a total of three pull-down transistors (102) and two pass transistors (104, 105) at each port of the write. Similarly, the number of transistors (202, 204, 205) increases, and the area for wiring routing and connection also increases. Reference numerals 206 and 207 denote a write word line and a write bit line which are added as the number of write ports increases.
[0008]
As the number of write ports further increases, the transistor region and the wiring routing and connection regions increase accordingly, so the effect of reducing the area of the multi-port semiconductor memory device due to the single-ended write bit line is reduced. There is. This becomes more noticeable as the number of wiring processes increases. Furthermore, since the length of the word line and the bit line is determined from the area of the semiconductor memory device, if the area reduction effect is small, the wiring length reduction effect is also small. For this reason, there is a problem that the delay reduction effect is also reduced.
[0009]
An object of the present invention is to provide a semiconductor memory device with a small area increase even when the number of write ports increases.
[0010]
[Means for solving the problems]
According to the present invention, there is provided a semiconductor memory device in which write bit line data is written in a memory portion comprising an inverter pair by control of a word line, between one node of the inverter pair and the write bit line. A pass transistor having a gate connected to the word line, a pull-down transistor provided between the other node of the inverter pair and a ground potential, and between the gate of the pull-down transistor and the write bit line And a pass transistor having a gate connected to the word line, and a pull-down element provided between the gate of the pull-down transistor and a ground potential.
[0011]
Corresponding to the addition of the write port, a pass transistor having a gate connected to the added word line is added between the one node and the added write bit line, and the gate of the pull-down transistor is added. A pass transistor having a gate connected to the added word line is added between the write bit line and the added write bit line.
[0012]
The pull-down element may be a resistor, an n-channel transistor whose gate is connected to a power supply potential, or a p-channel transistor whose gate is connected to the output of the inverter whose word line is connected to the input. Furthermore, a parallel circuit configuration of an n-channel transistor whose gate is connected to the power supply potential and a p-channel transistor whose gate is connected to the word line may be used.
[0013]
The operation of the present invention will be described. In the write portion of the semiconductor memory circuit, an operation is performed in which signals selected by a plurality of write port pass transistors are input to the gate of a pull-down transistor for generating inverted data of the write bit line. Therefore, it is not necessary to prepare a pull-down transistor for each addition of a write port, and it is only necessary to add two pass transistors, and an effect of suppressing an increase in the transistor area and the wiring connection area can be obtained.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
In order to clarify the objects, features, and advantages of the present invention, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention, and the same parts as those in FIG. 10 are denoted by the same reference numerals. Referring to FIG. 1, a semiconductor memory device (read port is omitted) having one write port as an embodiment of the present invention is shown.
[0015]
The semiconductor memory device includes an inverter pair 101, a pull-down nMOS transistor 102, a pull-down element 103, nMOS pass transistors 104 and 105, a write word line 106, and a write bit line 107. Write data is supplied from the write bit line 107, and is supplied to one node 108 of the inverter pair 101 via the nMOS pass transistor 104 whose gate is connected to the write word line 106.
[0016]
A pull-down nMOS transistor 102 is provided between the other node 109 of the inverter pair 101 and the ground potential, and the gate of the transistor 102 is connected via a pass transistor 105 having a word line 106 connected to the gate. The write bit line 107 is connected, and a pull-down element 103 is disposed between the gate of the transistor 102 and the ground potential.
[0017]
When the write data on the write bit line 107 is at low level, the low level is written to the node 108 via the pass transistor 104, and when the write data on the write bit line 107 is at high level, via the pass transistor 105. A low level is written to the other node 109 via the pull-down transistor 102. The pull-down element 103 connected to the gate of the pull-down transistor 102 prevents erroneous writing due to the gate of the pull-down transistor 102 becoming a floating node. The resistance value of the pull-down element 103 may be high and the influence on the write operation is small.
[0018]
Referring to FIG. 2, a semiconductor memory device (read port is omitted) having two write ports is shown as another embodiment of the present invention. In this semiconductor memory device, nMOS pass transistors 204 and 205, a write word line 206, and a write bit line 207 are added to the semiconductor memory device of FIG.
[0019]
The pass transistor 204 is disposed between the write bit line 207 and one node 108 of the inverter pair 101 with the write word line 206 connected to the gate. The pass transistor 205 is arranged between the write bit line 207 and the gate of the pull-down transistor 102 with the write word line 206 connected to the gate. In this way, when adding a write port, the addition of an element is merely the addition of two transistors.
[0020]
Referring to FIG. 3, an example of the pull-down element 103 of FIG. 1 is shown. That is, this is an example in which a resistor 110 is used as the pull-down element 103 in FIG. Thus, the process described above is executed. The inverter pair 101 shown in the figure is well known to those skilled in the art, and since it is not directly related to the present invention, its detailed configuration is omitted. Further, the read port circuit is omitted from the drawing because it is not mentioned here.
[0021]
Hereinafter, the operation of the present embodiment will be described. First, the write operation when the resistor 110 is used as the pull-down element 103 will be described with reference to the timing chart of FIG. Since this is a pseudo differential operation, the operation differs depending on whether the write data is at a high level or a low level. When the data on the write bit line 107 is at a high level and the word line 106 is at a high level, one node 108 of the inverter pair 101 is pulled up to a high level via the pass transistor 104, and the other node 109 is a pass transistor. After passing through 105, the pull-down transistor 102 is turned on and pulled down to a low level.
[0022]
Since one node 108 passes through the pass transistor 104, the so-called Vt, which decreases by the threshold value of that transistor, drops, and it is difficult to write a high level. However, a low level is written to the other node 109, so a high level is written. Become a level. When the word line 106 becomes low level, the gate of the pull-down transistor 102 is gradually pulled down to low level by the pull-down resistor 110, and the pull-down transistor is turned off.
[0023]
When the data on the write bit line 107 is at a low level, when the word line 106 is at a high level, one node 108 of the inverter pair 101 is pulled down to a low level via the pass transistor 104, and the other is connected to the pull-down transistor 102. It remains off and the low level is written. When the word line 106 becomes low level, the inverter pair 101 is disconnected from the bit line 107 and holds data.
[0024]
Similarly, when the data of the bit line 107 changes when the word line 106 is at the high level, writing is performed according to the change of the bit line 107. When the data on the bit line 107 is at a high level, the high level of the signal after passing through the pass transistors 104 and 105 drops by so-called Vt. The gate of the pull-down transistor 102 that has passed through the pass transistor 105 is further lowered by the pull-down resistor 110 than the Vt drop of Vdd, but the pull-down transistor 102 contributes to the lowering of the other node 109 of the inverter pair 101, and the high level is increased. Written.
[0025]
When the data on the bit line 107 is at low level, one node 108 after passing through the pass transistor 104 is pulled down to low level, and the gate of the pull-down transistor 102 after passing through the pass transistor 105 is pulled down to low level to turn off. The low level is written. It is apparent that writing is performed by the same operation when the write port is added in FIG.
[0026]
As another embodiment of the present invention, the basic configuration is as described above, but the pull-down element 103 is further devised. The configuration is shown in FIG. Referring to FIG. 5, the pull-down element 103 of FIG. 1 is configured as follows. That is, the nMOS transistor 111 whose gate is connected to Vdd. This can be easily realized as compared with the case where a high resistance element is made with high accuracy. The same processing as described above is executed, and the timing chart is also the same as FIG.
[0027]
The pull-down element 103 in FIG. 1 is also configured as shown in FIG. That is, the output of the inverter 112 having the write word line 106 connected to the input terminal is composed of the nMOS transistor 111 connected to the gate. When the word line is at the high level, the pull-down resistor is increased and the influence on the write operation can be reduced.
[0028]
The operation of this embodiment is executed according to the timing chart of FIG. That is, when the word line 106 is at a high level, the inverter 112 outputs a low level and the pull-down transistor 111 is turned off. When the word line 106 is at a low level, the inverter 112 outputs a high level and the pull-down transistor 111 is turned on. It becomes.
[0029]
In this way, since the driving force for pulling down the gate terminal of the pull-down transistor 102 when the word line 106 is at a high level write is suppressed, the gate of the pull-down transistor 102 is further increased when the data on the word bit line 107 is at a high level. The terminal voltage increases. Therefore, high-level writing can be performed at higher speed, and the power supply voltage can be further reduced, thereby reducing power consumption. Furthermore, in this embodiment, since the driving force for pulling down the gate of the pull-down transistor 102 when the word line 106 is held at a low level is increased, erroneous writing due to noise or the like can be further prevented.
[0030]
In the present embodiment, the effects of reducing the write delay and improving the noise margin can be obtained. In this example, when a port is added, a write word line 106 is added accordingly. In this case, the inverter 112 may be a multi-input NOR gate.
[0031]
In the configuration of FIG. 6, the pull-down element 103 (inverter 112 + nMOS transistor 111) is also configured as shown in FIG. In FIG. 8, a pull-down element 103 has a parallel connection configuration of a pMOS transistor 113 having a write word line 106 connected to the gate and an nMOS transistor 111 having a gate connected to Vdd. In addition to the same effects as in FIG. 6, the inverter 112 can be omitted by using pMOS. The nMOS transistors 111 connected in parallel serve as an auxiliary to the pMOS transistor 113 which cannot realize the ground (GND) level due to the drop of Vt.
[0032]
Also in this example, when a write port is added, each additional write word line may be connected to each input of the OR gate using a multi-input OR gate at the gate of the transistor 113.
[0033]
FIG. 9 is a diagram showing the effect of the present invention, and summarizes the relationship between the number of write ports and the number of write elements. When the number of write ports increases, the increase in the number of transistors can be suppressed according to the present invention, and accordingly, an increase in the area for connection and wiring can be suppressed. It should be noted that the present invention is not limited to the above-described embodiments, and it is obvious that each embodiment can be appropriately changed within the scope of the technical idea of the present invention.
[0034]
【The invention's effect】
As described above, according to the present invention, the increase in the number of transistors when adding a write port can be suppressed to two, and when dealing with a large number of write ports, the number of transistors can be significantly reduced. Therefore, it is possible to significantly reduce the dedicated area, and conversely, there is an effect that an improvement in the degree of integration can be expected.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a first embodiment of the present invention.
FIG. 2 is a circuit diagram of a second embodiment of the present invention.
3 is a circuit diagram showing an example of a pull-down element in the circuit of FIG. 1. FIG.
FIG. 4 is a time chart for explaining the operation of the present invention.
5 is a circuit diagram showing another example of the pull-down element in the circuit of FIG. 1. FIG.
6 is a circuit diagram showing still another example of the pull-down element in the circuit of FIG. 1. FIG.
7 is a time chart for explaining the operation of FIG. 6; FIG.
8 is a circuit diagram showing another example of a pull-down element in the circuit of FIG. 1. FIG.
FIG. 9 is a chart showing the effect of suppressing increase in the number of elements of the present invention.
FIG. 10 is a circuit diagram of a conventional embodiment.
FIG. 11 is a circuit diagram of another conventional embodiment.
[Explanation of symbols]
101 Inverter pair 102 Pull-down nMOS transistor 103 Pull-down element 104, 105, 204, 205 nMOS pass transistor 106, 206 Write word line 107, 207 Write bit line 108 One node 109 of the inverter pair 109 Another node 110 of the inverter pair Pull-down resistor 111 Pull-down nMOS transistor 112 Inverter 113 Pull-down pMOS transistor

Claims (7)

A semiconductor memory device in which write bit line data is written into a memory portion comprising an inverter pair by controlling a word line, the word line provided between one node of the inverter pair and the write bit line A pass transistor having a gate connected thereto, a pull-down transistor provided between the other node of the inverter pair and a ground potential, and the word line provided between the gate of the pull-down transistor and the write bit line And a pull-down element provided between the gate of the pull-down transistor and a ground potential. Corresponding to the addition of the write port, a pass transistor having a gate connected to the added word line is added between the one node and the added write bit line, and the gate of the pull-down transistor is added. 2. The semiconductor memory device according to claim 1, wherein a pass transistor having a gate connected to the added word line is added between the write bit line and the added write bit line. 3. The semiconductor memory device according to claim 1, wherein the pull-down element is a resistor. 3. The semiconductor memory device according to claim 1, wherein the pull-down element is an n-channel transistor having a gate connected to a power supply potential. 3. The semiconductor memory device according to claim 1, wherein the pull-down element is an n-channel transistor in which an output of an inverter having the word line connected to an input is supplied to a gate. 3. The semiconductor device according to claim 1, wherein the pull-down element has a parallel circuit configuration of an n-channel transistor whose gate is connected to a power supply potential and a p-channel transistor whose gate is connected to the word line. Storage device. A multi-write port type having first and second word lines and first and second write bit lines, and writing write bit line data to a memory portion comprising an inverter pair by controlling the word lines A semiconductor memory device,
First and second pass transistors provided between one node of the inverter pair and the first and second write bit lines, respectively, each having a gate connected to the first and second word lines; ,
A pull-down transistor provided between the other node of the inverter pair and a ground potential;
Third and fourth pass transistors provided between the gates of the pull-down transistors and the first and second write bit lines, respectively, and gates connected to the first and second word lines, respectively.
A pull-down element provided between the gate of the pull-down transistor and a ground potential;
A semiconductor memory device comprising:

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