KR100469762B1 - C-gate circuit - Google Patents

Abstract

A Seagate circuit with faster operating speed and smaller size is disclosed. A Seagate circuit that inputs a plurality of input signals and outputs one output signal, wherein the logic signals are output when the input signals are all logic high, and the logic high is output when the input signals are all logic low, and the input signals are logic high. And the logic low, the input unit is maintained in a high impedance state, and if the output of the input unit is a logic high, the output signal is latched as a logic low, if the output of the input unit is a logic low, the output signal is latched as a logic high, When the output is in the high impedance state, the operation speed of the seagate circuit is increased by providing an output unit for outputting the output signal of the previous stage.

Description

C-gate circuit

The present invention relates to a small size and high efficiency seagate circuit provided in a semiconductor device.

Asynchronous systems are currently in the field of research and use the same circuit for data paths compared to synchronous systems.However, to eliminate clock skew, the asynchronous system eliminates the global clock and adds control circuits at each stage to provide data in a self-timed manner. send. By adding the control circuit in this way, the number of transistors increases, causing an overhead of area. Seagate circuits are typically used as control circuits.

1 is a circuit diagram of a conventional Seagate circuit.

Referring to FIG. 1, the seagate circuit 101 includes first to third stages 111, 121, and 131. The first to third stages 111, 121, and 131 include NMOS transistors NQ1 to NQ7 and PMOS transistors PQ1 to PQ5, respectively. That is, the seagate circuit 101 is composed of 12 MOS transistors.

The seagate circuit 101 outputs the value of the output signal Z as shown in Table 1 according to the values of the input signals A and B.

A B Z 0 0 0 0 One Stay full One 0 Stay full One One One

However, the conventional seagate circuit 101 is composed of all twelve MOS transistors NQ1 to NQ7 and PQ1 to PQ5 as shown in FIG. The larger the number of MOS transistors, the slower the operation speed of the seagate circuit 101 and the larger the size. Today, since the operation speed and the size of a small circuit is required, it is necessary to make the operation speed of the Seagate circuit 101 faster and to reduce its size.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a seagate circuit having a faster operating speed and a smaller size.

1 is a circuit diagram of a conventional Seagate circuit.

2 is a circuit diagram of a seagate circuit according to the present invention.

3 is a waveform diagram illustrating a result of simulating the circuit of FIG. 2.

<Explanation of symbols for the main parts of the drawings>

101,201; Seagate circuits, 111,121,131; First to third stages 211; Input unit 221; Output

225; Inversion 227; Latch

In order to achieve the above technical problem, the seagate circuit according to the present invention may include a plurality of input signals and a single output signal. The seagate circuit may output a logic low when the input signals are all logic high, and the input signals may be all. An input unit configured to output a logic high when the logic is low, and to maintain the high impedance when the input signals include both the logic high and the logic low; And latching the output signal as logic low if the output of the input is logic high, and latching the output signal as logic high if the output of the input is logic low, and outputting the output signal of the previous stage if the output of the input is high impedance. And an output unit.

The input unit has a power supply voltage applied to a source, a first PMOS transistor having a first input signal input to a gate, a source connected to a drain of the first PMOS transistor, and the second input signal being input to a gate. A second PMOS transistor outputting an output of the input unit from a drain, a first NMOS transistor having a drain connected to a drain of the second PMOS transistor, and the second input signal being input to a gate; And a drain connected to the source of the first NMOS transistor, the first input signal input to a gate, and the source having a second grounded NMOS transistor.

Further, when the input signals are all logic high, the size of the first and second NMOS transistors is small so that the output of the input portion is sufficiently kept logic low.

The output unit may include an inverting unit for inverting the output of the input unit and outputting the output signal of the seagate, and a latch unit for latching the output signal of the seagate.

The inverting unit may include a third PMOS transistor in which the power supply voltage is applied to a source, an output of the input unit is input to a gate, and a drain of the third PMOS transistor and a drain of the third PMOS transistor are outputted from a drain. Connected, the output of the input is input to the gate, and the source has a grounded third NMOS transistor.

In addition, the latch unit may include a power supply voltage applied to a source, an output signal of the seagate is input to a gate, and a drain of a fourth PMOS transistor connected to gates of the third PMOS transistor and the third NMOS transistor, and the fourth PMOS transistor; A drain is connected to the drain of the 4 PMOS transistor, an output signal of the seagate is input to the gate, and the source includes a fourth NMOS transistor grounded.

In addition, when the input signals are all logic low, the size of the fourth NMOS transistor is large so that the output of the input unit is sufficiently kept logic high.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a circuit diagram of a seagate circuit according to the present invention.

Referring to FIG. 2, the seagate circuit 201 of the present invention inputs a plurality of input signals INA and INB and outputs one output signal OUT. In addition, an input unit 211 and an output unit 221 are provided.

The input unit 211 outputs a logic low when the input signals INA and INB are logic high, and outputs a logic high when the input signals INA and INB are logic low. . In addition, when one of the input signals INA and INB is logic high and the other is logic low, the output of the input unit 211 is maintained in a high impedance state.

The input unit 211 includes first and second PMOS transistors PQ1 and PQ2 and first and second NMOS transistors NQ1 and NQ2. Therefore, when the input signals INA and INB are all logic low, both the first and second PMOS transistors PQ1 and PQ2 are turned on and the first and second NMOS transistors NQ1 and NQ2 are both Since it is off, the output V1 of the input unit is logic high, and when the input signals INA and INB are both logic high, the first and second PMOS transistors PQ1 and PQ2 are both off and the first and Since the second NMOS transistors NQ1 and NQ2 are both turned on, the output V1 of the input unit becomes logic low.

Since the sizes of the first and second NMOS transistors NQ1 and NQ2 are large, the output V1 of the input unit is sufficiently low when the input signals INA and INB are all logic high.

The output unit 221 latches the output signal OUT as a logic low when the output V1 of the input unit is logic high, and outputs the output signal OUT as a logic high when the output V1 of the input unit is logic low. Latch it. The output unit 221 also outputs the output signal of the previous stage when the output V1 of the input unit is in the high impedance state. For example, when the output V1 of the input unit is in the high impedance state, the output unit 221 outputs logic high when the output signal of the previous stage is logic high, and the output unit 221 outputs logic low when the output signal of the previous stage is logic low. Output

The output unit 221 includes an inverting unit 225 and a latching unit 227.

The inverting unit 225 inverts the output V1 of the input unit and outputs the output signal OUT. The inverting unit 225 includes a third PMOS transistor PQ3 and a third PMOS transistor in which a power supply voltage Vdd is applied to a source, an output V1 of an input unit is input to a gate, and an output signal OUT is output from a drain. A drain is connected to the drain of PQ3, an output V1 of the input unit is input to the gate, and the source includes a third NMOS transistor NQ3 grounded. Therefore, when the output V1 of the input part is logic high, the third PMOS transistor PQ3 is turned on and the third NMOS transistor NQ3 is turned off, so the output signal OUT is turned to logic low, and the output V1 of the input part is When the logic low, the third PMOS transistor PQ3 is turned off and the third NMOS transistor NQ3 is turned on, so the output signal OUT is turned to logic high.

The latch unit 227 latches the output signal OUT. In the latch unit 227, a fourth voltage connected to the gates of the third PMOS transistor PQ3 and the third NMOS transistor NQ3 is applied to the source voltage Vdd, a source, an output signal OUT, and a drain thereof. A drain is connected to the PMOS transistor PQ4 and the drain of the fourth PMOS transistor PQ4, the output signal OUT is input to the gate, and the source has a fourth NMOS transistor NQ4 grounded. Accordingly, when the output signal OUT is logic high, the fourth PMOS transistor PQ4 is turned off and the fourth NMOS transistor NQ4 is turned on, thereby causing the third PMOS transistor PQ3 of the inverting unit 225 to be turned on and output. Signal OUT is latched as logic high. In addition, when the output signal OUT is logic low, the fourth PMOS transistor PQ4 is turned on and the fourth NMOS transistor NQ4 is turned off so that the third NMOS transistor NQ3 of the inverter 225 is turned on and output. Signal OUT is latched as logic low.

The size of the fourth NMOS transistor NQ4 of the latch portion 227 is small. Accordingly, since the resistance of the fourth NMOS transistor NQ4 is large when the output V1 of the input unit is logic high, the output V1 of the input unit is sufficiently maintained at logic high.

The truth value of the seagate circuit 201 is shown in Table 2 below.

INA INB OUT 0 0 0 0 One Stay full One 0 Stay full One One One

FIG. 3 is a waveform diagram illustrating a result of HSPICE simulation of the circuit of FIG. 2.

As shown in FIG. 3, when the input signals INA and INB are all logic high, the output signal OUT is logic high. When the input signals INA and INB are all logic low, the output signal OUT is logic high. It turns out that when the logic signal is low and one of the input signals INA and INB is logic high and the other is logic low, the output signal OUT maintains the state of the previous stage.

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

As described above, according to the Seagate circuit according to the present invention, since the number of MOS transistors provided in the Seagate circuit 201 is much smaller than that of the conventional Seagate circuit 101, the operation speed of the Seagate circuit 201 is faster, the size of the Is also reduced. The size of the seagate circuit 201 of the present invention is reduced by about 33% compared to the conventional seagate circuit 101.

Claims (7)

A seagate circuit for inputting a plurality of input signals and outputting one output signal, An input unit configured to output a logic low when the input signals are all logic high, and output a logic high when the input signals are all logic low, and to maintain a high impedance state when the input signals include both logic high and logic low; And When the output of the input unit is logic high, the output signal is latched as logic low. When the output of the input unit is logic low, the output signal is latched as logic high. Seagate circuit comprising an output unit for outputting the. The method of claim 1, wherein the input unit A first PMOS transistor, in which a power supply voltage is applied to the source and a first input signal is input to the gate; A second PMOS transistor having a source connected to a drain of the first PMOS transistor, a second input signal input to a gate, and an output of the input unit output from the drain; A first NMOS transistor having a drain connected to a drain of the second PMOS transistor and having the second input signal input to a gate; And And a drain connected to the source of the first NMOS transistor, the first input signal to a gate, and the source having a second grounded second NMOS transistor. 3. The seagate circuit according to claim 2, wherein the size of the first and second NMOS transistors is small so that the output of the input portion is sufficiently kept logic low when the input signals are all logic high. The method of claim 1, wherein the output unit An inverting unit for inverting the output of the input unit and outputting the output signal of the seagate; And And a latch unit for latching an output signal of the seagate. The method of claim 4, wherein the inversion unit A third PMOS transistor, wherein the power supply voltage is applied to a source, an output of the input unit is input to a gate, and an output signal of the seagate is output from a drain; And And a drain connected to a drain of the third PMOS transistor, an output of the input unit is input to a gate, and a source having a grounded third NMOS transistor. The method of claim 5, wherein the latch unit A fourth PMOS transistor connected to the source voltage, a source signal of the seagate, and a drain connected to gates of the third PMOS transistor and the third NMOS transistor; And And a drain connected to the drain of the fourth PMOS transistor, an output signal of the seagate is input to the gate, and a source having a fourth grounded NMOS transistor. 7. The seagate circuit according to claim 6, wherein the size of the fourth NMOS transistor is large so that the output of the input portion is sufficiently kept logic high when the input signals are all logic low.