KR100521351B1 - Full adder - Google Patents

Abstract

The full adder circuit of the present invention uses CMOS logic at the front end to improve driving capability, and transfer gates at the output end for fast data transfer. The full adder of the present invention used a single input similar to the structure of a single-rail but without the need for inverted input signals. Thus, the full adder circuit of the present invention has a high operating speed, which is an advantage of a double-rail (CPL), and low power and high integration, which is an advantage of a single-rail (LEAP).

Description

Full adder {FULL ADDER}

The present invention relates to logic circuits and, more particularly, to a full adder.

The number, speed, power consumption, and layout of transistors are very important criteria in designing logic circuits.

IEEE J. of Solid-state Circuits, vol. 32, no. 7, "Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic," by Reto Zimmenrmmann and Wolfgang Fichtner, published in pp. 779-1090, July, 1997, compares CMOS full adders and full adders using pass-transistor logic. .

There are many types of full adders implemented in CMOS, but in particular, CMOS full adders implemented with 28 transistors have excellent performance. However, due to the transistors connected in series with the output terminal, the output driving ability is reduced, thereby increasing the delay time, and the power consumption is increased by the short current of the CMOS logic itself.

Of the full adders using pass transistor logic, the dual adder (CPL), which receives the complementary signal, is the fastest in terms of speed compared to the full adder using the single-rail (LEAP). Excellent performance However, there is a disadvantage in that power consumption and layout are increased due to the increase of wires due to the use of the double-rail.

In other words, the CMOS full adder has a high density but consumes a lot of power and is slow. The double-rail full adder implemented with pass transistor logic has a high speed but high power consumption and low integration.

Accordingly, an object of the present invention has been proposed to solve the above-mentioned problems, and is to provide a full adder capable of reducing the layout size at a high speed.

According to a feature of the present invention for achieving the object of the present invention as described above, the full adder for receiving the first and second input signals and the carry input signal and outputting the sum signal and the carry output signal: A full adder that accepts a second input signal and a carry input signal and outputs a sum signal and a carry output signal includes: a NAND gate that accepts the first and second input signals and performs a NAND operation; A noah gate for accepting the first and second input signals and performing a noa operation; A first inverter using the output signal of the NOR gate as a first voltage source and inverting the output signal of the NAND gate; A second inverter using the output signal of the NAND gate as a second voltage source and inverting the output signal of the NOR gate; A P-channel MOS transistor having a drain connected to the output terminal of the NOR gate, a source connected to the output terminal of the first inverter, and a gate controlled by the first input signal; An N-channel MOS transistor having a drain connected to an output terminal of the NAND gate, a source connected to an output terminal of the first inverter, and a gate controlled by the first input signal; And controlled by the carry input signal and the inverted input carry signal to selectively output a signal of an output terminal of the first inverter or a signal of an output terminal of the second inverter as the sum signal, and an output signal of the NAND gate. Or output means for selectively outputting the output signal of the NOR gate as the carry output signal.

In a preferred embodiment, the output means comprises: a first transmission gate having an input terminal and an output terminal and controlled by the carry input signal and the inverted carry input signal to transfer the output of the first inverter as the sum signal; A second transmission gate having an input terminal and an output terminal and controlled by the carry input signal and the inverted carry input signal to transfer the output of the second inverter as the sum signal; A third transmission gate having an input terminal and an output terminal and controlled by the carry input signal and the inverted carry input signal to transfer an output of the NAND gate to the carry output signal; And a fourth transmission gate having an input terminal and an output terminal and controlled by the carry input signal and the inverted carry input signal to transfer an output of the noah gate to the carry output signal.

In a preferred embodiment, the first inverter comprises: a P-channel MOS transistor having one current path and a gate controlled by the output of the NAND gate; And an N-channel MOS transistor having one current path and a gate controlled by the output of the NAND gate. Current paths of the P-channel MOS transistor and the N-channel MOS transistor are sequentially formed in series between a power supply voltage and an output terminal of the NOR gate.

In a preferred embodiment, the second inverter comprises: a P-channel MOS transistor having one current path and a gate controlled by the output of the NAND gate; And an N-channel MOS transistor having one current path and a gate controlled by the output of the NAND gate. Current paths of the P-channel MOS transistor and the N-channel MOS transistor are sequentially formed in series between the output terminal of the NAND gate and the ground voltage.

With such a device, it is possible to implement a high integration full adder circuit, such as a single-rail CMOS full adder, with a high operating speed, such as a double-rail full adder implemented with pass transistor logic. have.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 3.

1 is a block diagram of a full adder circuit according to a preferred embodiment of the present invention.

Referring to FIG. 1, the full adder circuit 1 according to a preferred embodiment of the present invention receives an n-bit first input signal A and an n-bit second input signal _Bi , and sums the signals. (S ₁ ~ S _n ) and carry signals (C ₁ ~ C _n ) are output. The full adder circuit 1 is composed of n full adders 10_1, 10_2,..., 10_n. The i th full adder 10_ _i adds a carry signal C _i , a first input signal A _i , and a second input signal B _i input from the previous stage 10_ _i-1 to add up the sum signal ( S _i ) and a carry signal C _i are output.

A detailed circuit diagram of the ith full adder among the n full adders 10_1, 10_2,..., 10_n is shown in FIG. 2. Referring to FIG. 2, the full adder 10_ _i includes inverters 12, 18, 20, 34, 36, NAND gate 14, NOR gate 16, PMOS transistor 22, and NMOS transistor 24. ), And transmission gates 26 to 32. The NAND gate 14 receives the first and second input signals A _i and B _i and performs a NAND operation. The NOR gate 16 receives the two input signals A _i and B _i and performs a NOR operation.

The first inverter 18 has a current path sequentially formed between a power supply voltage VDD and an output terminal of the NOR gate 16 and a PMOS transistor having a gate controlled by an output of the NAND gate 14. 40 and an NMOS transistor 42. The second inverter 20 has a current path sequentially formed in series between the output terminal of the NAND gate 14 and the ground voltage VSS and a PMOS transistor having a gate controlled by the output of the NOR gate 16. And an NMOS transistor 46. That is, the first inverter 18 inverts the output signal of the NAND gate 14 while the output signal of the NOR gate 16 is at a low level. The second inverter 20 inverts the output signal of the NOR gate 16 while the output signal of the NAND gate 14 is at a high level.

The PMOS transistor 22 is connected to a drain connected to an output terminal of the NOR gate 16, a source connected to an output terminal of the first inverter 18, and a gate controlled by the first input signal A _i . Have The NMOS transistor 24 has a drain connected to an output terminal of the NAND gate 14, a source connected to an output terminal of the second inverter 20, and a gate controlled by the second input signal _Bi . Have

The first transmission gate 26 has an input terminal connected to the output terminal of the first inverter 18, an output terminal connected to the input terminal of the fourth inverter 34, and the carry input signal C _i-1 and the _first terminal. 3 is controlled by the carry input signal / C _i-1 which is inverted through the inverter 12 to transmit the output of the first inverter 18 to the fourth inverter 34.

The second transmission gate 28 has an input terminal connected to the output terminal of the second inverter 20, an output terminal connected to the input terminal of the fourth inverter 34, and the carry input signal C _i-1 and the _first terminal. 3 is controlled by the carry input signal / C _i-1 , which is inverted through the inverter 12, to transfer the output of the second inverter 20 to the fourth inverter 34.

The third transmission gate 30 has an input terminal connected to the output terminal of the NAND gate 14, an output terminal connected to the input terminal of the fifth inverter 36, and the carry input signal Ci _-1 and the third terminal. The output of the NAND gate 14 is transmitted to the fifth inverter 36 by being controlled by the carry input signal / C _i-1 , which is inverted through the inverter 12.

The fourth transmission gate 32 has an input terminal connected to the output terminal of the NOR gate 16, an output terminal connected to the input terminal of the fifth inverter 36, and the carry input signal C _i-1 and the third terminal. The inverted through the inverter 12 is controlled by the carry input signal / C _i-1 to transfer the output of the NOR gate 16 to the fifth inverter 36.

The full adder of the present invention having the configuration as described above uses CMOS logic at the front end to improve driving capability, and transfer gates 26 to 32 at the output end for fast data transfer. The full adder of the present invention looks similar to the structure of a single-rail (C, / C), but uses a single input (A _i , B _i ) that no longer requires inverted signals (/ A _i , / B _i ). It was. Thus, it has a low power and high density, which is an advantage of the single-rail (LEAP), while having a high operating speed, which is the advantage of the double-rail (CPL).

Subsequently, the operation of the full adder according to the preferred embodiment of the present invention will be described with reference to FIG.

The full adder 10 operates in the same way as a truth table of a general full adder. The following table 1 is a truth table of a general full adder.

TABLE 1

As can be seen in Table 1, exclude the carry input signal (C _i-1) is when the logic "0", each of the sum signal (S _i) are the two input signals (A _i, B _i) Same as the result of the exclusive OR (EOR) operation, and the carry output signal C _i is the same as the AND operation result of the two input signals A _i and B _i . When the carry input signal C _i-1 is a logic '1', the sum signal S _i is a result of an Exclusive NOR (ENOR) operation of the two input signals A _i and B _i . And the carry output signal C _i is the same as the result of the OR operation of the two input signals A _i and B _i .

For example, while the carry input signal C _i is at a low level, the first and third transfer gates 26 and 30 are enabled, and the first and third transfer gates 26 and 30. ) Receives the outputs of the inverter 18 and the NAND gate 14 and delivers them to the inverters 34, 36, respectively.

First, when the two input signals A _i and B _i are each low level (ie, logic '0'), the output signals of the NAND gate 14 and the noah gate 16 are each high level (ie, , Logic '1'). Accordingly, the voltage source of the first inverter 18 becomes a high level and outputs an incomplete high level signal. However, the PMOS transistor 22 is turned on by the first input signal A _i so that the Noah gate ( The high level, which is the output of 16, is passed to node N1. Accordingly, the first and third transfer gates 26 and 30 respectively receive a high level, which is an output signal of the inverter 18 and the NAND gate 14, and transfer the same to the inverters 34 and 36, respectively. do. As a result, the sum signal (S _i) and the carry output signal (C _i) are respectively a low level by the inverter (34, 36).

When the two input signals A _i and B _i are at the low level and the high level, respectively, the output signals of the NAND gate 14 and the NOR gate 16 are at the high level and the low level, respectively. Thus, the output of the first inverter 18 goes low. The node N1 maintains a low level even when the PMOS transistor 22 is turned on by the low level first input signal A _i . As a result, the sum signal (S _i) and the carry output signal (C _i) are respectively the high level and the low level by the inverter (34, 36).

When the two input signals A _i and B _i are at the high level and the low level, respectively, the output signals of the NAND gate 14 and the NOR gate 16 are at the high level and the low level, respectively. Thus, the output of the first inverter 18 goes low. Since the first input signal A _i is at a high level, the PMOS transistor 22 is turned off. As a result, the sum signal (S _i) and the carry output signal (C _i) are respectively the high level and the low level by the inverter (34, 36).

When the two input signals A _i and B _i are both at a high level, the output signals of the NAND gate 14 and the NOR gate 16 are both at a low level. Thus, the output of the first inverter 18 is at a high level. Since the first input signal A _i is at a high level, the PMOS transistor 22 is turned off. As a result, the sum signal (S _i) and the carry output signal (C _i) are respectively a low level and the high level by the inverter (34, 36).

Second and fourth transfer gates 28 and 32 are enabled while the carry input signal C _i-1 is at a high level (ie, logic '1') and the second and fourth transfer gates are enabled. Reference numerals 28 and 32 transmit the outputs of the inverter 24 and the Noah gate 16 to the inverters 34 and 36, respectively.

The operation of the full adder circuit 10 with respect to the two input signals A _i , B _i while the carry input signal C _i-1 is at a high level causes the carry input signal C _i-1 to operate. Is the same as when is at the low level. One thing to note is when the two input signals A _i , B _i are both at a high level. If the two input signals A _i and B _i are both at a high level, the outputs of the NAND gate 14 and the NOR gate 16 are both at a low level. Therefore, the voltage source of the inverter 20 becomes the ground voltage GND, and the PMOS transistor 44 is turned on so that the threshold voltage V _T44 of the PMOS transistor 44 is applied to the node N2. do. At this time, since the first input signal A _i is at a high level, the NMOS transistor 24 is turned on so that the node N2 is at a completely low level. Thus, the sum signal (S _i) and the carry output signal (C _i) is at a high level both by the inverter (34, 36).

The full adder circuit 10 of the present invention as described above has an optimized performance with low power consumption and high degree of integration of a single rail (LEAP) while having a fast operating speed such as a double-rail (CPL).

3A and 3B show simulation results of CMOS, LEAP, CPL full adders and the full adder of the present invention implemented using a 0.24 μm CMOS process, and FIG. 3A shows the sum signal S _i . 3b shows the carry output signal C _i .

Table 2 below shows the simulation results shown in FIGS. 3A and 3B.

TABLE 2

As can be seen in Table 2, the full adder of the present invention has the same fast operating speed (delay time 0.3 ns) as a double-rail (CPL) full adder implemented with pass transistor logic, but is also a single-rail (LEAP). It has a high degree of integration like a CMOS full adder. Further, it can be seen that the full adder of the present invention consumes less power than the double-rail (CPL) full adder implemented with the pass transistor logic and the single-rail CMOS full adder.

While the invention has been described using exemplary preferred embodiments, it will be understood that the scope of the invention is not limited to the disclosed embodiments. Rather, the scope of the present invention is intended to include all of the various modifications and similar configurations. Accordingly, the claims should be construed as broadly as possible to encompass all such modifications and similar constructions.

According to the present invention as described above, such a device has the same high speed as a single-rail CMOS full adder while having the same fast operating speed as a double-rail full adder implemented with pass transistor logic. A full adder circuit having is implemented.

1 is a block diagram of a full adder circuit in accordance with a preferred embodiment of the present invention;

2 shows a full adder circuit according to a preferred embodiment of the present invention; And

3A and 3B show simulation results of CMOS, LEAP, CPL, and the full adder of the present invention using a 0.24 μm CMOS process.

* Description of the symbols for the main parts of the drawings *

1: full adder circuits 10_1, 10_2,. , 10_n: Full adder

12, 18, 20, 34, 36: Inverter 14: NAND gate

16: Noah gate 22, 40, 44: PMOS transistor

24, 42, 46: NMOS transistors 26, 28, 30, 32: transfer gate

Claims (7)

In a full adder that accepts first and second input signals and a carry input signal and outputs a sum signal and a carry output signal: A NAND gate that accepts and NAND the first and second input signals; A noah gate for accepting the first and second input signals and performing a noa operation; A first inverter using the output signal of the NOR gate as a first voltage source and inverting the output signal of the NAND gate; A second inverter using the output signal of the NAND gate as a second voltage source and inverting the output signal of the NOR gate; A P-channel MOS transistor having a drain connected to the output terminal of the NOR gate, a source connected to the output terminal of the first inverter, and a gate controlled by the first input signal; An N-channel MOS transistor having a drain connected to an output terminal of the NAND gate, a source connected to an output terminal of the first inverter, and a gate controlled by the first input signal; And Controlled by the carry input signal and the inverted input carry signal to selectively output the signal of the output terminal of the first inverter or the signal of the output terminal of the second inverter as the sum signal, the output signal of the NAND gate, or And output means for selectively outputting the output signal of the noah gate as the carry output signal. The method of claim 1, The output means, A first transmission gate having an input terminal and an output terminal and controlled by the carry input signal and the inverted carry input signal to transfer an output of the first inverter as the sum signal; A second transmission gate having an input terminal and an output terminal and controlled by the carry input signal and the inverted carry input signal to transfer the output of the second inverter as the sum signal; A third transmission gate having an input terminal and an output terminal and controlled by the carry input signal and the inverted carry input signal to transfer an output of the NAND gate to the carry output signal; And And a fourth transmission gate having an input stage and an output stage and controlled by the carry input signal and the inverted carry input signal to transfer an output of the noah gate to the carry output signal. The method of claim 1, The first inverter, A P-channel MOS transistor having one current path and a gate controlled by the output of the NAND gate; An N-channel MOS transistor having one current path and a gate controlled by the output of the NAND gate, And the current paths of the P-channel MOS transistor and the N-channel MOS transistor are sequentially formed in series between a power supply voltage and an output terminal of the NOR gate. The method of claim 1, The second inverter, A P-channel MOS transistor having one current path and a gate controlled by the output of the NAND gate; An N-channel MOS transistor having one current path and a gate controlled by the output of the NAND gate, And the current paths of the P-channel MOS transistor and the N-channel MOS transistor are sequentially formed in series between the output terminal of the NAND gate and the ground voltage. In a full adder that accepts first and second input signals and a carry input signal and outputs a sum signal and a carry output signal: A NAND gate that accepts and NAND the first and second input signals; A noah gate for accepting the first and second input signals and performing a noa operation; A first inverter using the output signal of the NOR gate as a first voltage source and inverting the output signal of the NAND gate; A second inverter using the output signal of the NAND gate as a second voltage source and inverting the output signal of the NOR gate; A P-channel MOS transistor having a drain connected to the output terminal of the NOR gate, a source connected to the output terminal of the first inverter, and a gate controlled by the first input signal; An N-channel MOS transistor having a drain connected to an output terminal of the NAND gate, a source connected to an output terminal of the first inverter, and a gate controlled by the first input signal; A first transmission gate having an input terminal and an output terminal and controlled by the carry input signal and the inverted carry input signal to transfer an output of the first inverter as the sum signal; A second transmission gate having an input terminal and an output terminal and controlled by the carry input signal and the inverted carry input signal to transfer the output of the second inverter as the sum signal; A third transmission gate having an input terminal and an output terminal and controlled by the carry input signal and the inverted carry input signal to transfer an output of the NAND gate to the carry output signal; And And a fourth transmission gate having an input stage and an output stage and controlled by the carry input signal and the inverted carry input signal to transfer the output of the noah gate to the carry output signal. The method of claim 5, The first inverter, A P-channel MOS transistor having one current path and a gate controlled by the output of the NAND gate; An N-channel MOS transistor having one current path and a gate controlled by the output of the NAND gate, And the current paths of the P-channel MOS transistor and the N-channel MOS transistor are sequentially formed in series between a power supply voltage and an output terminal of the NOR gate. The method of claim 5, The second inverter, A P-channel MOS transistor having one current path and a gate controlled by the output of the NAND gate; An N-channel MOS transistor having one current path and a gate controlled by the output of the NAND gate, And the current paths of the P-channel MOS transistor and the N-channel MOS transistor are sequentially formed in series between the output terminal of the NAND gate and the ground voltage.