KR100278992B1 - Full adder - Google Patents

Abstract

The present invention relates to a full adder, and an object thereof is to reduce the chip layout area of an integrated circuit including the full adder by configuring the full adder with only a few transistors.

The full adder according to the present invention includes the first and second logic gates, a carry generator, and an island generator. The first logic gate receives the first input signal and the second input signal, and generates an output of logic value 0 when at least one of the first input signal and the second input signal is one. The second logic gate receives the first input signal and the second input signal, and generates an output of logic value 0 when the logic values of the first input signal and the second input signal are all one. The carry generator uses the output of the first logic gate as the pull-up control signal, the output of the second logic gate as the pull-down control signal, and the inverted signal of the input carry signal is used as the clock signal. The island generator includes a third logic gate, first to third transfer means, and an inverter. The third logic gate generates an output of logic value 0 when the logic value of the output of the first logic gate is zero and the logic value of the output of the second logic gate is one. The first transmission means receives the output of the third logic gate and is turned on when the logic value of the input carry signal is zero. The second transmission means receives an input carry signal and is turned on when the logic value of the output of the third logic gate is zero. The third transmission means receives the inverted signal of the input carry signal and is turned on when the logic value of the output of the third logic gate is one. The inverter receives the output of the first to third transmission means, inverts it and outputs it as an island signal.

Description

Full adder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a full adder. The present invention relates to a full adder configured to generate two island signals and a new carry signal by receiving two input signals and a carry signal of a preceding stage.

In general, the full adder is configured to generate a new island signal and a carry signal by using the addition result of two half adders. A block diagram of such a conventional general full adder is shown in Fig. 1 (a).

The full adder of FIG. 1A consists of two half adders 102 and 104 and an OR gate 106. Two input signals A and B to be added are input to the first half adder 102, and the first addition result S1 of these two input signals A and B is input to the second half adder 104. do. The second half adder 104 is input with an input carry signal C (n-1) generated in the previous addition step and added together with the first addition result S1 of the first half adder 104. The second half adder 104 outputs an island signal SUM (n) which is the final addition result. Two carry signals C1 and C2 generated by each of the half adders 102 and 104 are input to the OR gate 106. The output of this OR gate 106 is the final output carry signal C (n).

FIG. 1B is a logic circuit diagram of the half adder 102 shown in FIG. Half adder 102 is comprised of an exclusive or gate 108 and an end gate 110. Two input signals A and B to be added are input to the exclusive OR gate 108 and the AND gate 110. The addition result S1 is output at the exclusive OR gate 108, and the primary carry signal C1 is output at the AND gate 110.

The second half adder 104 of FIG. 1 (a) also has the same structure as the half adder of FIG. 1 (b), except that the output signal is an island signal SUM (n) and an output carry signal C (n). Is different.

The number of transistors required to construct such a conventional full adder is calculated as follows. Exclusive or gates have two end-or-inverter (AOI) structures, requiring a total of 12 transistors. And gate is composed of NAND gate and inverter, so all six transistors are needed. That is, 18 transistors are basically required to configure one half adder.

Since one full adder is composed of two half adders, 36 transistors are required alone, and 42 transistors are required because six transistors are added to form an OR gate for generating an output carry signal.

Since the full adder is a very popular circuit in an integrated circuit, the number of transistors in the full adder is an important cause for increasing the chip layout area of the integrated circuit. Therefore, if the number of transistors constituting the full adder is reduced, the chip layout area of the integrated circuit can be greatly reduced.

Accordingly, an object of the present invention is to reduce the chip layout area of an integrated circuit including a full adder by configuring the full adder with only a few transistors.

The full adder according to the present invention for this purpose comprises a first and a second logic gate, a carry generator, and an island generator.

The first logic gate receives the first input signal and the second input signal, and generates an output of logic value 0 when at least one of the first input signal and the second input signal is one.

The second logic gate receives the first input signal and the second input signal, and generates an output of logic value 0 when the logic values of the first input signal and the second input signal are all one.

The carry generator uses the output of the first logic gate as the pull-up control signal, the output of the second logic gate as the pull-down control signal, and the inverted signal of the input carry signal is used as the clock signal.

The island generator includes a third logic gate, first to third transfer means, and an inverter. The third logic gate generates an output of logic value 0 when the logic value of the output of the first logic gate is zero and the logic value of the output of the second logic gate is one. The first transmission means receives the output of the third logic gate and is turned on when the logic value of the input carry signal is zero. The second transmission means receives an input carry signal and is turned on when the logic value of the output of the third logic gate is zero. The third transmission means receives the inverted signal of the input carry signal and is turned on when the logic value of the output of the third logic gate is one. The inverter receives the output of the first to third transmission means, inverts it and outputs it as an island signal.

1 is a diagram showing a conventional full adder, (a) is a block diagram of a full adder, and (b) is a logic circuit diagram of a half adder.

2 is a block diagram of a full adder according to the present invention;

3 is a detailed circuit diagram of a full adder according to the present invention.

4 is a truth table of the full adder.

Explanation of symbols on the main parts of the drawings

100: full adder 102, 104: half adder

202: Carry generator 204: Island signal generator

210: conditional carry generator 212: direct carry generator

C (n-1): Input carry signal C (n): Output carry signal

SUM (n): island signal

Referring to Figures 2 to 4 a preferred embodiment of the full adder according to the present invention is as follows.

2 is a block diagram of a full adder according to the present invention.

In the full adder of FIG. 2, two input signals A and B to be added to the NOR gate 206 serving as the first logic gate and the NAND gate 210 serving as the second logic gate are input. The input carry signal C (n-1) generated at the front end is inverted by the inverter 208. The carry generator 202 and the island generator 204 receive the outputs of the NOR gate 206, the NAND gate 210, and the inverter 208, and output the output carry signal C (n) and the island signal SUM ( n)).

3 is a circuit diagram of a full adder according to the present invention. In FIG. 3, the carry generator 202 includes a conditional carry generator 210 and a direct carry generator 212.

The conditional carry generator 210 has a first to fourth switching means, that is, two PMOS transistors 214 and 216 and two NMOS transistors 218 and 220 are connected to a power supply voltage VDD and a ground VSS. Are connected in series. The PMOS transistor 214, which is the first switching means, is switched by the output of the NOR gate 206. The PMOS transistor 216 and the NMOS transistor 218 which are the second and third switching means are complementarily switched by the inverter 208 which is the inverted signal of the input carry signal C (n-1). The NMOS transistor 220 which is the fourth switching means is switched by the output of the NAND gate 210. The output carry signal C (n) is generated at a node to which the PMOS transistor 216 and the drain of the NMOS transistor 218 are connected.

In the direct carry generator 212, the PMOS transistor 222 serving as the fifth switching means and the NMOS transistor 224 serving as the sixth switching means are connected in series between the power supply voltage VDD and the ground VSS. The PMOS transistor 222 is switched by the output of the NAND gate 210, and the NMOS transistor 224 is switched by the output of the NOR gate 206. The PMOS transistor 224 and the NMOS transistor 224 generate an output carry signal C (n) at a node interconnected.

In the island generator 204, a signal in which the output of the NOR gate 206 is inverted by the inverter 226 and the output of the NAND gate 210 are input to the first NAND gate 228.

The output of the NAND gate 228 is input to the transmission gate 234 which is the first transmission means, and is turned on when the logic value of the input carry signal C (n-1) is zero. The input carry signal C (n-1) is input to the source of the PMOS transistor 232 serving as the second transfer means, and is turned on when the logic value of the output of the NAND gate 228 is zero. The inverted signal of the input carry signal C (n-1) is input to the source of the NMOS transistor 236, which is the third transfer means, and is turned on when the logic value of the output of the NAND gate 228 is one. . In the above-described NMOS transistor 232 and PMOS transistor 236, since the source and the drain are determined by the logic value (ie, the voltage level) of the input signal, it is actually meaningless to distinguish between the source and the drain.

The above-described outputs of the transmission gate 234, the PMOS transistor 232, and the NMOS transistor 236 are inverted by the inverter 238 and output as an island signal SUM (n).

The operation of the full adder according to the present invention configured as described above is divided into the case where the logic value of the output carry signal is 1 and the case where the logic value of the island signal is 1 and 0.

First, when the logic value of the output carry signal C (n) becomes 1, that is, when the carry occurs, the operation of the carry generator 202 is as follows.

According to the truth table of the full adder shown in Fig. 4, when the logic value of the output carry signal C (n) becomes 1, the two input signals A and B include at least one logical value 1, and the input carry The logic value of the signal C (n-1) is also one.

Since the two input signals A and B contain at least one logic value 1, the output of the NOR gate 206 is zero. For this reason, the PMOS transistor 214 of the conditional carry generation part 210 is turned on. At this time, since the logic value of the input carry signal C (n-1) is 1, the output of the inverter 208 becomes 0 to turn on the PMOS transistor 216. FIG. Therefore, the logic value of the output carry signal C (n) becomes one.

Another case where the logic value of the output carry signal C (n) becomes 1 is when the logic values of the two input signals A and B are all 1. In this case, the logic value of the output carry signal C (n) is not affected by the input carry signal C (n-1).

Since the logic values of the two input signals A and B are all 1, the outputs of the NOR gate 206 and the NAND gate 210 are both zero. For this reason, the PMOS transistor 222 of the carry generator 212 is turned on so that the logic value of the output carry signal C (n) becomes one. At this time, the PMOS transistor 214 and the NMOS transistor 220 of the conditional carry generator 210 are also turned on. In this case, however, if the input carry signal C (n-1) is 1, the PMOS transistor 216 is turned on so that the logic value of the output carry signal C (n) remains 1 (the PMOS transistor ( 214 is turned on), when the input carry signal C (n-1) is 0, the NMOS transistor 218 is turned on to affect the logic value of the output carry signal C (n). It does not reach (because the NMOS transistor 220 is turned off).

Next, when the logic value of the output carry signal C (n) is 0, that is, when no carry signal is generated, the operation of the carry generator 202 is as follows.

According to the truth table of the full adder shown in Fig. 4, when the logic value of the output carry signal C (n) becomes zero, the two input signals A and B include at least one logical value 0, and the input carry The logic value of the signal C (n-1) is also one.

Since the two input signals A and B include at least one zero, the output of the NAND gate 210 becomes one. For this reason, the NMOS transistor 220 of the conditional carry generator 210 is turned on. At this time, since the logic value of the input carry signal C (n-1) is zero, the NMOS transistor 218 is also turned on, and as a result, the output carry signal C (n) becomes zero.

When the logic value of the island signal SUM (n) becomes 1, it is represented by the following two cases. The first case is that both the logic values of the two input signals A and B are 0, and the input carry signal C (n-1) is 1. The second case is when the logic values of the two input signals A and B include one 1 and one 0, and the input carry signal C (n-1) is zero. Third, the logic values of the two input signals A and B are all 1, and the logic values of the input carry signal C (n-1) are also 1.

In the first case, since the logic values of the two input signals A and B are all 0, the outputs of the NOR gate 206 and the NAND gate 210 are both 1, so that the NAND gate 228 of the island generator 204 is one. The output of becomes 1 At this time, since the input carry signal C (n-1) is 1, the transmission gate 234 is not turned on. In this case, the input carry signal C (n-1) is input to the PMOS transistor 232 of the island generator 204 through the inverter 230, and the input carry signal () is input to the NMOS transistor 236. The inverted signal of C (n-1)) is input. Among them, the NMOS transistor 236 is turned on by a signal of logic value 1 output from the NAND gate 228 to convert an inverted signal (logical value 0) of the input carry signal C (n-1) into an inverter ( INV238). The inverter 238 inverts this value to generate an island signal SUM (n) of logic value 1.

In the second case, since the logic values of the two input signals A and B include one 1 and one 0, the output of the NOR gate 206 is 0 and the output of the NAND gate 210 is 1. Therefore, the output of the NAND gate 228 of the island generator 204 becomes zero. At this time, since the input carry signal C (n-1) is 0, the transmission gate 234 is turned on, and a signal having a logic value 0 output from the NAND gate 228 is transmitted to the inverter 238. The inverter 238 inverts the input value to generate an island signal SUM (n) of logic value 1.

In the third case, since the logic values of the two input signals A and B are all 1, the outputs of the NOR gate 206 and the NAND gate 210 are both zero. Therefore, the output of the NAND gate 228 of the island generator 204 is one. At this time, since the logic value of the input carry signal C (n-1) is 1, the transmission gate 234 is not turned on. In this case, the input carry signal C (n-1) of logic value 1 is input to the PMOS transistor 232, and the input carry signal C (n-1) is inverted to the NMOS transistor 236. The signal of logic value 0 is input. At this time, since the output of the NAND gate 228 is 1, the NMOS transistor 236 is turned on so that a signal having a logic value of 0 is input to the inverter 238. The inverter 238 inverts the input signal of logic value 0 to generate an island signal SUM (n) of logic value 1.

The full adder according to the present invention thus obtained achieves the same logical result as the existing technology, but has a very small number of transistors necessary for construction. Therefore, when the full adder according to the present invention is implemented as an integrated circuit, the layout area of the chip may be greatly reduced. In addition, since the carry signal is generated almost simultaneously with the input of the input signal, a large synergistic effect can be expected in terms of the operating speed.

Claims (5)

In full adder, A first logic gate configured to generate an output of a logic value 0 when a first input signal and a second input signal are input and at least one logic value of the first input signal and the second input signal is 1; A second logic gate configured to generate an output of a logic value 0 when the first input signal and the second input signal are input, and a logic value of the first input signal and the second input signal is all 1; A carry generator which uses an output of the first logic gate as a pull-up control signal, uses an output of the second logic gate as a pull-down control signal, and uses an inverted signal of an input carry signal as a clock signal; A third logic gate for generating an output of logic value 0 when the logic value of the output of the first logic gate is 0 and the logic value of the output of the second logic gate is 1, and an output of the third logic gate First transmission means input and turned on when the logic value of the input carry signal is 0, and second turning on when the logic value of the output of the third logic gate is input and the input carry signal is input; A transmission means, a third transmission means which is turned on when the inverted signal of the input carry signal is input, and a logic value of the output of the third logic gate is 1, and outputs of the first to third transmission means. A full adder comprising an island generator comprising an inverter which receives an input and inverts it to output an island signal. The method according to claim 1, wherein the carry generation unit, When the output of the first logic gate, the output of the second logic gate, the inverted signal of the input carry signal are input, and the logic value of the first input signal and the logic value of the second input signal are both one. And generating an output carry signal having a logic value of 1 regardless of the logic value of the input carry signal, wherein the logic value of the first input signal and the logic value of the second input signal are 1 and 0 or 0 and 1, respectively. An output carry signal having the same logic value as that of the input carry signal is generated. When both the logic value of the first input signal and the logic value of the second input signal are zero, the logic is independent of the logic value of the input carry signal. A full adder comprising a conditional carry generator and a direct carry generator configured to generate an output carry signal having a value of zero. The method according to claim 2, The conditional carry generation unit, First to fourth switching means are connected in series between a power supply voltage and ground, the first switching means is switched by an output of the first logic gate, and the second and third switching means are connected to each other of the input carry signal. Complementarily switched by an inverted signal, the fourth switching means being switched by the output of the second logic gate, wherein the second and third switching means are adapted to generate an output carry signal at an interconnected node. Full adder. The method of claim 2, wherein the direct carry generation unit, A fifth switching means and a sixth switching means are connected in series between the power supply voltage and the ground, the fifth switching means is switched by an output of the second logic gate, and the sixth switching means is the first logic. And a total switch configured to generate the output carry signal at a node interconnected by the fifth switching means and the sixth switching means. The method according to claim 1, The island generating unit, A first NAND gate to which an inverted output of the first logic gate and an output of the second logic gate are input; First transmission means input to an output of the first NAND gate and turned on when a logic value of the input carry signal is 0; Second transmission means input to the input carry signal and turned on when the logic value of the output of the first NAND gate is 0; Third transmission means for inputting an inverted signal of the input carry signal and being turned on when the logic value of the output of the first NAND gate is 1; And an inverter configured to receive the output of the first to third transmission means and to invert and output the output.