KR100553702B1 - Full Adder - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a full adder, and discloses a full transfer device consisting of a NAND gate, a noah gate, an inverter, a PMOS transistor, an NMOS transistor, and a transfer gate.

The full adder according to the present invention has an improved processing speed compared to the conventional full adder.

Full adder, NAND gate, Noah gate, Inverter, Transmission gate

Description

Full Adder {Full Adder}

1 is a view showing a full adder currently being provided to an ASIC Library;

2 is a view showing the configuration of a conventional full adder,

3A is a view showing a circuit configuration of a noble gate;

3b is a view showing a circuit configuration of a NAND gate;

4 is a view showing the configuration of a full adder circuit according to an embodiment of the present invention;

5A is a view showing a simulation result of the delay speed of the conventional full adder of FIG. 2 and the full adder of the present invention of FIG.

5B is a view showing simulation results for power consumption of the conventional full adder of FIG. 2 and the full adder of the present invention of FIG.

FIG. 5C is a view showing a comparison result of a product of delay speed versus power consumption of the conventional full adder of FIG. 2 and the full adder of the present invention of FIG. 4.

In the drawings according to the present invention, the same reference numerals are used for components having substantially the same configuration and function.

* Description of the symbols for the main parts of the drawings *

14: NAND Gate 16: Noah Gate

12, 18, 20, 34, 36: inverter

26, 28, 30, 32: transmission gate

The present invention relates to a logic circuit, and more particularly to a full adder.

1 is a view showing a full adder currently being provided to an ASIC Library. The full adder of FIG. 1 is a full adder widely used as a single-rail technique using a conventional dual pass-transistor (DPL) technique. To generate the sum signal, XOR / XNOR logic is used, which uses high-speed CMOS and transmission gates. However, the full adder of FIG. 1 uses an inverting circuit to generate a complementary signal to perform high-speed operation after a delay occurs for substantially two inverting stages.

In order to prevent the time delay caused by the generation of such a complementary signal, a full adder logic circuit without using the complementary signal has already been filed by the present applicant (Korean Patent Publication No. 2001-0037189: Full Adder). , May 7, 2001).

2 is a view showing the configuration of the conventionally filed invention. Referring to FIG. 2, a conventionally applied full adder is an inverter 12, 18, 20, 34, 36, a NAND gate 14, a NOR gate 16, a PMOS transistor 22, an NMOS transistor 24. And transmission gates 26-32. The NAND gate 14 receives the first and second input signals Ai and Bi and performs a NAND operation. The NOR gate 16 receives the two input signals Ai and Bi and performs a NOR operation.

The first inverter 18 has a current path sequentially formed between a power supply voltage VDD and an output terminal of the NOR gate 16 and a PMOS transistor having a gate controlled by an output of the NAND gate 14. 40 and an NMOS transistor 42. The second inverter 20 has a current path sequentially formed in series between the output terminal of the NAND gate 14 and the ground voltage VSS and a PMOS transistor having a gate controlled by the output of the NOR gate 16. And an NMOS transistor 46. That is, the first inverter 18 inverts the output signal of the NAND gate 14 while the output signal of the NOR gate 16 is at a low level. The second inverter 20 inverts the output signal of the NOR gate 16 while the output signal of the NAND gate 14 is at a high level.

The PMOS transistor 22 has a drain connected to the output terminal of the NOR gate 16, a source connected to the output terminal of the first inverter 18, and a gate controlled by the first input signal Ai. . The NMOS transistor 24 has a drain connected to the output terminal of the NAND gate 14, a source connected to the output terminal of the second inverter 20, and a gate controlled by the second input signal Bi. .

The first transmission gate 26 has an input terminal connected to the output terminal of the first inverter 18, an output terminal connected to the input terminal of the fourth inverter 34, and the carry input signal Ci-1 and the third terminal. The output of the first inverter 18 is transmitted to the fourth inverter 34 by being controlled by the carry input signal / Ci-1 which is inverted through the inverter 12.

The second transmission gate 28 has an input terminal connected to an output terminal of the second inverter 20, an output terminal connected to an input terminal of the fourth inverter 34, and the carry input signal Ci-1 and the third terminal. The output of the second inverter 20 is transmitted to the fourth inverter 34 by being controlled by the carry input signal / Ci-1 which is inverted through the inverter 12.

The third transmission gate 30 has an input terminal connected to the output terminal of the NAND gate 14, an output terminal connected to the input terminal of the fifth inverter 36, and the carry input signal Ci-1 and the third inverter. The output of the NAND gate 14 is transmitted to the fifth inverter 36 by being controlled by the carry input signal / Ci-1, which is inverted through the reference numeral 12.

The fourth transmission gate 32 has an input terminal connected to the output terminal of the noah gate 16, an output terminal connected to the input terminal of the fifth inverter 36, and the carry input signal Ci-1 and the third inverter. Controlled by the carry input signal / Ci-1, which is inverted through 12, the output of the Noah gate 16 is transmitted to the fifth inverter 36.

The operation of the conventional full adder having the above configuration will be described.

First, when the two input signals Ai and Bi are each low level (ie, logic '0'), the output signals of the NAND gate 14 and Noah gate 16 are each at a high level (ie, logic). '1'). Accordingly, the voltage source of the first inverter 18 becomes a high level to output an incomplete high level signal, but the PMOS transistor 22 is turned on by the first input signal Ai so that the Noah gate is turned on. The high level, which is the output of 16, is passed to node N1. Accordingly, the first and third transfer gates 26 and 30 respectively receive a high level, which is an output signal of the inverter 18 and the NAND gate 14, and transfer the same to the inverters 34 and 36, respectively. do. As a result, the sum signal Si and the carry output signal Ci are brought low by inverters 34 and 36, respectively.

However, there are the following problems in this case. 3A is a diagram illustrating a circuit configuration of a noah gate.

Referring to FIG. 3A, when two input signals Ai and Bi are respectively input at a low level (ie, logic '0') and a sum signal and a carry signal thereof are outputted, an output signal of the noah gate is generated. As the PMOS transistor 66 and the PMOS transistor 64 are turned on, a high level (logical '1') is output to the output terminal N1 through the current path of the PMOS transistor 22.

At this time, the output signal outputted to the output terminal N1 is output through the three transistors of the PMOS transistor 66, the PMOS transistor 64, and the PMOS transistor 22, so that a long time is required to output the signal. There is a problem.

It is assumed that both input signals Ai and Bi are at a high level. When the two input signals Ai and Bi are both at high level, the outputs of the NAND gate 14 and the NOR gate 16 are both at low level. Accordingly, the voltage source of the inverter 20 becomes the ground voltage GND, and the PMOS transistor 44 is turned on so that the threshold voltage VT44 of the PMOS transistor 44 is applied to the node N2. do. At this time, since the first input signal Ai is at a high level, the NMOS transistor 24 is turned on so that the node N2 is at a completely low level. Accordingly, the sum signal Si and the carry output signal Ci are all brought high by the inverters 34 and 36.

However, there are the following problems in this case. 3B is a diagram illustrating a circuit configuration of a NAND gate.

Referring to FIG. 3B, when two input signals Ai and Bi are respectively input at a high level (ie, logic '1') and a sum signal and a carry signal thereof are output, an output signal of the NAND gate is output. As the NMOS transistor 54 and the NMOS transistor 56 are turned on, a low level (logical '0') is output to the output terminal N2 through the current path of the NMOS transistor 24.

However, the output signal output to the output terminal (N2) is a signal is output through the three transistors of the NMOS transistor 54, the NMOS transistor 56 and the NMOS transistor 24, so it takes a long time for the signal to be output There is a problem.

The present invention was devised to solve the above problems, and an object of the present invention is to provide a full adder logic circuit having a low delay time and low power consumption.

The configuration of the present invention for achieving the above object is a full adder that receives the first and second input signals and the carry input signal and outputs a sum signal and a carry output signal: a power supply voltage (VDD) and a ground voltage ( PMOS transistors 52, NMOS transistors 54, and NMOS transistors having current paths sequentially formed in series between the VSSs and having gates controlled by the second input signal, the first input signal, and the second input signal, respectively. And a PMOS transistor 50 having a gate connected to the output terminal of the NAND gate, a source connected to the power supply voltage VDD, and controlled by a first input signal. A NAND gate that accepts two input signals and performs a NAND operation; A PMOS transistor 66 having a current path sequentially formed in series between the power supply voltage VDD and the ground voltage VSS and having a gate controlled by a first input signal, a second input signal, and a second input signal, respectively; A PMOS transistor 64, an NMOS transistor 62, and a drain are connected to an output terminal of the noble gate, a source is connected to the ground voltage VSS, and has an NMOS transistor 60 having a gate controlled by a first input signal. A noah gate configured to receive and noah the first and second input signals; A first inverter using the output signal of the NOR gate as a first voltage source and inverting the output signal of the NAND gate; A second inverter using the output signal of the NAND gate as a second voltage source and inverting the output signal of the NOR gate; A drain connected between the drain of the PMOS transistor 66 and the source of the PMOS transistor 64, a source connected to the output terminal of the first inverter 18, and a gate controlled by the second input signal Bi. A PMOS transistor having; A drain connected between the source of the NMOS transistor 54 and the drain of the NMOS transistor 56, a source connected to an output terminal of the second inverter 20, and controlled by the first input signal Ai. An NMOS transistor having a gate; And controlled by the carry input signal and the inverted input carry signal to selectively output a signal of an output terminal of the first inverter or a signal of an output terminal of the second inverter as the sum signal, and an output signal of the NAND gate. Or output means for selectively outputting the output signal of the NOR gate as the carry output signal.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention discloses a full adder designed using NAND / Nor Based Logic (NNBL) for high speed operation and low power consumption. In the full adder according to the embodiment of the present invention, no complementary signals are used so as not to be affected by the operation speed, and Nand / Nor logic is used for high speed operation.

4 is a diagram illustrating a configuration of a full adder circuit according to an exemplary embodiment of the present invention.

4, the full adder according to the embodiment of the present invention, inverters 12, 18, 20, 34, 36, NAND gate 14, NOR gate 16, PMOS transistor 22, NMOS transistor 24, and transmission gates 26-32. The NAND gate 14 receives the first and second input signals Ai and Bi and performs a NAND operation. The NOR gate 16 receives the two input signals Ai and Bi and performs a NOR operation.

The NAND gate has a current path sequentially formed in series between the power supply voltage VDD and the ground voltage VSS, and has a PMOS transistor having a gate controlled by a second input signal, a first input signal, and a second input signal, respectively. (52), an NMOS transistor (54), an NMOS transistor (56), and a drain connected to an output terminal of the NAND gate, a source connected to the power supply voltage (VDD), and a PMOS transistor having a gate controlled by a first input signal. It consists of 50.

The NOR gate has a current path sequentially formed in series between the power supply voltage VDD and the ground voltage VSS, and has a PMOS transistor having a gate controlled by a first input signal, a second input signal, and a second input signal, respectively. (66), a PMOS transistor (64), an NMOS transistor (62), and a drain connected to an output terminal of the noble gate, a source connected to the ground voltage (VSS), and an NMOS transistor having a gate controlled by a first input signal. It consists of 60.

The first inverter 18 has a current path sequentially formed between a power supply voltage VDD and an output terminal of the NOR gate 16 and a PMOS transistor having a gate controlled by an output of the NAND gate 14. 40 and an NMOS transistor 42. The second inverter 20 has a current path sequentially formed in series between the output terminal of the NAND gate 14 and the ground voltage VSS and a PMOS transistor having a gate controlled by the output of the NOR gate 16. And an NMOS transistor 46. That is, the first inverter 18 inverts the output signal of the NAND gate 14 while the output signal of the NOR gate 16 is at a low level. The second inverter 20 inverts the output signal of the NOR gate 16 while the output signal of the NAND gate 14 is at a high level.

The PMOS transistor 22 includes a drain connected between a drain of the PMOS transistor 66 and a source of the PMOS transistor 64, a source connected to an output terminal of the first inverter 18, and the second input signal ( Has a gate controlled by Bi).

The NMOS transistor 24 includes a drain connected between a source of the NMOS transistor 54 and a drain of the NMOS transistor 56, a source connected to an output terminal of the second inverter 20, and the first input signal ( Has a gate controlled by Ai).

Since the first transfer gate 26 to the fourth transfer gate 32 have the same configuration and operation characteristics as those of the conventional art, detailed description thereof will be omitted.

Hereinafter, the operation of the full adder according to the embodiment of the present invention configured as described above.

The full adder operates in the same way as a truth table of a general full adder. This is well known to those of ordinary skill in the art to which the present invention pertains through the prior art. Therefore, description of some calculation results in the truth table of the full adder is omitted, and only some calculation results are described as an example. do.

First, when the two input signals Ai and Bi are each at a low level (ie, logic '0'), the NAND gate 14 has a PMOS transistor 50 and a PMOS transistor 52 turned on and an NMOS transistor. Reference numeral 54 and NMOS transistor 56 are turned off to output a high level (ie, logic '1') as an output signal.

The NOR gate 16 has a PMOS transistor 66 and a PMOS transistor 64 turned on, and the NMOS transistor 60 and the NMOS transistor 62 turned off to output a high level (ie, logic '1') as an output signal. Output

As the NAND gate 14 and the NOA gate 16 output a high level, the voltage source of the first inverter 18 becomes a high level to output an incomplete high level signal, but the second input signal Bi The PMOS transistor 22 is turned on to transmit the high level, which is the voltage level of the drain of the PMOS transistor 66 of the NOR gate 16, to the node N1.

In this case, the voltage level transmitted to the node N1 is transmitted not the voltage level of the drain of the PMOS transistor 64 which is the voltage level of the output terminal of the NOA gate but the voltage level of the drain of the PMOS transistor 66. VDD) is transmitted through only one PMOS transistor 66 without passing through two transistors of the PMOS transistor 66 and the PMOS transistor 64, resulting in an effect of improving the speed of the full adder.

The first and third transfer gates 26 and 30 respectively receive a high level, which is an output signal of the inverter 18 and the NAND gate 14, and transmit the same to the inverters 34 and 36, respectively. As a result, the sum signal Si and the carry output signal Ci are brought low by inverters 34 and 36, respectively.

The case where both the input signals Ai and Bi are at a high level will be described. If both input signals Ai and Bi are at a high level, the NAND gate 14 may turn off the PMOS transistor 50 and the PMOS transistor 52 and the NMOS transistor 54 and the NMOS transistor 56 may turn off. It is turned on to output a low level (ie, logic '0') as an output signal.

The NOR gate 16 has the PMOS transistor 66 and the PMOS transistor 64 turned off and the NMOS transistor 60 and the NMOS transistor 62 turned on to output a low level (ie, logic '0') as an output signal. Output

As the NAND gate 14 and the NOA gate 16 output a low level, the voltage source of the inverter 20 becomes the ground voltage GND, and the PMOS transistor 44 is turned on so that the node N2 is turned on. The threshold voltage VT44 of the PMOS transistor 44 is applied thereto. At this time, since the first input signal Ai is at a high level, the NMOS transistor 24 is turned on so that the node N2 is at a completely low level which is an output of the drain of the NMOS transistor 56.

In this case, the voltage level transmitted to the node N2 is transmitted not the voltage level of the drain of the NMOS transistor 54 which is the voltage level of the output terminal of the NAND gate, but the voltage level of the drain of the NMOS transistor 56 is transmitted. VSS) is transmitted through only one NMOS transistor 56 without passing through two transistors of the NMOS transistor 54 and the NMOS transistor 56, resulting in an effect of improving the speed of the full adder.

The sum signal Si and the carry output signal Ci are all brought high by the inverters 34, 36.

FIG. 5A is a diagram illustrating a simulation result of a delay rate between the conventional full adder of FIG. 2 and the full adder of the present invention of FIG. 4, and FIG. 5B is a full adder of the present invention of FIG. 5C is a view showing a comparison result of a product of a delay rate versus power consumption of the conventional full adder of FIG. 2 and the full adder of the present invention of FIG. 4.

The simulation conditions were the same as the size of the transistor with respect to the inverter, measured by varying the load capacitance (load cap) at the output terminal of Sum and Cout.

As can be seen in Figure 5a, the full adder (NNBL_FA (invention)) according to an embodiment of the present invention exhibits a delay rate of about 5% compared to the conventional full adder (NNBL_FA (conventional)).

In addition, referring to Figure 5b, the power consumption simulation results (L13HS, Typical) for the two full adders, the full adder (NNBL_FA (invention)) according to the embodiment of the present invention is a conventional full adder (NNBL_FA (conventional)) Compared with the above, it shows about 10% improvement in power consumption.

In addition, as shown in FIG. 5C, even when comparing the product of delay speed versus power consumption, the full adder (NNBL_FA (invention)) according to the embodiment of the present invention is compared with the conventional full adder (NNBL_FA (conventional)). About 13% improved results.

In the above, the configuration and operation of the circuit according to the present invention has been shown in accordance with the above description and drawings, but this is only an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

According to the present invention as described above, according to the present invention, by reducing the number of transistors that pass when the power supply voltage or ground voltage is transmitted, there is an effect of improving the speed of the full adder.

Claims (7)

A full adder circuit for receiving a first input signal, a second input signal, and an input carry signal, and outputting a sum signal and an output carry signal, A NAND gate configured to receive the first input signal and the second input signal and perform a NAND operation; The NAND gate is A first PMOS transistor 50 receiving the first input signal as a gate voltage and a second PMOS transistor 52 receiving the second input signal as a gate voltage are connected in parallel between a power supply voltage and an output terminal of the NAND gate. Become, A first NMOS transistor 54 having the first input signal as a gate voltage and a second NMOS transistor 56 having the second input signal as a gate voltage are connected in series between an output terminal of the NAND gate and a ground; And a NOR gate receiving the first input signal and the second input signal and performing a NOR operation; The noah gate, A third PMOS transistor 66 having the first input signal as a gate voltage and a fourth PMOS transistor 64 having the second input signal as a gate voltage are connected in series between a power supply voltage and an output terminal of the NOR gate; A third NMOS transistor 60 having the first input signal as a gate voltage and a fourth NMOS transistor 62 having the second input signal as a gate voltage are connected in parallel between an output terminal of the NOR gate and a ground; A first inverter (18) using the output signal of the NOR gate as a first voltage source and inverting the output signal of the NAND gate; A second inverter (20) which uses the output signal of the NAND gate as a second voltage source and inverts the output signal of the NOR gate; A fifth PMOS transistor having a gate controlled by the second input signal and switching a drain of the third PMOS transistor 66 and an output terminal of the first inverter 18; A fifth NMOS transistor having a gate controlled by the first input signal and switching a source of the first NMOS transistor 66 and an output terminal of the second inverter 20; And In response to the input carry signal, one of an output of the first inverter 18 and an output of the second inverter 20 is selected and inverted, respectively, and output as a sum signal. And an output means for selecting one of the outputs, inverting the outputs, and outputting the output carry signal. The method of claim 1, And the first input signal and the second input signal are bit unit data which are not inverted, respectively. The method of claim 1, The first inverter 18, A sixth PMOS transistor having an output of the NAND gate as a gate control voltage, and a source connected to a power supply voltage; And a sixth NMOS transistor having an output of the NAND gate as a gate voltage, connected to a drain of the sixth PMOS transistor, and having a NOR gate output connected to a source. The method of claim 1, The second inverter 20, A seventh PMOS transistor having an output of the NOR gate as a gate voltage, and an output of the NAND gate connected to a source; And a seventh NMOS transistor having an output of the NOR gate as a gate voltage, connected to a drain of the seventh PMOS transistor, and having a source connected to ground. The method of claim 1, The output means, A first pass gate configured to output one of an output of the first inverter 18 and an output of the second inverter 20 as a sum signal in response to the input carry signal; And a second pass gate configured to output one of an output of the NAND gate and an output of the NOR gate as an output carry signal in response to the input carry signal. The method of claim 5, wherein If the input carry signal is a logic level '0', The first pass gate selects and inverts the output of the first inverter 18 and outputs the sum signal. And the second pass gate selects and inverts an output of the NAND gate to generate an output carry signal. The method of claim 5, wherein If the input carry signal is a logic level '1', The first pass gate selects and inverts the output of the second inverter 20 and outputs the sum signal. And the second pass gate selects and inverts an output of the noah gate to generate an output carry signal.

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