KR100407984B1 - Multiplexer_ - Google Patents

Abstract

The present invention relates to a multiplexer which prevents glitch from occurring in an output signal and improves the density by reducing the number of transistors. The present invention relates to a multiplexer configured in series between a power supply terminal and a ground terminal and common to each gate terminal. A first PMOS transistor and a first NMOS transistor to which the first input signal is applied are arranged in series between a source terminal of the first PMOS transistor and a source terminal of the first NMOS transistor, and a data select signal is common to each gate. Commonly connected to the applied second PMOS transistor and the second NMOS transistor, the drain terminal of the first PMOS transistor and the drain terminal of the first NMOS transistor, and are configured in series between the power supply terminal and the ground terminal and common to each gate terminal. A third PMOS transistor and a third NMOS transistor to which a second input signal is applied; A fourth PMOS transistor and a fourth NMOS transistor configured in series between the source terminal of the PMOS transistor and the source terminal of the third NMOS transistor, and to which an inverted signal of the data select signal is applied to each gate terminal; And a latch circuit connected to an output terminal of the second NMOS transistor, the fourth PMOS transistor, and the fourth NMOS transistor to output an output signal.

Description

Multiplexer

TECHNICAL FIELD The present invention relates to a multiplexer. In particular, the present invention relates to a multiplexer suitable for improving circuit performance and increasing integration by reducing the number of transistors used at the same time as well as eliminating the glitch output and reducing the intrinsic delay. It is about.

In general, a multiplexer is a combination circuit that selects binary information from one of many input lines and connects it to a single output line.

The selection of a particular input line is controlled by a set of selection variables. There are usually 2 ⁿ input lines and n selection variables, and the input is selected by a bit combination of the combination of these selection variables.

Hereinafter, a conventional multiplexer will be described with reference to the accompanying drawings.

1 is a circuit diagram illustrating a conventional multiplexer.

As illustrated in FIG. 1, a first AND gate 11 for receiving a first input signal A and a data select signal Sel as inputs, and performing a logical operation to output the same, and the data select signal. A first inverter 12 that inverts and outputs Sel, and a second AND gate 13 that receives logic outputs of the second input signal B and the output signals of the first inverter 12 as inputs, and outputs a logic operation. And an NOR gate 14 that receives the output signals of the first and second AND gates 11 and 13 as inputs, and outputs a logical operation by outputting the signals output from the NOR gate 14. It is comprised including the 2nd inverter 15 which outputs (Z).

Referring to the operation of the conventional multiplexer configured as described above are as follows.

2 is an operation timing diagram illustrating an operation of a conventional multiplexer.

As shown in FIG. 2, when the data select signal Sel transitions from "High" to "Low" when the first input signal A and the second input signal B are "High", the first inverter in the circuit structure. Until the output of (12) becomes "High", there is a period in which Sel and / Sel have the same value "Low" by the delay.

During this period, regardless of the first input signal A and the second input signal B, the output signal Z is forced to “Low” by the delay of the first inverter 12, thereby causing glitches. Occurs.

However, the above conventional multiplexer has the following problems.

That is, grizziness occurs in the output signal due to the circuit structure, which affects other circuits connected thereto, causing a malfunction.

An object of the present invention is to provide a multiplexer designed to solve the above problems, to prevent bleeding from occurring in an output signal, and to improve the degree of integration by reducing the number of transistors.

1 is a circuit diagram showing a conventional multiplexer

2 is an operation timing diagram illustrating an operation of a conventional multiplexer.

3 is a circuit diagram illustrating a multiplexer according to the present invention.

4 is an operation timing diagram for explaining the operation of the multiplexer according to the present invention.

Explanation of symbols for main parts of the drawings

21,23,25,27: PMOS transistors 22,24,26,28: NMOS transistors

29 latch circuit 30 inverter

In order to achieve the above object, a multiplexer according to the present invention comprises a first PMOS transistor and a first NMOS transistor configured in series between a power supply terminal and a ground terminal, and to which a first input signal is applied to each gate terminal, A second PMOS transistor and a second NMOS transistor configured in series between a source terminal of the first PMOS transistor and a source terminal of the first NMOS transistor, and to which a data select signal is applied to each gate in common; and a drain terminal of the first PMOS transistor And a third PMOS transistor and a third NMOS transistor which are commonly connected to the drain terminal of the first NMOS transistor, are configured in series between a power supply terminal and a ground terminal, and have a second input signal applied to each gate terminal in common. In series between the source terminal of the PMOS transistor and the source terminal of the third NMOS transistor And a fourth PMOS transistor and a fourth NMOS transistor to which an inverted signal of the data select signal is applied to each gate terminal, and connected to an output terminal of the second PMOS transistor, the second NMOS transistor, the fourth PMOS transistor, and the fourth NMOS transistor. And a latch circuit for outputting an output signal.

Hereinafter, a multiplexer according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram illustrating a multiplexer according to the present invention.

As shown in FIG. 3, a first PMOS transistor 21 and a first NMOS configured in series between a power supply terminal Vdd and a ground terminal Vss and to which a first input signal A is applied in common to each gate terminal. A second configured in series between the transistor 22 and the source terminal of the first PMOS transistor 21 and the source terminal of the first NMOS transistor 22 and having a data select signal Sel applied to each gate in common; The PMOS transistor 23 and the second NMOS transistor 24, the drain terminal of the first PMOS transistor 21 and the drain terminal of the first NMOS transistor 22 are commonly connected, and the power supply terminal Vdd and the ground terminal are commonly connected. A third PMOS transistor 25 and a third NMOS transistor 26 configured in series between (Vss) and to which a second input signal B is applied to each gate terminal in common, and the third PMOS transistor 25. Between the source terminal of and the source terminal of the third NMOS transistor 26 A fourth PMOS transistor 27 and a fourth NMOS transistor 28 configured in series and to which an inverted signal / Sel of the data select signal is applied to each gate terminal; the second PMOS transistor 23 and the second; And a latch circuit 29 connected to an output terminal of the NMOS transistor 24 and the fourth PMOS transistor 27 and the fourth NMOS transistor 28 to output the output signal Z.

In this instance, the data select signal Sel is inverted by the inverter 30, and the latch circuit 29 is configured in series so that two inverters are fed back.

Referring to the operation of the multiplexer according to the present invention configured as described above are as follows.

4 is an operation timing diagram for explaining the operation of the multiplexer according to the present invention.

As shown in FIG. 4, when the data select signal Sel transitions to “Low” when the first input signal A and the second input signal B are in the mode “High,” the output node of the inverter 30 ( Node) / Sel transitions from "Low" to "High" after a time delay of the inverter 30.

Sel and / Sel have a "Low" value from the time when the data select signal Sel transitions from "High" to "Low" until the / Sel becomes "Low" to "High" after a time delay.

On the other hand, when Sel and / Sel are "Low" at the same time, the first PMOS transistor 21, the third PMOS transistor 25, the second NMOS transistor 24, and the fourth NMOS transistor 28 are off. The second PMOS transistor 23, the fourth PMOS transistor 27, the first NMOS transistor 22, and the third NMOS transistor 26 are turned on.

Therefore, the node ZN maintains the Z-state without forming a path to either the power supply terminal Vdd or the ground terminal Vss, and the output signal Z is a latch circuit. By (29), the previous value "High" is kept as it is.

As described above, the multiplexer according to the present invention has the following effects.

First, since the grit is not generated even when the data select signal changes, it can be usefully used not only as a data selector but also as a clock selector, and can improve operation speed.

Second, by using fewer transistors, the integration density can be improved by minimizing the layout area.

Claims (2)

A first PMOS transistor and a first NMOS transistor configured in series between a power supply terminal and a ground terminal, and having a first input signal applied to each gate terminal in common; A second PMOS transistor and a second NMOS transistor configured in series between a source terminal of the first PMOS transistor and a source terminal of the first NMOS transistor, and to which a data select signal is applied in common to each gate; A third PMOS transistor commonly connected to the drain terminal of the first PMOS transistor and the drain terminal of the first NMOS transistor, configured in series between a power supply terminal and a ground terminal, and having a second input signal applied to each gate terminal in common; With 3 NMOS transistors, A fourth PMOS transistor and a fourth NMOS transistor configured in series between a source terminal of the third PMOS transistor and a source terminal of the third NMOS transistor and to which an inverted signal of the data select signal is applied to each gate terminal; And a latch circuit connected to an output terminal of the second PMOS transistor, the second NMOS transistor, the fourth PMOS transistor, and the fourth NMOS transistor to output an output signal. 2. The multiplexer of claim 1 wherein the latch circuit is configured in series such that two inverters are fed back.