JP3513158B2 - Semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device including a flip-flop circuit, and a semiconductor integrated circuit whose logical operation timing is controlled by clock synchronous operation with respect to a flip-flop circuit arranged in an information transmission path. The present invention relates to a device, for example, a technique effectively applied to a logic LSI such as a microprocessor or a microcomputer.

[0002]

2. Description of the Related Art In a logic LSI such as a microprocessor, a register is arranged in an information transmission path between logic circuits such as an arithmetic logic operation circuit, a multiplexer, a shifter, a decoder, and a selector included in an execution section of each register. Are synchronized with a clock signal to easily prevent malfunction and perform data processing.
As such a register, generally, a plurality of static flip-flop circuits capable of stably holding data regardless of the influence of a clock signal cycle, coupling noise, minute leak current, alpha ray, etc. are generally used. Has been adopted.

The performance of such a logic LSI is determined by a clock signal cycle which defines the operation of a plurality of static flip-flop circuits arranged in an information transmission path. That is, when data is output from a register, that is, a plurality of static flip-flop circuits in synchronization with a change in a clock signal, various logical operations are performed on the data, and the operation result is stored in the register of the next stage. The cycle of the clock signal is determined so that the register of the next stage can input data in synchronization with the arrival timing in synchronization with the change of the clock signal.

Examples of documents describing such a microprocessor are "Nikkei Electronics (July 13, 1987)", pages 124 to 138, published by Nikkei McGraw-Hill.

[0005]

However, in the conventional logic LSI of this type, a plurality of static flip-flop circuits constituting a register are changed in the clock signal and then the data held therein is output. Until the data writing is started in synchronism with the change of the clock signal, the delay time is up to several times longer than that of general gates such as NAND gates and NOR gates. It has been clarified by the present inventor that there is a possibility that it may be an obstacle to speeding up. This is because in a static flip-flop circuit as a sequential circuit, a data system logic gate for statically latching data between its data input terminal and its data output terminal and the data system logic gate are synchronized with a clock signal. This is because the number of gate serial stages existing between the data input terminal and the data output terminal increases because it includes a clock logic gate for operating the same.

The flip-flop circuit to which attention is paid here is positioned as a synchronous sequential circuit, and in particular, the inventor of the present invention has found that the flip-flop circuit, which is a unit cell or a standard cell of automatic placement and wiring such as design automation, Specifically, the level sense flip-flop shown in FIG. 13 was examined.

In the figure, G101 to G103 and G
106 to G108 are inverter gates, G104 and G105 are NAND gates, and T101 and T102 are transfer gates. The NAND gate G10
4, G105 constitutes a static latch by being feedback-connected via the transfer gate T101. The flip-flop circuit shown in the figure is used as a standard cell, and the driving capacity and the capacitive load of the circuit connected to its input / output terminal are different for each semiconductor integrated circuit device in which this flip-flop is actually used. It varies, and in consideration of this, the inverter gates G101, G
103, G106, and G107 are provided. That is, the inverter gate G101 performs waveform shaping so that the setup time and hold time that define the data write timing and the minimum pulse width of the clock are not affected by the slope of the change in the input waveform of the clock signal CLK. The inverter gate G103 has an amplifying function to prevent the writing time from being influenced by the driving capability of the data D input front stage circuit. The inverter gates G106 and G107 prevent the data output operation from being affected by the output side load capacitance. Further, the inverter gate G10 is configured to give priority to the set and reset operations with respect to the writing and reading of the input data D that is taken in by the level change of the clock signal CLK.
6, the inputs of G107 are connected to the output side of the NAND gate G105, and are not connected to the input side of the NAND gate G104.

Therefore, in this flip-flop circuit, six stages of gates G101, T102, G104, and G10 are provided after the clock signal CLK is changed to the high level and before the inverted output Q * (* means negative logic) is obtained.
5, it is necessary to wait for the outputs of G106 and G108 to be determined, and in order to obtain the non-inverted output (normal output) Q, the gates G101, T102, G104 and G10 of five stages are provided.
5, it is necessary to wait until the output of G107 is fixed. As a result, the delay from the change of the clock signal CLK to the high level until the data output is determined becomes large.

FIG. 14 shows another flip-flop circuit examined by the present inventor. The flip-flop circuit shown in the figure has two OR-and-
A static latch is formed by the inverter gates G113 and G114, a waveform shaping inverter gate G111 is arranged at the input stage of the clock signal CLK, and an inverter for preventing the write operation from being influenced by the output side load capacitance at the output side. Gate G115, G116
And an inverter gate G112 for inverting the input data D is provided. This flip-flop circuit also has four stages of gates G111, G113, G114, G116 or G111, G113, G114, until the inverted output Q * and the non-inverted output Q are obtained after the clock signal CLK is changed to the high level. Since it is necessary to wait for the output of G115 to be determined, similarly to the above, a large delay occurs from the change of the clock signal CLK to the high level until the data output is determined.

As described above, in the conventional clock-synchronous flip-flop circuit, a relatively large delay occurs from the level change of the clock signal until the data output is determined.
The clock signal period is inevitably long in order to secure the required time for the data setup time and hall time for the clock signal. As a result, there is a limit to the speedup of the logic LSI whose operation speed is determined by the cycle of the clock signal that defines the operation of the flip-flop circuit. For example, when such a flip-flop circuit exists in the critical path, the operation delay time of the flip-flop circuit is logic L.
This will prevent an increase in SI speed.

Especially, only in terms of speeding up, ECL
Although a circuit can be adopted, it is not necessarily a good idea because it is difficult to achieve high integration and the power consumption is remarkably large as compared with the MOS type semiconductor integrated circuit device.

An object of the present invention is to reduce the operation delay of a clock synchronous flip-flop circuit and speed up the logical operation of a semiconductor integrated circuit device.

Another object of the present invention is to realize high integration and low power consumption in a semiconductor integrated circuit device whose performance is determined by a clock signal cycle that defines the operation of a flip-flop circuit, while realizing high integration and low power consumption. It is an object of the present invention to provide a semiconductor integrated circuit device capable of performing a logical operation at high speed in terms of the performance of a switching circuit.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0015]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, in the semiconductor integrated circuit device whose logical operation timing is controlled by the clock synchronous operation with respect to the flip-flop circuit arranged in the information transmission path, the operation included in the area below the curve (a) in FIG. It employs a flip-flop circuit having characteristics.

Further, in the semiconductor integrated circuit device whose logical operation timing is controlled by the clock synchronous operation with respect to the flip-flop circuit arranged in the information transmission path, the flip-flop circuit has its data input terminal and output terminal. In between, a storage circuit and a bypass circuit having a smaller number of serial gate stages than the storage circuit are connected in parallel.

Alternatively, by a clock synchronous operation with respect to the flip-flop circuit arranged in the information transmission path,
In the semiconductor integrated circuit device whose logical operation timing is controlled, as the flip-flop circuit, a memory circuit and a bypass circuit are connected in parallel between the data input terminal and the output terminal of the flip-flop circuit to reach the output terminal from the data input terminal. With respect to the data propagation delay time up to, the bypass circuit is smaller than the storage circuit.

The bypass circuit bypasses the logic of the memory circuit and bypasses the information to be written in the memory circuit and transmits it to the output terminal. In order to prevent the conflict between the holding information before the output of the storage circuit is confirmed and the output information of the bypass circuit, the bypass circuit is brought into conduction with the data output terminal during the data writing operation of the storage circuit,
It is preferable that the flip-flop circuit includes switching means for bringing the bypass circuit into a non-conductive state with the data output terminal when the memory circuit is in a data holding state.

The switching means has a switch circuit, a logic gate, and a clock whose conduction / non-conduction state is controlled to be switched based on a clock signal which is substantially the same as a clock signal which controls the write operation of the memory circuit. It is possible to employ one or more means selected from among the gates.

Further, in the semiconductor integrated circuit device whose logical operation timing is controlled by the clock synchronous operation for the flip-flop circuit arranged in the information transmission path, the flip-flop circuit has its data input terminal and output terminal. The storage circuit and the bypass circuit are connected in parallel between the two, and the output of the bypass circuit is transmitted to the output terminal during the data writing operation of the storage circuit, and the output of the storage circuit is transmitted to the output terminal in the data holding state of the storage circuit. You may employ | adopt the structure containing a means.

In order to stabilize the operation or unify the operation specifications regardless of the circuit configuration to which the flip-flop circuit is applied, the setup time and hold time for writing information in the memory circuit are set to the data output terminal. A driver circuit for driving the load to be coupled to the output terminal may be provided in order not to largely depend on the magnitude of the capacitive load coupled to the.

In order to correspond to the structure having the normal output and the inverted output, the bypass circuit for the normal output and the bypass circuit for the inverted output can be separately included.

In order to stabilize information storage that is not affected by coupling noise, minute leak current, etc.,
It is advisable to employ a memory circuit of a type that statically holds information.

When the memory circuit has a set / reset function, in order to give priority to the set / reset operation in the entire flip-flop circuit regardless of the state of the clock signal, the bypass circuit should also have the set / reset function. It is desirable to have it. That is, the bypass circuit forces the data output to the output terminal to a first value in response to the first signal and outputs the data output to the output terminal in response to the second signal to the first value. A means for forcing a value of 2 is provided.

When the flip-flop circuit includes two memory circuits of a master stage and a slave stage, which are connected in series,
It is desirable to connect a bypass circuit in parallel to at least the slave stage.

In terms of high integration and low power consumption, it is preferable that the semiconductor integrated circuit device including the flip-flop circuit is constructed in a complementary MOS circuit form. Further, in terms of improving the driving capability of the flip-flop circuit, the flip-flop circuit is a BI-CMO including a bipolar transistor and a MOS transistor.
It can also be configured with an S circuit.

[0028]

According to the above-mentioned means, when the storage circuit fetches and holds the input data in synchronization with the change of the clock signal, the bypass circuit connected in parallel to the storage circuit is in parallel with the input data. The information corresponding to is output.
The bypass circuit does not involve a storage operation, has a smaller number of stages of serially connected built-in gates than the storage circuit, or has an information transfer delay from an input terminal to an output terminal smaller than that of the storage circuit. Before the write operation of the input data is completed, the bypass circuit outputs the information corresponding to the input data at high speed. In this way, the timing from the input of the input data to the input terminal of the flip-flop in synchronization with the change of the clock signal to the output of the data corresponding to the input data to the output terminal of the flip-flop is accelerated. This reduces the operation delay of the clock synchronous flip-flop circuit.
Therefore, in a semiconductor integrated circuit device such as a microprocessor or a microcomputer, the performance of which is determined by a clock signal cycle for defining the operation of the flip-flop circuit, the clock signal cycle can be speeded up. The logical operation of the device can be speeded up.

Then, such a semiconductor integrated circuit device is provided with a MOS.
Type semiconductor integrated circuit device, due to the miniaturization of elements and the accompanying reduction of the power supply voltage, the flip-flop circuit as well as the LSI according to the scaling rule.
The overall operation of the flip-flop circuit is further accelerated, and a higher-speed logic operation is achieved in terms of the performance of the flip-flop circuit without sacrificing high integration and low power consumption.

[0030]

FIG. 2 is a chip layout diagram of a microcomputer or microprocessor according to an embodiment of the present invention.

In the figure, 1 is one semiconductor substrate such as silicon. For example, a large number of bonding pads 2 are arranged on the outer edge of the semiconductor substrate 1, and an input buffer, an output buffer, and an input / output buffer forming region 3 are formed. Inside the formation area 3, an instruction queue 4 that prefetches instructions, an instruction register 5 that receives instructions from the instruction queue 4 in a predetermined procedure, and an instruction that decodes the instructions held by the instruction register 5 and generates various control signals. An instruction control unit including the decoder 6 and the like is configured. Further, arithmetic logic unit 7, multiplier array 8, barrel shifter 9, arithmetic register, and other arithmetic means, and a floating point controller 11 and a multiplier controller 12 for controlling the arithmetic means are provided. In addition, a register file 13, a data cache memory 14, an address register 15, an address conversion buffer 16 and a clock generator 17 are provided. In the microprocessor 1, the instruction fetched in the instruction register 5 is decoded by the instruction decoder 6 so that data and addresses are calculated through various arithmetic units and registers to execute the instruction.

FIG. 3 shows an example of an information transmission path for indicating the performance of the microprocessor 1 shown in FIG. 2, for example, a critical path. The critical path shown in the figure is a path when an instruction address is generated by a jump instruction, although not particularly limited. The instruction register 5, the arithmetic register 10, and the address register 15 write and hold data in synchronization with a change in the clock signal CLK, for example. Instruction register 5 is clock signal CLK
The instruction is input and held and output in synchronization with the change of.
The output instruction is decoded by the instruction decoder 6 and supplied to the arithmetic and logic operation unit 7 through the selector 20, and the operation result there is transmitted to the operation register 10. In order to prevent the operation result from being normally transmitted to the subsequent stage and causing a malfunction, the operation register 10 is supplied with the clock signal CLK.
Of the cycle time Tc before the next change of
The calculation result data must reach the input of the calculation register 10 within yc. Similarly, the information output from the operation register 10 by the barrel shifter 9 and transmitted to the address register 15 via the selector 21 must reach the input of the address register 15 within the cycle time Tcyc. I have to. The instruction register 5, the arithmetic register 10, the address register 15 and the like are composed of flip-flop circuits of the number corresponding to the number of bits constituting the instruction register 6, the instruction decoder 6 and the arithmetic logic operation unit 7 are composed of a NAND gate, a NOR gate, an inverter gate and the like. It As represented by the critical path of FIG. 3, in the microprocessor 1 of the present embodiment in which the logical operation timing is controlled by the clock synchronous operation with respect to the flip-flop circuit arranged in the information transmission path, the data processing is performed. It is necessary to shorten the cycle time Tcyc in order to increase the operation speed of the flip-flop circuit. Therefore, the operation delay time of the combinational circuit such as the NAND gate is reduced, and at the same time, the normal time after the clock signal CLK changes in the flip-flop circuit. It is necessary to minimize the delay time until the data is output.

FIG. 1 shows an example of a flip-flop circuit for forming the various registers. The flip-flop circuit 30 shown in the figure is of a level sense type which inputs data in accordance with the level of the clock signal CLK, and includes a clock input terminal 31, a data input terminal 32,
It has a data non-inversion output terminal 33, a data inversion output terminal 34, a set terminal 35, and a reset terminal 36, and a storage circuit 40, a non-inversion output bypass circuit 41, and a data input terminal and an output terminal. Bypass circuit 42 for inverting output
Are connected in parallel, and they have a common clock signal CLK,
It is controlled by the set signal S * and the reset signal R *. Vcc in the figure is a power supply voltage such as 2 V, and G
ND is set to a ground voltage such as 0 volt.

The normal output bypass circuit 41 includes an inverter gate G2 and two p-channel MOS transistors.
Alternatively, a MIS field effect transistor (hereinafter simply referred to as MO
Also referred to as S-transistor) MP1, MP2 and two n
A clocked inverter gate G20 composed of channel type MOS transistors MN1 and MN2;
It includes a transmission path of input data D formed by a complementary MOS transfer gate (hereinafter also simply referred to as a transfer gate) T1.

The inverting output bypass circuit 42 has two
P channel type MOS transistors MP4, MP
Five and two n-channel type MOS transistors MN
4, a clocked inverter gate G21 constituted by MN5 and a transmission path of input data D constituted by a transfer gate T2.

The memory circuit 40 has a static latch composed of a transfer gate T3 and two NAND gates G8 and G9, and an inverter gate G7,
The transfer gate T4, the NAND gates G8 and G9, the transfer gate T3, the inverter gate G10, and the transfer gate T5 constitute a transmission path for normal data output, and the inverter gate G7, the transfer gate T4, the NAND gates G8 and G9, and the transfer gate. The gate T3, the inverter gate G11, and the transfer gate T6 form a data inversion output transmission path.

The set / reset function in the flip-flop circuit 30 has a storage circuit 40 and a bypass circuit 41,
42 of each set signal S in the memory circuit 40.
The NAND gate G8 which receives * controls the set function, and the NAND gate G9 which receives the reset signal R * controls the reset function. In the non-inverting output bypass circuit 41, the clocked inverter gate G20 and the p-channel type MOS transistor MP3 and the n-channel type MOS transistor MN3 control the set / reset function. In the bypass circuit 42 for inverting output,
The clocked inverter gate G21, p-channel type MOS transistor MP6 and n-channel type M
The OS transistor MN6 controls the set / reset function.

The normal output of the storage circuit 40 and the output of the bypass circuit 41 are wired or connected by a node N1, and which output is selected is selected by transfer gates T1 and T5 which are complementarily switch-controlled. It In addition, the inverted output of the storage circuit 40 and the bypass circuit 4
The two outputs are wired-OR connected by the node N2, and which output is selected is selected by the transfer gates T2 and T6 which are complementarily switch-controlled. Inverter gates G4, G5, G6 of three stages in series for transmitting a clock signal CLK for switching control of the transfer gates T1, T2, T5, T6 etc. are arranged.

When the clock signal CLK is set to the high level, the transfer gates T1 and T2 are turned on, and the outputs of the bypass circuits 41 and 42 are the normal output terminal 33.
And the inverting output terminal 34 are brought into conduction, and the output of the memory circuit 40 is brought out of conduction with the output terminals 33 and 34.
Therefore, at this time, the data D from the data input terminal 32
Is supplied, the normal output Q is supplied to the output terminal 33 through the bypass circuit 41, and the inverted output Q * is supplied to the output terminal 34 through the bypass circuit 42.

When the clock signal CLK is at the high level, the memory circuit 40 is put in the write state, and the bypass circuit 41,
The input data D is written in parallel with the output operation by 42. That is, the transfer gate T3, which constitutes a static latch together with the NAND gates G8 and G9, is turned off, and the transfer gate T4 that takes in the input data D via the inverter gate G7 is turned on and put in a write state.

In this written state, the set signal S
When * is set to a low level and a set operation is instructed, in the non-inverting output bypass circuit 41, the MOS transistor MN2 is inverted to the off state, and the MOS transistor MP3 is turned on. The normal output Q is fixed to the high level regardless of the D level. In the inverting output bypass circuit 42, the MO
When the S transistor MN6 is turned on,
The MOS transistor MP4 is turned off, whereby the inverting output Q * is fixed to the low level regardless of the level of the input data D. At this time, the memory circuit 40 is set to the set state regardless of the logical value of the input data D by the operation of the NAND gate G8 which receives the low level set signal S *. Thus, when the set operation is instructed during the write operation, the set operation has priority over the control by the clock signal CLK. That is, the normal output Q and the inverted output Q * are forced to the output level in the set state regardless of the logical value of the data D taken in in synchronization with the change of the clock signal CLK. The same applies when the reset signal R * is set to the low level and a reset operation is instructed.

When the clock signal CLK is set to the low level, the transfer gates T1 and T2 are turned off, the transfer gates T5 and T6 are turned on, and the outputs of the bypass circuits 41 and 42 are forward output. Terminal 3
3 and the inverting output terminal 34 are made non-conductive, and the output of the storage circuit 40 becomes the output of the flip-flop circuit 30. At this time, the transfer gate T4 of the memory circuit 40
Is turned off and the transfer gate T3 is turned on, so that the written data is statically latched. Therefore, the data written in the memory circuit 40 during the high level period of the clock signal CLK is stably output without being undesirably level-reversed due to the influence of the capacitive coupling, the minute leak current, and the alpha ray. It is output from the terminals 33 and 34. Further, by the action of the inverter gates G10 and G11 arranged in front of the transfer gates T5 and T6, data can be output without being affected by the output load capacitance.

At this time, when the set signal S * is set to the low level and the set operation is instructed, the memory circuit 40 is concerned with the logical value of the input data D by the operation of the NAND gate G8 which receives the set signal S * of the low level. Without being set, the normal output Q obtained at the output terminal 33 is high level,
The inverted output Q * obtained at the output terminal 34 is fixed at a low level. Once the set operation is instructed and the state is stored in the storage circuit 40, the set state is stably maintained even if the set signal S * is negated to the high level. The same applies when the reset signal R * is set to the low level and the reset operation is instructed.

In the inverter gate G4 and the like arranged in the input stage of the clock signal CLK, the setup time and the hold time for defining the data write operation and the minimum clock pulse width depend on the slope of the change of the input waveform of the clock signal CLK. Performs waveform shaping to prevent it from being affected.

In this flip-flop circuit 30,
The number of gate stages through which the data must pass after the clock signal CLK is changed to the high level until the data is output is minimized by only one stage of the transfer gates T1 and T2 in the bypass circuits 41 and 42, respectively. Therefore, as compared with the circuits shown in FIGS. 13 and 14, the delay time from the change timing of the clock signal to the output of the normal data is extremely short. Moreover, since the flip-flop circuit 30 is assured of the stability of the write operation and the stability of the data output performance in the memory circuit 40 as in the conventional case, it is a unit cell or a standard cell of automatic placement and routing such as design automation. As a mode of use, that is, a mode of use in which it is assumed that the driving capacity and the capacitive load of the circuit connected to the input / output terminal are different for each semiconductor integrated circuit device in which this flip-flop is actually used. It is also perfect for

Regarding the size of the MOS transistors forming the flip-flop circuit 30, the MOS transistors MP2, MN1, MP5, MN4, the MOS transistors forming the transfer gates T1 and T2, and the MOS forming the inverter gate G4. If the gate width of the transistor is standard, the gate width of the inverter gates G2 and G7 composing MOS transistors that receive the input data D is about half of the standard, which reduces the input capacitance and accelerates the transient response speed of the input data. It is like this. Also, the MOS transistor MP
The MOS transistors forming the transistors MN3, MP3, MP6, and MN6 and the transfer gates T5 and T6 have parasitic capacitances of diodes at their output nodes. Therefore, the gate widths of these MOS transistors are about half of the standard. Further, since high speed is not required for the set / reset operation used at the time of system reset or diagnosis, the MOS transistors MP1, MN2, MP4, M
The gate input capacitance of N5 may be increased.
Therefore, in order to increase the driving capability of the bypass circuits 41 and 42, the gate widths of these transistors are set to about 2 to 5 times the standard, and the on-resistance is made extremely small.

FIG. 4 shows the characteristic of the flip-flop circuit shown in FIG. This characteristic shows the load capacitance CL dependence of the delay time Tpd (the average of the normal output Q and the inverted output Q *) from the time when the clock signal CLK is changed with the data applied to the input terminal until the data is output. The characteristic curve (a) relates to the flip-flop circuit 30 shown in FIG. 1, the characteristic curve (b) relates to the flip-flop circuit shown in FIG. 13, and the characteristic curve (c) relates to the flip-flop circuit shown in FIG.

Load capacity 0.3 in characteristic curve (a)
The characteristics at [PF] were acquired, for example, under the following simulation conditions. That is, this flip-flop circuit is configured by a complementary MOS circuit adopting the 0.2 [μm] process, and the power supply voltage is assumed to be 2.0 [V]. The standard size of the MOS transistor is 0.20 [μm] and the gate width is 15 [μm], and the input capacitance of the standard-sized complementary MOS inverter gate is 0.05 [PF]. However, MOS transistor M
The gate width of P1, MP4, MN1, and MN4 is 45 [μ
m], inverter gates G2, G3, G5 to G11 and transfer gates T3 to T6, and MOS transistors MP3, MN3, MP6.
The gate width of MN6 is 7.5 [μm]. The load capacity 0.3 [PF] is not particularly limited, but the length 1
Assuming the sum of parasitic capacitance (0.18 [PF]) of aluminum wiring of [mm] and width 0.7 [μm] and gate input capacitance (0.1 [PF]) corresponding to fan out = 2. The standard load capacity is

As representatively shown by the characteristic curve (a), when the microprocessor 1 of the present embodiment is constituted by a MOS type semiconductor integrated circuit device, the miniaturization of the elements and the accompanying reduction of the power supply voltage are caused. Due to the promotion, not only the flip-flop circuit but also the whole circuit operation is accelerated in accordance with the scaling rule, and it becomes comparable to the current ECL circuit, and further, high integration and low power consumption which cannot be realized by the ECL circuit. Of the flip-flop circuits, which enables higher-speed logic operation.

FIG. 5 shows an example of a master / slave type flip-flop circuit in consideration of racing prevention. In the figure, Vcc is set to 2V and GND is set to 0V.

Flip-flop circuit 50 shown in FIG.
Is a master stage 51 and a slave stage 52 connected in series between the data input terminal 32 and the output terminals 33 and 34.
2 storage circuits, and the slave stage 52 has a normal output bypass circuit 41 and an inverted output bypass circuit 42 connected in parallel. The master stage 51 takes in data according to the low level of the clock signal CLK, and the slave stage 52 takes in data from the master stage 51 and outputs it in synchronization with the rising change of the clock signal CLK.

The master stage 51 has an inverter gate G3.
0, two transfer gates T10, T11, two NAND gates G31, G32 are included, and gates G31, G
A feedback loop composed of 32 and T11 constitutes a static latch. The slave stage 52 has four transfer gates T12 to T15 and two NAND gates G.
33, G34, three inverter gates G35 to G37
And a feedback loop constituted by the gates G33, G34 and T13 constitutes a static latch. The bypass circuits 41 and 42 are configured in the same way as in FIG. Also in such a master / slave type flip-flop circuit 50, it is possible to speed up the operation similarly to FIG.

FIG. 6 shows another example of a master / slave type flip-flop circuit to which the present invention is applied. This embodiment is similar to the embodiment shown in FIG.
Therefore, only the differences will be described. In the embodiment of FIG. 6, not the data output of the master stage but the data D from the transfer gate T10 is used as the bypass circuit 4
It is supplied as data D to 1, 42. According to this embodiment, the setup time can be shortened.

FIG. 7 shows another example of a master / slave type flip-flop circuit to which the present invention is applied. Since this embodiment is also similar to the embodiment shown in FIG. 5, only the differences will be mainly described. In the embodiment shown in FIG. 7, the bypass circuits 41 and 42 shown in FIG. 5 are connected to the MOS transistors MN2, MN3, MN5 and MN.
6, MP1, MP3, MP4, MP6 and inverter G
1, G3 are excluded. Therefore, the bypass circuit 4
1, 42 do not have a set / reset function. According to this embodiment, the number of elements can be reduced.

FIG. 8 shows another example of a master / slave type flip-flop circuit to which the present invention is applied. Since this embodiment is also similar to the embodiment shown in FIG. 7, only the differences will be mainly described. In the embodiment shown in FIG. 8, a master stage 53 is further provided, and the data from this master stage 53 is used as the bypass circuits 41 and 4.
2 is being supplied. The master stage 53 has a transfer gate T16 having the same function as the transfer gate T10 and a transfer gate T17 having the same function as the transfer gate T11.
Further, it has a configuration as described below. That is, the feedback loop for forming the static latch includes the inverter G39, the transfer gate T17, the MOS transistors MN10 and MN11, and the MOS transistor M.
And a clocked inverter circuit composed of P10 and MP11. Further, the data D is the MOS transistors MN7 and MN8 and the MOS transistor MP.
It is supplied to the feedback loop through a clocked inverter circuit composed of MP7. The master stage 53
The MOS transistor MN9 to which the set signal S * is supplied via the inverter G40 and the MOS transistor MP9 to which the reset signal R * is supplied to the output node thereof so that it has the set / reset function. The inverted set signal S connected by the inverter G40 is further supplied to the MOS transistor MP8,
The set signal S * supplied to the MP10 is further supplied to the MOS transistors MN8 and MN11. Also in this embodiment, the bypass circuits 41 and 4 are provided.
2 may have the same configuration as that of the embodiment shown in FIG.

FIG. 9 shows another example of a master / slave type flip-flop circuit to which the present invention is applied. In this embodiment, the bypass circuit (2) is connected in parallel to the slave stage and the bypass circuit (1) is connected to the master stage in parallel. The circuits described above can be used for the master stage and the slave stage, respectively. Similarly,
As the bypass circuits (1) and (2), the circuits described above can be used.

FIG. 10 shows an example circuit in which the output stage of the bypass circuit, for example, the bypass circuit for normal output is made into BI-CMOS. The bypass circuit 60 has npn-type bipolar transistors BT1 and BT2 connected in series at the output stage, and has the set / reset MOS transistors MP3 and MN3 connected to the bipolar transistors BT1 and BT.
It is connected in parallel to T2. When the clock signal CLK is at the low level, the transfer gate T1 and the n-channel type MOS transistor MN10 are turned off and the output of the bypass circuit 60 is set to the high impedance state. When the clock signal CLK is at high level, the transfer gate T1 and the MOS transistor MN10 are turned on, so that the bipolar transistors BT1 and BT
2 complementarily switches according to the switch state of the n-channel MOS transistor MN11 to output the input data D in the normal direction. It goes without saying that this circuit configuration can be applied to a bypass circuit for inverting output.

By converting the output stage of the bypass circuit into BI-CMOS, the output operation of the bypass circuit can be speeded up. It is considered that such BI-CMOS technology can be positioned as an alternative means or a transient means until then when the ultra-high speed flip-flop circuit represented by the characteristic curve (a) of FIG. 4 is not used. To be In other words, it is extremely difficult to lower the base-emitter voltage of the transistor due to the nature of using the bipolar transistor due to scaling or miniaturization of the device. Therefore, when the totem-pole type bipolar output stage as shown in FIG. 10 is used, if the base-emitter voltage of each bipolar transistor is 0.7 V, the high level of the output signal is (Vcc-0.7) V. The low level of the output signal is (GND + 0.7) volt. Therefore, when Vcc is set to a value such as 5 volts and GND is set to a value such as 0 volt, a sufficient signal amplitude of the output signal is obtained. However, when Vcc is set to a value such as 2.0 V and GND is set to a value such as 0 V, the amplitude of the output signal sufficient to drive the CMOS circuit of the next stage cannot be obtained. . That is, FIG.
The use of the bypass circuit of 0 is limited by the values of the power supply voltage Vcc and GND. A technique for increasing the output operation of the bypass circuit by using BI-CMOS is M
It is necessary to take into consideration the inconvenience that the power supply voltage may be reduced due to the miniaturization and high integration of elements in the OS semiconductor integrated circuit device. On the other hand, the use of the flip-flop shown in FIGS. 1 and 5 is not limited by the value of the power supply voltage (Vcc, GND).

According to the above embodiment, there are the following effects.

(1) Storage circuit 40 as shown in FIG.
Bypass circuits 41, 42 connected in parallel to the
In the bypass circuits 41 and 42 connected in parallel to the slave stage 52 as a storage circuit as shown in FIG. 8, the data passes after the clock signal CLK is changed to the high level and before the data is output. Since the number of power gate stages is minimized by only one stage of the transfer gates T1 and T2 in the respective bypass circuits 41 and 42, the number of gate stages should be minimized from the timing of changing the clock signal as compared with the circuits shown in FIG. 13 and FIG. The delay time until the regular data is output can be made extremely small.

(2) Due to the above-described effects, the delay time until the normal data is output from the flip-flop circuit in synchronization with the change of the clock signal CLK is shortened as much as possible. Therefore, the register arranged in the information transmission path. In the microprocessor 1 of the present embodiment in which the logic operation timing is controlled by the clock synchronization operation for the configuration flip-flop circuits 30 and 50, the cycle time Tcyc as shown in FIG. 3 can be shortened. As a result, the speed of data processing can be increased.

(3) When the microprocessor 1 of this embodiment is constituted by a MOS type semiconductor integrated circuit device, the characteristic curve of FIG. The flip-flop circuits 30 and 5 have the operation characteristics typically shown in FIG.
0, the entire circuit operation of the microprocessor 1 as well as the flip-flop circuits 30 and 50 is further speeded up to be comparable to the current ECL circuit. It is possible to achieve high integration and low power consumption that cannot be realized with a circuit.

(4) The outputs of the bypass circuits 41 and 42 are transmitted to the output terminals 33 and 34 during the data writing operation of the storage circuits 40 and 52, and the outputs of the storage circuits 40 and 52 are held in the data holding state. Output terminal 3
Since it is transmitted to the memory circuit 3, 34,
Retained information before write operation of 0, 52 and bypass circuit 4
It does not conflict with the output information of 1, 42 at all.

(5) Since the memory circuits 40 and 52 statically latch the written data, the data written in the memory circuit during the high level period of the clock signal CLK is capacitively coupled, a minute leak current, and an alpha. It is possible to stably output from the output terminals 33 and 34 without undesired level inversion under the influence of lines or the like.

(6) Inverter gates G10, G11 or G arranged before the transfer gates T5, T6
By the action of 36 and G37, data can be output without being affected by the output load capacitance.

(7) Since the inverter gate G4 and the like are arranged at the input stage of the clock signal CLK, the setup time and hold time for defining the data write operation and the clock minimum pulse width are the clock signal CLK.
It is possible not to be influenced by the slope of the change of the input waveform.

(8) By virtue of the above operational effects (6) and (7), it is possible to stabilize the operation or unify the operation specifications regardless of the circuit configuration to which the flip-flop circuit is applied. Therefore, the unit cells of the automatic placement / wiring in which the driving capacity and the capacitive load of the circuit connected to the input / output terminal of the flip-flop circuit are actually different for each semiconductor integrated circuit device in which this flip-flop is used, or It is most suitable for use as a standard cell.

(9) The bypass circuit 41, together with the storage circuit
Since 42 also has the set / reset function using the common set signal S * and reset signal R *, the set / reset function can be prioritized over the control by the clock signal CLK even during the write operation. That is, regardless of the state of the clock signal CLK, the set / reset operation is prioritized in the entire flip-flop circuit.

(10) By providing the bypass circuit 41 for normal output and the bypass circuit 42 for inverted output separately, it is possible to easily correspond to the configuration of the flip-flop circuit having the normal output and the inverted output. You can

(11) Bypass circuit 4 in slave stage 52
If 1 and 42 are connected in parallel, it is possible to easily correspond to the configuration of a flip-flop circuit including two memory circuits of a master stage and a slave stage in a serial connection form.

(12) By constructing the bypass circuit by the BI-CMOS circuit including the bipolar transistor and the MOS transistor, the driving ability can be easily improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes.

For example, the information storage format in the storage circuit is not limited to the above embodiment, and other circuit formats such as the configuration shown in FIG. 14 can be adopted as appropriate. Further, the bypass circuit is not limited to the combination of the clocked inverter gate and the transfer gate, and can be configured by using other gates. Although the flip-flop circuit of the above embodiment shown in FIG. 5 has a set / reset function, the present invention is not limited to this, and both functions or one function may be omitted. For example, as shown in FIG. 11, the bypass circuit is connected to the inverter gate G4.
0 to G42 and switch gates G43 and G44 such as transfer gates, and the memory circuit can be constituted by inverter gates G45 to G48, switch gates G49 and G50 such as transfer gates, and static latch LAT. In addition, FIG.
As shown in FIG.
51 and clocked inverter gates G52 and G53, and the storage circuit includes inverter gates G54 and G55.
In addition, it can be constituted by clocked inverter gates G56 and G57 and a static latch LAT.

Further, although both the normal output and the inverted output are provided in the above embodiment, only one of them may be provided. Further, the flip-flop circuit is not limited to the level sense type and may be an edge sense type or an edge trigger type. The operation characteristics of the flip-flop circuit incorporated in the semiconductor integrated circuit device according to the present invention are not limited to the characteristic curve (a) of FIG. It may have a speed-up characteristic as described above.

In the above description, the MOS invention, which is the field of application of the invention mainly made by the present inventor, is the background of the invention.
The case where the present invention is applied to a microprocessor constituted by a semiconductor integrated circuit device has been described, but the present invention is not limited thereto and can be widely applied to various logic LSIs. According to the present invention, at least the operational performance of the flip-flop circuit arranged in the information transmission path is LSI.
It can be applied to the semiconductor integrated circuit device under the condition that affects the overall logical operation speed.

[0076]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in the bypass circuit connected in parallel to the storage circuit, the number of stages of built-in gates connected in series is smaller than that of the storage circuit, or the information transmission delay from the input terminal to the output terminal is smaller than that of the storage circuit. Due to
Normal information can be output at high speed before the writing operation of the memory circuit in synchronization with the change of the clock signal is completed. Therefore, it is possible to speed up the logical operation of the semiconductor integrated circuit device whose performance is determined by the clock signal cycle that defines the operation of the flip-flop circuit.

Then, such a semiconductor integrated circuit device is connected to a MOS.
Type semiconductor integrated circuit device, and by miniaturization of elements and promotion of power supply voltage drop accompanying this, it is possible to further speed up not only the flip-flop circuit but also the entire operation in accordance with the scaling rule, and high integration and There is an effect that a higher speed logical operation can be achieved in terms of the performance of the flip-flop circuit without sacrificing low power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an example of a level sense flip-flop circuit applied to a semiconductor integrated circuit device according to the present invention.

FIG. 2 is a diagram showing a layout in a chip of a microprocessor according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram showing an example of a critical path.

FIG. 4 is a characteristic explanatory diagram of a flip-flop circuit applied to the microprocessor of FIG.

FIG. 5 is a first master-slave flip-flop circuit applied to the semiconductor integrated circuit device according to the present invention.
It is an example circuit diagram.

FIG. 6 is a second master / slave flip-flop circuit applied to the semiconductor integrated circuit device according to the present invention.
It is an example circuit diagram.

FIG. 7 is a third master / slave flip-flop circuit applied to the semiconductor integrated circuit device according to the present invention.
It is an example circuit diagram.

FIG. 8 is a fourth master / slave flip-flop circuit applied to the semiconductor integrated circuit device according to the present invention.
It is an example circuit diagram.

FIG. 9 is a fifth master-slave flip-flop circuit applied to the semiconductor integrated circuit device according to the present invention.
It is an example circuit diagram.

FIG. 10 is a circuit diagram of an example of a BI-CMOS-based bypass circuit.

FIG. 11 is a circuit diagram showing an example of another flip-flop circuit applied to the semiconductor integrated circuit device according to the present invention.

FIG. 12 is a circuit diagram showing an example of still another flip-flop circuit applied to the semiconductor integrated circuit device according to the present invention.

FIG. 13 is a circuit diagram of a flip-flop circuit examined by the present inventor.

FIG. 14 is a circuit diagram of still another flip-flop circuit examined by the present inventor.

[Explanation of symbols]

1 microprocessor 5 instruction register 10 Operation register 15 Address register 30 flip-flop circuit 31 Clock signal input terminal 32 data input terminals 33,34 data output terminals 35 set terminals 36 reset terminal 40 memory circuit 41,42 Bypass circuit T1, T2, T5, T6 transfer gate G2, G4, G7, G10, G11 Inverter gate G20, G21 Clocked inverter gate MP3, MP6 p-channel MOS transistor MN3, MN6 n-channel MOS transistor Q Forward output Q * inverted output CLK clock signal D input data R * reset signal S * set signal 50 flip-flop circuit 51 master stage 52 slave stages T14, T15 transfer gate G30 Inverter gate BT1, BT2 bipolar transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-58-79328 (JP, A) JP-A-55-3234 (JP, A) JP-A-5-191220 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H03K 3/356 G06F 15/78 510 G06F 7/00 G06F 13/42 350 G11C 11/413

Claims (4)

(57) [Claims] 1. In a semiconductor integrated circuit in which a logical operation timing is determined by a clock synchronous operation with respect to a flip-flop circuit arranged in an information transmission path, the flip-flop circuit has a data input terminal and a data non-inversion output terminal. Data is written from the input terminal in synchronization with a data inversion output terminal and a clock signal , the written data is held, and the held data is output to the non-inversion output terminal in a non-inversion state. A storage unit that outputs the held data to the inversion output terminal in an inverted state, and outputs the data to the non-inversion output terminal in a write state in which the data is written to the storage unit in synchronization with the clock signal. However, in the holding state of the data written in the storage means, the data is cut off from the non-inverting output terminal. Written to the non-inverting bypass circuit and the data in synchronization with said clock signal said memory means that
Output to come the inverting output terminal and inverting the data in the write state to be written, viewed contains a inverting bypass circuit is disconnected from the inverting output terminal in a holding state of the data written in the storage means, wherein The non-inverting bypass circuit and the inverting bypass circuit,
The signal propagation time is set shorter than that of the storage means.
The semiconductor integrated circuit, characterized in that that. 2. The memory device further includes a set terminal and a reset terminal for the storage means, and the inverting bypass circuit resets the inverting output terminal of the storage means in the write state in response to a reset state instruction for the reset terminal. The output state in the state, in response to the set state instruction to the set terminal, the inverting output terminal is forced to the output state in the set state of the storage means, the non-inverting bypass circuit in the write state,
In response to the reset state instruction to the reset terminal,
Forcing the non-inverting output terminal equal to the output state of the storage means in the reset state, and forcing the non-inverting output terminal equal to the output state of the storage means in the set state in response to an instruction of the setting state to the set terminal. The semiconductor integrated circuit according to claim 1, wherein 3. The semiconductor integrated circuit according to claim 1, wherein the storage unit and the bypass circuit have a driver circuit for driving a load to be coupled to the output terminal. . 4. A microcomputer having a register constituted by the flip-flop circuit,
Claims characterized by being formed into chips
4. The semiconductor integrated circuit according to any one of 1 to 3.