JP2723765B2 - Programmable logic array and microcomputer using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable logic array and a microcomputer in which the programmable logic array is integrated on the same chip.

[0002]

2. Description of the Related Art With the recent advancement of functions and performance of electronic devices, semiconductor integrated circuits used in the electronic devices are also required to have higher functions and higher performance. Also, in order to differentiate products, electronic device design engineers are demanding semiconductor integrated circuits that are not general-purpose products but special-purpose products specialized for the electronic devices. Semiconductor integrated circuits optimal for such applications include so-called application-specific integrated circuits (hereinafter referred to as ASICs) such as gate arrays and standard cells, and microcomputers. The ASIC can realize a desired function by converting hardware (circuit) desired by an electronic device design engineer into a semiconductor integrated circuit.
The microcomputer can realize a desired operation by rewriting software (program). Further, a semiconductor integrated circuit called an ASIC microcomputer having both features has been devised.

On the other hand, the development period of electronic equipment has been shortened year by year. Along with this, an electronic device design engineer designs a desired semiconductor integrated circuit at a development site and desires to obtain a product designed on the site. However, the above-described semiconductor integrated circuits such as gate arrays, standard cells, and microcomputers have a certain period of time from design to acquisition of a product (hereinafter referred to as lead time) in order to produce desired functions in the manufacturing process. Cost. In order to meet the demands of electronic equipment design engineers for shortening the lead time, field programmable gate arrays (hereinafter referred to as FPGAs) and microcomputers with built-in programmable ROMs (hereinafter referred to as PROMs) have been devised. I have.

[0004] These semiconductor integrated circuits are capable of creating desired hardware (circuits) and writing software (programs) using dedicated devices at the site of development, and are therefore lead by electronic equipment design engineers. It satisfies the demand for time reduction.

[0005] One of such semiconductor integrated circuits is a programmable logic array (hereinafter referred to as PLA) that enables writing at a development site. PLA is widely used because it can generate various logic functions with a regular program.

The PLA is programmed by the presence or absence of a transistor at the intersection of the input line and the product term line and the product term line and the output line. Generally, a transistor having a floating gate, avalanche injection, MOS (hereinafter referred to as FAMOS) structure is used to rewrite the program, but a high voltage power supply of 10 V or more is used for writing data. Therefore, a PLA has been devised in which data is written into a static RAM cell so that a program can be rewritten with a single power supply (eg, Japanese Patent Application Laid-Open No. 1-238219).

FIG. 5 shows the structure of this conventional PLA. φ
1 and φ2 are clocks having different phases. Clock φ1
Becomes high level, the NMOS transistor Tφ1 is turned on, and the product term line is precharged to high level. When the clock φ2 goes high, NMO
The S transistor Tφ2 is turned on, and the output line is precharged to a high level.

Inverter latch R on AND plane
0, R1 and transmission gates TR0, TR
Static RA in which 1 stores information of “1” and “0”
When a word line is externally selected in the M cell, the corresponding transmission gates TR0 and TR1 are turned on, and predetermined information is stored in the corresponding inverter latches R0 and R1 through the bit lines BL and NBL. Also, AN
0 and AT0 are NMOS transistors, and AN0 is P
A transistor for generating an AND condition of LA.
T0 is a transistor for controlling whether or not to connect the transistor AN0 to the product term line.

If the potential at the point B of the inverter latch is at a high level and the potential at the point A is at a low level, the transistor AT0 is turned off, and the transistor AN0 for generating the AND condition is disconnected from the product term line. That is, the corresponding product term line remains precharged. On the other hand, when the potential at the point B of the inverter latch is low level,
When the potential of the point is at a high level, the transistor AT0 is turned on, and the transistor AN that generates the AND condition is turned on.
0 is connected to the product term line. Therefore, if the potential of the input line is at a high level, the transistor AN0 is turned on, and the potential of the corresponding product term line is pulled down through the transistor AN0 to be at a low level. That is, the information written in the static RAM cell allows the AND plane of the PLA to be programmed to a desired state, and a signal of a desired AND condition is output from the product term line.

Similarly, also on the OR plane, inverter latches R2 and R3 and transmission gate TR
2. A desired state is programmed by controlling whether or not to connect an NMOS transistor ON0, which generates an OR condition based on information written in a static RAM cell composed of TR3, to an output line, by using an NMOS transistor OT0. It is possible to output a signal of a desired OR condition from the output line.

[0011]

However, the PLA structured as described above has the following three problems.

First, when the potential of the product term line (or output line) is pulled down to a low level, the electric charge is transferred to the NMOS transistors AT0 and AN0 and the inverter gate R1.
Transistors (or NMOS transistors OT0, ON0, and inverter gate R3)
Is discharged through the NMOS transistor that constitutes the transistor. Therefore, in order to increase the discharge rate, the capacity of each transistor must be increased, and the area required to realize a semiconductor integrated circuit increases. Conversely, when the area is reduced, the discharge speed is reduced.

Second, since the bit lines BL and NBL for writing data to the static RAM cell and the input line to the AND plane are independent, the number of wirings increases, which is necessary to realize a semiconductor integrated circuit. The area increases.

Third, all the product term lines are once precharged to a high level, and then all product term lines are pulled down to a low level except for the product term lines for which the AND condition is satisfied. Therefore, unnecessary electric charges are discharged, so that current consumption is increased.

On the other hand, microcomputers, especially one-chip microcomputers, integrate various peripheral functions (hardware) on the same chip. A wide variety of functions can be realized by a combination of the peripheral function and software (program). However, functions attributable to hardware can be realized only within the range of functions prepared by the manufacturer in advance. For example, an N-bit counter alone can only count up to 2 ^N times and produce an overflow output. However,
By using two N-bit counters and using the overflow output of one N-bit counter as a set signal and the overflow output of the other N-bit counter as a reset signal, a pulse width modulation (hereinafter referred to as PWM) signal is used. Can be generated. If such a function is prepared by the manufacturer, a PWM signal can be generated, but otherwise, generation of a PWM signal cannot be realized.

Generally, a manufacturer preliminarily assumes a function desired by a user and makes preparations for realizing a plurality of functions, but it is impossible to satisfy the needs of all users.

[0017]

In order to solve the above-mentioned problems, the present invention provides a PLA having N inputs to the AND plane, M product terms, and K outputs in the OR plane. Thus, two MOS transistors connected in series as a set
In the AND plane, (N × M) pairs of transistors and (N × M)
A (M) -bit storage element is provided, and (M × K) sets of transistors and a (M × K) -bit storage element are provided on the OR plane.
The source of a pair of MOS transistors arranged on the ND plane is at the power supply potential, the drain is at the product term line,
An input line to the AND plane is connected to the gate of the S transistor,
The output signal of the storage element arranged on the AND plane is connected to the gate of the other MOS transistor, the source of the pair of MOS transistors arranged on the OR plane is set to the power supply potential, and the drain is set to the output of the OR plane. Line, one MO
The product term line is connected to the gate of the S transistor, and the output signal of the storage element arranged on the OR plane is connected to the gate of the other MOS transistor, and the program of the PLA can be freely performed by an arbitrary value set in the storage element. Things.

In order to reduce the number of wirings, a bit line for reading and writing data to and from a storage element and an A
The product term line on the ND plane or the output line on the OR plane is commonly used.

Further, the above-mentioned PLA is integrated on the same chip as the microcomputer, and the behavior of the peripheral functions of the microcomputer can be freely set by setting data in the storage element by executing instructions. .

[0020]

According to the present invention, the AND condition and the OR condition of the PLA can be freely programmed according to the value set in the storage element. In addition, by integrating the PLA on the same chip as the microcomputer, it becomes possible to program the PLA by executing the instructions of the microcomputer, and realize the desired function by combining the peripheral functions of the microcomputer with arbitrary logic functions. It is possible to do. Furthermore, the realized peripheral functions are not fixed to one function, but can be dynamically changed as needed by the processing of the microcomputer.

[0021]

FIG. 1 shows a configuration of a PLA (a configuration of one PLA element) according to a first embodiment of the present invention. φ1 and φ2 are clocks having different phases. When the clock φ1 becomes high level, the NMOS transistor Tφ1 is turned on, and the product term line is precharged to high level. When the clock φ2 becomes high level, the NMOS transistor Tφ
2 is turned on, and the bit line / output line BOL is precharged to a high level.

Inverter latch R in AND plane
0, R1 and transmission gates TR0, TR
1 and the inverter latches R2, R3 in the OR plane
And transmission gates TR2 and TR3 are static RAM cells for storing information of "1" and "0".

When writing data in a static RAM cell, the control line C is set to a high level so that the NMOS
The transistor Tc is turned on, and the product term line is pulled down to a low level. Therefore, NM in the OR plane
The OS transistor ON0 is turned off, and the bit line and output line are not affected by the state of the NMOS transistor OT0. In this case, the PLA functions as a normal storage device.

When a word line is externally selected on the AND plane, the corresponding transmission gate TR0,
TR1 is turned on, and the corresponding inverter latch R0, R1 is passed through the bit line / input line BIL and bit line NBL.
1 stores predetermined information. AN0 and AT0
Is an NMOS transistor, AN0 is a transistor for generating an AND condition of PLA, and AT0 is a transistor for controlling whether or not to connect the transistor AN0 to a product term line.

If the potential at the point B of the inverter latch is at a high level and the potential at the point A is at a low level, the transistor AT0 is turned off, and the transistor AN0 for generating the AND condition is disconnected from the product term line. That is, the corresponding product term line remains precharged. On the other hand, when the potential at the point B of the inverter latch is low level,
When the potential of the point is at a high level, the transistor AT0 is turned on and the transistor AN0 that generates an AND condition
Is connected to the product term line. Therefore, if the potential of the input line is at a high level, the transistor AN0 is turned on, and the potential of the corresponding product term line is pulled down through the transistor AN0 to be at a low level. That is, the information written in the static RAM cell is
The ND plane can be programmed to a desired state, and a signal of a desired AND condition is output from the product term line.

Similarly, in the OR plane, inverter latches R2 and R3 and transmission gate TR
2. According to the information written in the static RAM cell constituted by TR3, whether or not the NMOS transistor ON0 for generating the OR condition is connected to the bit line / output line BOL is controlled by the NMOS transistor OT0, thereby making it desirable. State can be programmed. In other words, the desired O / L is determined depending on whether the bit line / output line BOL is kept precharged or pulled down to a low level.
The signal of the R condition is output.

FIG. 2 shows a PLA according to a second embodiment of the present invention.
(The configuration of one PLA element) is shown. In this embodiment, the static RAM cell of the first embodiment is replaced with a flip-flop as a storage element. φ1 and φ
Reference numeral 2 denotes clocks having different phases. When the clock φ1 becomes high level, the NMOS transistor Tφ1 is turned on, and the product term line is precharged to high level. When the clock φ2 goes high, the NMOS transistor Tφ2 is turned on, and the bit line and output line BOL is precharged to high level. M on the AND plane
1 and M2 in the OR plane are flip-flops for storing information of "1" and "0".

When writing data to the flip-flop, the NMOS transistor Tc is turned on by setting the control line C to high level, and the product term line is pulled down to low level. Therefore, the NMOS transistor ON0 in the OR plane is turned off, and the bit line and output line are not affected by the on / off state of the NMOS transistor OT0. In this case, the PLA functions as a normal storage device.

When a word write line is externally selected on the AND plane, predetermined information is stored in the corresponding flip-flop M1 through the bit line and input line BIL. AN0 and AT0 are NMOS transistors, AN0 is a transistor for generating an AND condition of PLA, and AT0 is a transistor for controlling whether or not to connect the transistor AN0 to a product term line.

If the Q output of the flip-flop is low, the transistor AT0 is turned off,
The transistor AN0 that generates the AND condition is disconnected from the product term line. That is, the corresponding product term line remains precharged.

On the other hand, when the Q output of the flip-flop is at a high level, the transistor AT0 is turned on and A
The transistor AN0 that generates the ND condition is connected to the product term line. Therefore, when the potential of the input line is at a high level, the transistor AN0 is turned on, and the potential of the corresponding product term line is pulled down through the transistor AN0 to be at a low level. That is, the information written in the flip-flop enables the AND plane of the PLA to be programmed to a desired state, and a signal of a desired AND condition is output from the product term line.

Similarly, also in the OR plane, the information written in the flip-flop M2 changes the NMOS transistor ON0 for generating the OR condition to the bit line / output line BO.
By controlling whether to connect to L by the NMOS transistor OT0, it is possible to program to a desired state, and a signal of a desired OR condition is output from the bit line and output line BOL.

When reading the information written in the flip-flops M1 and M2, the word read line is selected while the control line C is at a high level. At this time, the tristate gates G1 and G2 are turned on, and the information of the flip-flop is output to the bit line / input line BIL or the bit line / output line BOL.

FIG. 3 shows a PLA according to a third embodiment of the present invention.
(The configuration of one PLA element) is shown. φ1 and φ2
Are clocks with different phases. When the clock φ1 goes high, the NMOS transistor Tφ1 is turned on, one of the inputs of the NOR gate G0 is precharged to a high level, and the output of the NOR gate G0 goes low. When the clock φ2 goes high, NM
The OS transistor Tφ2 is turned on, and the bit line / output line BOL is precharged to a high level. AND
Inverter latches R0, R1 (R0 ', R0
1 ') and transmission gates TR0, TR1
(TR0 ', TR1') and the inverter latches R2, R3 and the transmission gates TR2, TR3 in the OR plane are static RAM cells for storing information "1" and "0".

When writing data in the static RAM cell, the control line C is set to the high level, so that NO
The output of the R gate G0, that is, the product term line goes low. Therefore, the NMOS transistor ON0 in the OR plane is turned off, and the bit line and output line
It is not affected by the state of the S transistor OT0. In this case, the PLA functions as a normal storage device.

When a word line is externally selected on the AND plane, the corresponding transmission gate TR0,
TR1 is turned on, and the corresponding inverter latch R0, R1 is passed through the bit line / input line BIL and bit line NBL.
1 stores predetermined information. AC0 and AP
0 is an NMOS transistor, AP0 is an AND of PLA
A transistor for generating a condition, AC0 is a transistor for controlling whether or not the transistor AP0 connected in series to the product term line is enabled.

If the potential at the point B of the inverter latch is low and the potential at the point A is high, the transistor AC0 is turned on and the transistor AP0 that generates the AND condition is disabled. That is, since the transistor AP0 is always bypassed irrespective of the ON / OFF state of the transistor AP0, whether the corresponding product term line remains precharged,
It is not a factor to determine whether the signal is pulled down to the low level. On the other hand, when the potential at point B of the inverter latch is at a high level and the potential at point A is at a low level, the transistor A
C0 is turned off, and the transistor AP0 that generates the AND condition becomes effective. That is, the transistor AP
Since whether or not to bypass is selected depending on the on / off state of 0, it becomes a factor to determine whether the corresponding product term line remains precharged or pulled down to a low level. Therefore, when the potential of the input line is at a high level, the transistor AP0 is turned on to be in a bypass state, and when all the transistors connected in series to the corresponding product term line are in a bypass state, the potential of the product term line is lowered. Are pulled down through the transistors AP0,..., AP0 ′, and become low level. When at least one of the transistors connected in series to the product term line is not in the bypass state, the potential of the product term line remains precharged. That is, the information written in the static RAM cell
The AND plane of A can be programmed to a desired state, and a signal of a desired AND condition is output from the product term line.

In the OR plane, as in the first embodiment, a static R composed of inverter latches R2 and R3 and transmission gates TR2 and TR3 is used.
According to the information written in the AM cell, the NMOS transistor ON0 generating the OR condition is set to the bit line / output line BO.
By controlling whether or not to connect to L by the NMOS transistor OT0, it is possible to program to a desired state. That is, a signal of a desired OR condition is output depending on whether the bit line / output line BOL is kept precharged or pulled down to a low level.

FIG. 4 shows a PLA according to a fourth embodiment of the present invention.
(The configuration of one PLA element) is shown. In this embodiment, the static RAM cell of the third embodiment is replaced by a flip-flop as a storage element. φ1 and φ
Reference numeral 2 denotes clocks having different phases. When the clock φ1 becomes high level, the NMOS transistor Tφ1 is turned on, and the product term line is precharged to high level. When the clock φ2 goes high, the NMOS transistor Tφ2 is turned on, and the bit line and output line BOL is precharged to high level. M on the AND plane
1 and M2 in the OR plane are flip-flops for storing information of "1" and "0".

When writing data to the flip-flop, the NOR line G is set by setting the control line C to high level.
The output of 0, that is, the product term line becomes low level. Therefore, the NMOS transistor ON0 in the OR plane is turned off, and the bit line and output line are not affected by the state of the NMOS transistor OT0. In this case book P
The LA functions as a normal storage device.

When a word write line is externally selected on the AND plane, predetermined information is stored in the corresponding flip-flop M1 through the bit line and input line BIL. AC0 and AP0 are NMOS transistors, AN0 is a transistor for generating the AND condition of PLA, AP0 is a transistor for generating the AND condition of PLA, and AC0 is a transistor connected in series to the product term line. This is a transistor for controlling whether or not to make AP0 valid.

If the Q output of the flip-flop is at a high level, the transistor AC0 turns on and A
The transistor AP0 that generates the ND condition is invalidated (that is, since the transistor AP0 is always bypassed regardless of the on / off state of the transistor AP0, it is determined whether the corresponding product term line remains precharged or pulled down to a low level). Is not a factor). On the other hand, Q of flip-flop
When the output is at the low level, the transistor AC0 is turned off, and the transistor AP0 that generates the AND condition is enabled (that is, whether or not the transistor AP0 is turned on or off by the on / off state is selected. It determines whether the line remains precharged or pulled down to low level). Therefore, when the potential of the input line is at a high level, the transistor AP0 is turned on to be in a bypass state, and when all the transistors connected in series to the corresponding product term line are in a bypass state, the potential of the product term line becomes low. Transistor AP
0,..., AP0 ′ are pulled down to a low level. When at least one of the transistors connected in series to the product term line is not in the bypass state, the potential of the product term line remains precharged. That is, the static R
The information written in the AM cell enables the AND plane of the PLA to be programmed to a desired state, and a signal of a desired AND condition is output from the product term line.

On the OR plane, as in the second embodiment, the information written in the flip-flop M2
By controlling with the NMOS transistor OT0 whether or not the NMOS transistor ON0 for generating the OR condition is connected to the bit line / output line BOL, it is possible to program to a desired state.
Output a signal of a desired OR condition.

When reading information written in the flip-flops M1 and M2, the word read line is selected while the control line C is at a high level. At this time, the tristate gates G1 and G2 are turned on, and the information of the flip-flop is output to the bit line / input line BIL or the bit line / output line BOL.

In the first, second, third, and fourth embodiments, the transistors Tφ1, Tφ2, AT0, AN
Although 0, AC0, AP0, ON0, and OT0 are constituted by NMOS transistors, they can be constituted by PMOS transistors. However, the polarity of the signal input to the gate is reversed. In the second and fourth embodiments, the tri-state gate is used for reading the flip-flop. However, an open drain gate can be used.

FIG. 6 shows an embodiment of a microcomputer in which the PLA of the present invention is integrated on the same chip. By integrating them in the same chip as the microcomputer, a desired value can be set for the storage element in the PLA by executing an instruction.

B1,..., B1 'are peripheral function blocks,
B2 is a DMA (Direct Memory Access) device,
B3 is an interrupt control circuit, L1 is an input signal synchronization circuit,
L2 is a register that can set a desired value by executing the instruction, L3 is a register that holds the output of the OR plane and can read the value by executing the instruction, and L4 is an output signal synchronization circuit.

On the AND plane of the PLA, (1) an output signal from at least one or more peripheral function blocks, and (2) a signal input from at least one or more inputtable terminals PI is input to an input signal synchronization circuit. A signal synchronized with the operation of the microcomputer at L1. (3) An output signal of the register L2 of at least 1 bit, which can be set to a desired value by executing an instruction. (4) An output of an OR plane of at least 1 bit. (5) An output signal synchronization circuit L of at least one bit or more
In step 4, the output of the OR plane synchronized with the operation of the microcomputer is input.

Here, as the output signals of the peripheral function block, (1) the most significant output signal of the N-bit counter, (2) the overflow signal of the N-bit counter, and (3) the value of the N-bit counter and the value of the N-bit register. (4) There are interrupt request signals from various peripheral function blocks to the CPU.

On the other hand, the output of the OR plane is held in (1) a register L3 of at least one bit which can be read by executing the instruction. (2) The output signal is synchronized with the operation of the microcomputer by the output signal synchronization circuit L4, and is output from at least one or more outputable terminals PO. (3) It is input to the DMA device B2 as a transfer request signal.

The types of the input signal to the AND plane and the output signals from the OR plane do not need to satisfy all the above-mentioned types, and some of them may be selected as needed.

FIG. 7 is a block diagram for explaining the operation of the present invention. In the figure, B1 and B1 'are N-bit counters, and L4 is an output signal synchronization circuit. The N-bit counter B1 'is reset by the overflow signal X of the N-bit counter B1. The overflow outputs X and Y of the N-bit counters B1 and B1 ', the output W of the OR plane, and the signal Z synchronized with the operation of the microcomputer by the output synchronization circuit L4 are input to the input lines of the AND plane of the PLA. Have been. The synchronization signal Z is output from the output terminal PO to the outside of the chip.

Here, it is assumed that the output terminal PO is set when the N-bit counter B1 overflows, and the output terminal PO is reset when the N-bit counter B1 'overflows. That is, the PWM signal is output from the output terminal PO. The truth table in this case is as follows.

[0054] That is,

[0055]

## EQU1 ## W = X + Z

By programming the logical function into the PLA, a waveform as shown in FIG. 8 can be output from the output terminal PO.

As described above, according to the present invention, a desired value can be set to a storage element of a PLA by executing an instruction. That is, since the PLA can be freely programmed, a desired function can be realized by combining the peripheral functions of the microcomputer input to the AND plane of the PLA with arbitrary logical functions. In addition, not only signals determined by hardware such as an overflow signal of a counter but also signals determined by software such as a register L2 are input to the input to the AND plane. Free functions can be realized. on the other hand,
Since the output of the OR plane is a transfer request signal of the DMA device, data transfer by the serial interface,
In the case where the transfer is performed only under certain specific conditions, for example, in capture data transfer at the time of input capture input, the transfer may be performed only by hardware without software intervention.

Further, when the PLA of the present invention is integrated on the same chip as a microcomputer with a built-in PROM, the program of the microcomputer and the program of the PLA can be made at the development site, so that the lead time can be further reduced.

[0059]

As described above, according to the present invention, (1) When the potential of the product term line is pulled down to a low level, the electric charge is reduced to the NMOS transistor AT on the AND plane.
Since the discharge is performed only through the NMOS transistors OT0 and ON0 in the OR plane, the operation can be performed at a higher speed than the conventional PLA. (2) Since the bit line and the input line or the bit line and the output line are also used, the number of wirings does not increase, and the chip area does not increase when implementing a semiconductor integrated circuit. (3) According to the invention shown in the third or fourth embodiment, the potential of the product term line changes only in the selected signal line, so that no extra charge is discharged and the current consumption can be reduced. (4) A desired function can be realized by combining peripheral functions of the microcomputer with an arbitrary logical function. Also,
Since the PLA program can be rewritten by executing the instruction, its function can be dynamically changed in one system.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a PLA as a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a PLA as a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a PLA according to a third embodiment of the present invention;

FIG. 4 is a circuit diagram showing a configuration of a PLA according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a conventional PLA.

FIG. 6 is a block diagram showing a microcomputer of the present invention.

FIG. 7 is a block diagram for explaining the operation of the microcomputer of the present invention;

FIG. 8 is a timing chart for explaining the operation of the microcomputer of the present invention;

[Explanation of symbols]

 AT0 NMOS transistor AN0 NMOS transistor ON0 NMOS transistor OT0 NMOS transistor AC0 NMOS transistor AP0 NMOS transistor Tφ1-2 Precharging NMOS transistor Tc Pulldown NMOS transistor TR0-3 Transmission gate R0-3 Inverter gate M1-2 Flip-flop G0 NOR gate G1 To 2 tri-state gate BIL bit line and input line NBL bit line C control line BOL bit line and output line B1 peripheral function block B2 DMA device B3 interrupt control circuit L1 input signal synchronization circuit L2-3 register L4 output signal synchronization circuit X, Y overflow signal

Claims (24)

(57) [Claims] 1. The number of inputs to the AND plane is N and the number of product terms is M
The number of outputs on the OR plane is K, and whether or not the transistor at the intersection of the input line to the AND plane and the product term line is connected to the product term line is controlled by data written in the storage element. In the AND plane of the programmable logic array to be performed, two (N × M) transistors and a (N × M) -bit storage element are provided as a set of two transistors connected in series, and are connected in series. The source of the pair of transistors thus obtained is set to the power supply potential, the drain is set to the product term line, the gate of one transistor is connected to the input line to the AND plane, and the gate of the other transistor is set to the output signal of the storage element A programmer, wherein whether or not to connect a transistor for generating an AND condition based on data set in the storage element to a product term line can be freely programmed. Bull logic array. 2. The number of inputs to the AND plane is N and the number of product terms is M
The number of outputs on the OR plane is K, and whether or not the transistor at the intersection of the product term line and the output line on the OR plane is connected to the output line on the OR plane is controlled by data written in the storage element. In the OR plane of the programmable logic array for performing the above, two (M × K) transistors and a (M × K) bit storage element are provided as a set of two transistors connected in series, and The source of the connected pair of transistors is at the power supply potential, the drain is at the output line of the OR plane, the product term line is at the gate of one transistor, and the output of the storage element is at the gate of the other transistor. A signal generating circuit for generating an OR condition based on data set in the storage element, and whether or not to connect the transistor to an output line can be freely programmed. Gramable logic array. 3. The number of inputs to the AND plane is N and the number of product terms is M
In the AND plane of the programmable logic array having K output planes and K output planes, N pairs of transistor pairs, each of which includes two transistors having a source and a source and a drain and a drain connected in parallel, are connected in series. The connected devices are regarded as a group, and the transistors of the M group and (N ×
M) a bit storage element, wherein a source of a transistor pair at one end of the group of transistors connected in series is connected to a power supply potential, and a drain of the transistor pair at the other end is connected to a product term line; An input line to the AND plane is connected to the gate of one transistor of each transistor pair, and an output signal of the storage element is connected to the gate of the other transistor to generate an AND output of the input line. A programmable logic array wherein whether or not a desired input line is included in an AND condition can be freely programmed by data set in a storage element. 4. The programmable logic array according to claim 1, wherein (N × M) bits of storage elements are set to AN.
Arranged in an array on the D-plane, and M
Connected to the storage element, read and write data to and from the storage element via the bit line, and connect a corresponding storage element to one gate of a pair of transistors connected in series. A programmable logic array, wherein the same bit line is connected to share one signal line as a bit line and an input line to the AND plane. 5. The programmable logic array according to claim 2, wherein (M × K) bits of storage elements are ORed.
M storage elements are connected to the same bit line in an array on a plane, and data is read from and written to the storage element via the bit line. Programmable logic characterized in that one signal line is shared by the bit line and the output line of the OR plane by connecting the drain of each set of transistors to the same bit line as the corresponding storage element. ·array. 6. The programmable logic array according to claim 3, wherein (N × M) bits of storage elements are set to AN.
Arranged in an array on the D-plane, and M
Connected to the storage element, data is read from and written to the storage element via the bit line, and the corresponding storage element is connected to the gate of one of the two transistor pairs connected in parallel. A programmable logic array characterized in that one signal line is shared as a bit line and an input line to an AND plane by connecting the same bit line to an element. 7. The programmable memory according to claim 1, wherein the AND plane according to any one of claims 1, 3, 4 and 6 is combined with the OR plane according to claim 2 or 5. -Logic array. 8. The power supply according to claim 4, which has an AND plane according to claim 4 and an OR plane according to claim 5, and sets a potential of a product term line to a power supply connected to a source of a pair of transistors connected in series. In the case where data is read or written to or from a memory element, the potential of the product term line is fixed to the potential of a source, and the transistor whose product term line is input to a gate is provided. A programmable logic array which is turned off. 9. An AND plane according to claim 6 and an OR plane according to claim 5, wherein a logic inversion and a product term line in the AND plane and a product term line in the OR plane are provided. And control means for fixing the product term line in the OR plane to the potential of a power supply to which the source of a pair of transistors connected in series is connected. When writing, the O
A programmable logic array, wherein the potential of a product term line in an R plane is fixed to the potential of a source, and the product term line turns off a transistor input to a gate. 10. A means for instructing the programmable logic array according to any one of claims 7 to 9 to function as a programmable logic array or a storage device. To function as a memory device, the potential of the product term line is fixed to the potential of a power supply to which the sources of a pair of transistors connected in series in the OR plane are connected.
A programmable logic array, wherein the function of the programmable logic array is eliminated and the programmable logic array can be used as a general-purpose data storage device. 11. A microcomputer comprising the programmable logic array according to claim 1 integrated in a single chip. 12. The programmable logic array A
12. The microcomputer according to claim 11, wherein an uppermost output signal of an N-bit counter integrated in the same chip is connected to an input line to the ND plane. 13. The programmable logic array A
12. The microcomputer according to claim 11, wherein an overflow signal of an N-bit counter integrated in the same chip is connected to an input line to the ND plane. 14. An N-bit counter, a register for holding N-bit data, and a comparator for comparing a count value of the N-bit counter with a value held in the N-bit register. 12. The microcomputer according to claim 11, wherein a comparison output signal of the comparator is connected to an input line to an AND plane of the programmable logic array. 15. Means for synchronizing a signal inputted from an input terminal or an input / output terminal with a system clock of a microcomputer, and synchronizing the synchronized terminal input signal to an input line to an AND plane of the programmable logic array. The microcomputer according to claim 11, wherein the microcomputer is connected. 16. The microcontroller according to claim 11, wherein an interrupt request signal from a peripheral function block integrated in the same chip to the CPU is connected to an input line to an AND plane of the programmable logic array. Computer. 17. A semiconductor memory device comprising: a register for setting a desired value from a CPU by execution of an instruction; and at least one bit, wherein an output of said register is connected to an input line to an AND plane of a programmable logic array. A microcomputer according to claim 11. 18. A programmable logic array, comprising:
12. The microcomputer according to claim 11, wherein at least one or more output signals of the R plane are input as an interrupt request signal to an interrupt control circuit integrated on the same chip. 19. The O of the programmable logic array.
At least one output signal of the R plane is used as a transfer request signal in a DMA (direct
12. The microcomputer according to claim 11, wherein the microcomputer is connected to a memory access device. 20. The programmable logic array, comprising:
2. The system according to claim 1, wherein at least one of the output signals of the R plane is output from an output terminal or an input / output terminal in synchronization with a system clock of the microcomputer.
2. The microcomputer according to 1. 21. At least one of output signals of an OR plane synchronized with a system clock of a microcomputer.
12. The microcomputer according to claim 11, wherein at least one of the microcomputers is connected to an input line to an AND plane of the programmable logic array. 22. The programmable logic array O
12. The microcomputer according to claim 11, further comprising means for holding at least one or more output signals on the R plane, wherein the value of the held output signal can be read by executing an instruction. 23. The programmable logic array O
Means for holding at least one output signal of the R plane, wherein at least one of the held output signals is connected to an input line to an AND plane of the programmable logic array. Item 12. The microcomputer according to Item 11. 24. A rewritable nonvolatile memory element for storing instructions and a programmable logic array integrated on the same chip.
24. The microcomputer according to claim 23.