JP3479389B2 - Data processing system and semiconductor integrated circuit - Google Patents

Data processing system and semiconductor integrated circuit

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Publication number
JP3479389B2
JP3479389B2 JP17817095A JP17817095A JP3479389B2 JP 3479389 B2 JP3479389 B2 JP 3479389B2 JP 17817095 A JP17817095 A JP 17817095A JP 17817095 A JP17817095 A JP 17817095A JP 3479389 B2 JP3479389 B2 JP 3479389B2
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Prior art keywords
clock signal
clock
signal
output
circuit
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JPH096462A (en
Inventor
和良 庄司
嘉隆 木下
一正 柳沢
貞幸 森田
清 永井
孝一郎 石橋
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株式会社日立製作所
株式会社日立超エル・エス・アイ・システムズ
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Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system which operates in synchronization with a clock signal, and more particularly to a semiconductor integrated circuit which operates using an externally applied clock signal as an operation reference clock signal, for example, a microprocessor,
The present invention relates to a technique effective when applied to a computer system including a DMA (direct memory access) controller, an input / output controller, a clock synchronous RAM (random access memory), and the like.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit which operates in synchronization with a clock signal, a stable internal clock signal synchronized with an externally supplied clock signal is generated, or an internal clock signal frequency is set to an external clock signal frequency. A PLL (Phase Locked Loop) circuit can be incorporated in order to perform multiplication. Further, in the computer system, when the input / output operation is not performed for a certain period of time and the high speed operation of the microprocessor is not required, it is possible to adopt the power management technique of lowering the clock signal frequency of the system from the viewpoint of low power consumption. As an example of a document describing the PLL circuit, there are pages 164 to 169 of "Digital Signal Processing System" issued by Tokai University Press on October 25, 1986.

[0003]

The present inventor uses a PLL circuit as a clock pulse generator of a semiconductor integrated circuit, and when the frequency of an external clock signal is lowered by power management control or the like, the frequency is changed accordingly. The period until the internal clock signal is stabilized was examined. The PLL circuit detects the phase error between the external clock signal and the output signal of the voltage controlled oscillator by the phase comparator, feeds back the detected phase error voltage to the voltage controlled oscillator through the loop filter, and outputs the output signal frequency of the voltage controlled oscillator. And the phase is synchronized with the external input signal. In general, the synchronization process in the PLL circuit can be considered by dividing it into two steps of synchronizing in the phase synchronization process after the frequencies are close to each other in the frequency pulling process. Further, when the input signal frequency is changed beyond the lock range, the PLL circuit cannot hold the synchronization state, and the above synchronization process is newly followed. In such a synchronization process, the output clock signal from the PLL circuit is unstable, and it is desirable to suspend the operation of the system until it stabilizes. It is also envisaged that the idle period of such an operation may last several hundred cycles of the clock signal. However, during that time, the operation of the system is waited, and the continuity of processing cannot be guaranteed. In addition, the operation time of a test that is performed by changing the clock signal frequency midway becomes long.

An object of the present invention is to provide a data processing system capable of shortening the idle period of system operation by switching the clock signal frequency of the system. Another object of the present invention is to provide a semiconductor integrated circuit that can immediately follow an internal clock signal when the frequency of a clock signal supplied from the outside is changed.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

The data processing system generates a first clock signal (PCLK) and a second clock signal (CLK) having a frequency equal to the frequency of the first clock signal and mutually delayed in phase for a certain time. A plurality of circuit units (2, 3) each of which is a semiconductor integrated circuit and has a clock pulse generator (10) for performing a synchronous operation upon receiving the first and second clock signals.
BUS, ABUS) are shared. The circuit unit receives a first clock signal and a second clock signal to form an internal clock signal.
0), and the delay locked loop circuit comprises a first
A first clock input buffer (21) for receiving the second clock signal, a second clock input buffer (22) for receiving the second clock signal, and an output clock signal of the first clock input buffer variably delayed. Variable delay means (23) for forming an internal clock signal, and phase difference detecting means (24) for detecting a phase difference between the internal clock signal and the clock signal output from the second clock input buffer, and this position. Delay control means (25, 26 or 26 to 29) for controlling the delay time by the variable delay means so as to cancel the phase difference detected by the phase difference detection means.
And

The clock pulse generator can be included in one circuit unit (1) such as a microprocessor. At this time, the one circuit unit is operated using the internal clock signal (ICLK1) synchronized with the second clock signal generated by the clock pulse generator as the operation reference clock signal. The remaining circuit unit comprises the delay locked loop circuit.

When the data processing system includes a power management unit (5), the clock pulse generator can select the first and second clock signal frequencies from a plurality of frequencies, and the first and second clock signal frequencies can be selected. The power management unit receives an instruction to reduce both the clock signal frequencies of.

[0010]

According to the above means, the phase difference detecting means is the second
The delay control means detects the phase difference between the second clock signal (CLKs) passing through the clock input buffer and the internal clock signal (ICLK2s) passing through the variable delay means, and cancels the detected phase difference. The variable delay means is used to determine the delay time of the internal clock signal (ICLK2s). As a result, the phase of the internal clock signal (ICLK2s) is made equal to the phase of the clock signal (CLKs).
This state is kept constant even if the phases of the first clock signal (PCLK) and the second clock signal (CLK) are deviated within a range equal to or less than the phase difference detectable by the phase difference detection means. That is, the delay time set by the variable delay means keeps the locked state. In this regard, the delay locked loop circuit stabilizes the internal clock signal which is synchronized with the external clock signal. Further, when the first and second clock signal frequencies are changed (the mutual phase difference or the delay time is not changed), the phase difference detected by the phase difference detecting means is not changed, and the internal clock signal is A signal having a frequency that immediately follows the frequency change of the external clock signal. Since one of the comparison targets in the PLL circuit is an external clock signal and the other is an internal clock signal (feedback signal) reflecting the comparison result, a change in the frequency of the external clock signal causes a change in the internal control state of the PLL circuit. give. With these functions, the internal clock signal can be stabilized and synchronized with the external clock signal as in the PLL circuit, and when the frequency of the clock signal supplied from the outside is changed, it is not compared with the PLL circuit. The internal clock signal can be made to follow immediately.

[0011]

1 is an overall block diagram of a microcomputer system according to an embodiment of the present invention. In the same drawing, a single microprocessor 1 and peripheral circuits 2 and 3 each represented by a semiconductor integrated circuit are representatively shown, and they share an address bus ABUS and a data bus DBUS. In this embodiment, the microprocessor 1 has a built-in clock pulse generator 10, and the clock signals PCLK and CLK generated thereby are supplied to the peripheral circuits 2 and 3 via the clock wiring 4. The clock signal CLK (second clock signal) is the clock signal PCLK.
The clock signals have a frequency equal to that of the (first clock signal) and are mutually delayed in phase for a predetermined time.

The microprocessor 1 has an internal circuit 11 for performing arithmetic processing and external access control in synchronization with an internal clock signal ICLK1 which is substantially the same as the clock signal CLK. The peripheral circuits 2 and 3 have delay locked loop circuits 20 and 30, respectively. The delay locked loop circuits 20 and 30 generate internal clock signals ICLK2 and ICLK3 based on clock signals PCLK and CLK supplied from the outside. Internal clock signals ICLK2 and ICLK3 are stably synchronized with clock signal CLK by delay locked loop circuits 20 and 30, which will be described in detail later. The peripheral circuits 2 and 3 have internal circuits 21 and 31 which are operated in synchronization with the internal clock signals ICLK2 and ICLK3. For example, the peripheral circuits 2 and 3 are semiconductor memory devices, timer counters, coprocessors, etc. that are operated in synchronization with a clock signal. Although not shown, the internal circuit 11 of the microprocessor 1 has a program counter for holding an instruction address to be executed next,
It is provided with an instruction register to which instructions are transferred according to the value of the program counter, a status register in which the internal state of the microprocessor 1 is set, an arithmetic circuit, a control circuit, an input / output buffer and the like. The control circuit decodes the instruction fetched in the instruction register to generate a control signal necessary for sequentially executing the instructions, and from receiving the interrupt signal to shifting the instruction execution state to a predetermined interrupt processing program. The interrupt transition control is performed. The control logic for realizing them can employ microprogram control or wired logic, or a logic configuration using both in combination.

The microcomputer system of this embodiment further includes a power management unit unit 5. The power management unit unit 5 is not particularly limited, but may include the address bus ABUS and the data bus D.
The BUS change state and the internal state of the microprocessor 1 are monitored, and when the high-speed operation of the microprocessor 1 is not required due to no input / output operation for a certain period of time, the system clock signal frequency is lowered from the viewpoint of low power consumption. Is a circuit for controlling the clock pulse generator 10 by activating the control signal FLOW.
Instructing to lower the frequency of the clock signals PCLK and CLK. As a result, the clock pulse generator 10
Reduces the frequency of the clock signals CLK and PCLK. At this time, the phase difference between the clock signals PCLK and CLK or the delay time is not changed. When the control signal FLOW is turned to the inactive state, the clock signals CLK and PC
The frequency of LK is restored. Also at this time, the phase difference between the clock signals PCLK and CLK or the delay time is not changed. Although the details will be described later, the delay locked loop circuits 20 and 30 are connected to the internal clock signal ICLK2.
ICLK3 as such clock signals PCLK, CLK
The signal has a frequency that immediately follows the frequency change of.

In the microcomputer system of FIG. 1, the microprocessor 1 has a clock pulse generator 10
2, the clock pulse generator 10 is separated from the microprocessor 1 as shown in FIG. 2, and instead, a delay locked loop circuit 12 similar to the above is built in the microprocessor 1 to provide the delay locked loop. It is also possible to configure the microcomputer system to operate the internal circuit 11 in synchronization with the internal clock signal ICLK4 generated by the circuit 12. The same circuit components as those in FIG. 1 are designated by the same reference numerals.

The clock system in the above microcomputer system will be described in detail below.

A clock pulse generator 10 is shown in FIG.
An example is shown. The configuration shown in the figure is an example in which the microprocessor 1 is on-chip. The clock pulse generator 10 shown in the figure mainly includes a PLL circuit that multiplies the oscillation frequency of the crystal oscillation circuit 100. That is, the phase comparison circuit 101 includes the voltage controlled oscillator 1
The oscillation output of 02 detects the phase error between the signal input through the frequency divider 103 and the delay circuit 104 and the oscillation output from the crystal oscillation circuit 100, and the detected phase error voltage is voltage-controlled through the low-pass filter 106. The oscillator 102 is fed back, which allows the voltage controlled oscillator 102 to
Is multiplied by the oscillation frequency of the crystal oscillation circuit 100, and the phase of the output signal of the voltage controlled oscillator 102 is synchronized with the oscillation signal of the crystal oscillation circuit 100. In this embodiment, the output of the frequency divider 103 is a clock signal φ1 having a relatively large frequency division ratio and a clock signal φ2 having a relatively small frequency division ratio, one of which is the selection circuit 10.
It is selected via 7 and is output to the outside as a clock signal PCLK from the clock output buffer or the clock driver CDRV1. Further, the clock signals φ1,
φ2 is delayed by the delay circuits 104 and 105 respectively for a predetermined time, and one of the delayed clock signals is selected by the selection circuit 108.
Is output via the clock output buffer or the clock driver CDRV2 as the clock signal CLK to the outside. The internal clock signal is the selection circuit 108
The clock signal is generated based on the clock signal selected in step 1, and has substantially the same phase as the clock signal CLK. The selection circuits 107 and 108 control the control signal FLOW.
Signal φ2 and its delay circuit 10 in the inactive state of
The signal delayed by 5 is selected, and the signal φ1 and the signal delayed by the delay circuit 104 in the active state of the control signal FLOW are selected. As is apparent from the configuration of FIG. 3, when the state of the signal FLOW is inverted after the PLL operation by the clock pulse generator 10 is once stabilized, the clock signals CLK and PCLK have a mutual phase difference or delay time. Only the frequency is changed immediately without any change.

A clock pulse generator 10 is shown in FIG.
Another example of is shown. The configuration shown in the figure is an example separated from the microprocessor 1. The clock pulse generator 10 shown in FIG.
Mainly 0. The crystal oscillator circuit 110 is the crystal oscillator 1
It is a Colpitts oscillation circuit including 101 and inverter amplifiers 1102 and 1103. Each of the inverter amplifiers 1102 and 1103 is provided with negative feedback resistors 1104 and 1105 for giving linearity to the input / output characteristics between the input and output of the CMOS inverter, and operates as an inverting amplifier circuit. This inverter amplifier 11
The crystal oscillator 1101 is connected between the input terminal of the oscillator 02 and the output terminal of the inverter amplifier 1103 to form an oscillation circuit that transmits at a frequency corresponding to the natural frequency of the oscillator 1101. Reference numeral 1106 denotes a load capacitor arranged between the ground potential Vss and the vibrator 1101. The frequency divider 111 divides the oscillation signal obtained by the crystal oscillation circuit 110. The selection circuit 112 composed of two AND gates selects either the output of the frequency divider 111 or the oscillation output of the crystal oscillator 110 by the control signal FLOW. The selected signal is output as a clock signal PCLK to the outside via the clock output buffer or the clock driver CDRV4 on the one hand, and delayed by the delay circuit 113 on the other side to the clock signal to the outside via the clock output buffer or the clock driver CDRV5. It is output as CLK. Delay circuit 113
Can be configured by a series circuit of even-numbered inverters.
The selection circuit 112 selects the output signal of the frequency divider 111 in the active state of the control signal FLOW, and outputs the control signal FLOW.
In the inactive state, the output signal of the crystal oscillation circuit 110 is selected. As is clear from the configuration of FIG. 4, the control signal F
When the LOW state is inverted, the clock signals CLK and P
CLK does not change in mutual phase difference or delay time,
Only the frequency is changed immediately.

FIG. 5 shows an example of the delay locked loop circuit. The delay locked loop circuit 20 shown in the figure compares the phase difference between the output clock signal CLKs of the clock input buffer 22 which receives the clock signal CLK and one internal clock signal ICLK2s by the phase comparison circuit 24, and detects it. The delay time by the variable delay circuit 23 is controlled by the binary counter 25 and the decoder 26 so as to cancel the generated phase difference. The variable delay circuit 23 delays the clock signal PCLK received by the clock input buffer 21. Internal clock signal ICLK2
Is generated by receiving the output clock signal of the variable delay circuit 23 by the clock driver CDRV6. In FIG. 5, P0
P7 is a group of terminals for supplying preset data to the binary counter 25 in parallel. The states of the terminal groups P0 to P7 can be set programmable so that arbitrary preset data can be supplied by pulling up or pulling down individual terminals. The preset operation of the binary counter 25 is performed in response to the reset of the microcomputer system. After the preset operation, the binary counter 25 counts up (+) in synchronization with the falling change of the up signal UP from the phase comparison circuit 24.
1) is performed, and the down count (-1) is performed in synchronization with the falling change of the down signal DOWN. The decoder 26 decodes the count value of the binary counter 25. The variable delay circuit selects one delay time selected by the decode output from the decoder 26 to select the clock input buffer 2
Delay the output of 1.

FIG. 6 shows an example of the variable delay circuit 23. The variable delay circuit 23 shown in the figure selects one delay time from eight kinds of delay times. Each delay time is determined by the delay element DLY. D of each delay element
The output of LY is output to the decoder 26 via the AND gate AND.
Are selected by the decode outputs S0 to S7. In this embodiment, the binary counter 25 has 3 bits.

FIG. 7 shows an example of a logic circuit diagram of the phase comparison circuit 24. The clock signal ICLK2s is applied to one input of the 2-input NAND gate 241, and the clock signal CLKs is applied to one input of the 2-input NAND gate 246. Two-input NAND gates 242 and 243 form a flip-flop, and two-input NAND gates 244 and 245 form a flip-flop. The logical output of the 2-input NAND gate 241 is input to one input terminal of the NAND gate 242 as a set signal of the flip-flop. Also, Nand Gate 2
The logic output of 46 is input to one input terminal of the NAND gate 245 as a set signal of the flip-flop. The logic output of the 4-input NAND gate 247 is used for resetting the flip-flop. The output of the flip-flop and the output signals of the 2-input NAND gates 241 and 246 are input to the 4-input NAND gate 247 in the subsequent stage,
Further, it is adapted to be inputted to the 3-input NAND gates 248 and 249. Output signal UP of NAND gate 248
Is a control signal for increasing the delay time in the variable delay circuit 23, and conversely, the output signal DOWN of the 3-input NAND gate 249 is for decreasing the delay time in the variable delay circuit 23. It is used as a control signal. The logic output of the NAND gate 248 is fed back to the other input terminal of the NAND gate 241, and similarly, the logic output of the NAND gate 249 is fed back to the other input terminal of the NAND gate 246, so that the signals UP and DOWN are low. The time to level, ie the pulse width, is determined.

Since the phase comparison circuit 24 of FIG. 7 includes a flip-flop, the output is determined by the state of the previous data. First, with respect to the input signal ICLK2s, the signal CLKs
, The time from the fall of the signal CLKs to the fall of the ICLK2s (the signal CLKs
And a signal ICLK2s corresponding to the phase difference), the down signal DOWN is set to low level and the up signal UP is increased.
Keeps high level. Conversely, if the phase of the signal ICLK2s leads the input signal CLKs, the signal ICLK2s
The up signal UP is set to the low level and the down signal DOWN is maintained at the high level only during the time from the falling edge of CLK2s to the falling edge of CLKs. When the falling edges of the signal CLKs and the signal ICLK2s coincide with each other, both the up signal UP and the down signal DOWN maintain the high level. As a result, the output UP indicating the lead and lag of the phase,
DOWN is obtained.

FIG. 8 shows the operation timing of the phase comparison circuit 24. When the phases of the signals ICLKs and CLKs are completely the same, there is no need to adjust the delay time, so the output control signal U of the phase comparison circuit 102 concerned.
Both P and DOWN are in a high level state.
However, when the phase of the signal ICLK2s is advanced with respect to the signal CLKs, it is necessary to delay it. Therefore, the negative AND condition in the NAND gate 248 is satisfied at the timing of the logic mismatch between the signals ICLK2s and CLKs. This causes its output signal UP to go low. When the phase of the signal ICLK2s is delayed with respect to the signal CLKs, it is necessary to advance it. Therefore, the negative logical product condition in the NAND gate 249 is satisfied at the timing of the logic mismatch between the signals ICLK2s and CLKs, so that Output control signal DOWN is set to a low level.

The delay time correction and holding operation by the delay locked loop circuit 20 will be described with reference to FIGS. The value preset in the binary counter 25 in response to the reset of the microcomputer is substantially the center value of the countable range of the counter 25. In this embodiment, the binary counter 25 is a 3-bit counter, for example, the preset value is "011". Therefore, of the decode outputs S0 to S7 by the decoder 26 immediately after the binary counter 25 is preset,
S3 is set to the selection level, and the delay element DLY to the other input of the AND gate AND1 which receives it at one input
The variable delay circuit 23 outputs a clock signal delayed by a delay time td2 determined by the number of stages.
The delay time td2 is the delay circuit 104, 105 or 11
The delay time is determined in advance so as to be equal to the delay time td1 of 3. In other words, the delay time obtained by each delay element DLY and the delay element DLY so that the delay time td2 matches the delay time td1.
And the number of steps is determined. Such delay time td2
May be subject to fluctuations that cannot be ignored due to process variations.

FIG. 9 shows clock signals CLKs and ICL when the decode output S3 is at the selection level.
The state is shown when the phases of Ks are matched. In this state, td1 = td2.

In FIG. 10, the clock signal ICLK2s
Is initially delayed from CLKs. The cause thereof is due to, for example, process variation of the peripheral circuit incorporating the delay locked loop circuit, and generation of an undesired skew (phase error) between the clock signals CLK and PCLK supplied to the delay locked loop circuit 20. To do. When this state is detected by the phase comparison circuit 24, the up signal UP is changed to the low level. As a result, the binary counter 25 counts up, the phase difference between the signals CLKs and ICLK2s is gradually reduced, and finally. When td3 = td2 + taj1 = td1, the signals ICLK2s and CLKs have the same phase.

In FIG. 11, the clock signal ICLK2s is used.
Is first advanced from CLKs. The cause is the same as in the case of FIG. 10, for example. When this state is detected by the phase comparison circuit 24, the down signal DOWN
As a result of N being changed to the low level, the binary counter 2
5 counts down and signals CLKs and ICLK2
The phase difference with s is gradually reduced, and finally td3 = td2
When -taj2 = td1, the signal ICLK2
s and CLKs have the same phase.

Here, the delay locked loop circuit 20
The reference of the phase comparison in is the clock signal CLK given from the outside. At first glance, the clock signal C
It may be considered that the clock signal CLKs obtained by receiving LK in the clock input buffer 22 can be used as it is for the generation of the internal clock ICLK2. However, the delay locked loop circuit 20 delays the input signal by a delay loop. It has a lock range to maintain. That is, even if the phases of the input signals CLK and PCLK fluctuate within a delay time width that can be set stepwise by the variable delay circuit 23, the precision of the phase comparison circuit is determined so as to ignore such slight fluctuations. Has been done. Since the delay locked loop circuit 20 has a lock range for such a delay loop, it is possible to stabilize the internal clock signal as compared with the case where the clock signal CLKs is directly used for generating the internal clock signal. In other words, the state in which the delay locked loop circuit 20 controls the phase of the internal clock signal ICLK2s to be equal to the phase of the clock signal CLKs is within a range less than the phase difference detectable by the phase comparison circuit 24. Even if the phase of CLK is undesirably shifted, it is kept constant, and
The delay time set in 3 is kept locked. In this regard, the delay locked loop circuit can stabilize the internal clock signal synchronized with the external clock signal.

FIG. 12 shows another example of the delay locked loop circuit. The delay-locked loop circuit 20 shown in the same figure has a charge pump circuit 27 for applying a DC potential corresponding to the phase difference detected by the phase comparison circuit 24.
Generate at. The DC potential generated by the charge pump circuit 27 is converted into a digital value by the A / D conversion circuit 28, and the digital value is held in the register 29 and given to the decoder 26. The A / D converter 28 is of a parallel comparison type. Although not shown, the charge pump circuit includes a CMOS inverter circuit, its P-channel type MOS transistor is controlled by an up signal UP, and its N-channel type MOS transistor is switch-controlled by an inverted signal of a down signal DOWN, An integrating circuit may be provided at the output of the CMOS inverter, and a DC potential may be formed thereby. In the example of FIG. 5, the initial value of the delay time is determined by presetting the binary counter 25, but in the case of FIG. 12, the output of the charge pump circuit may be initialized to a predetermined DC potential. Other points are the same as those in FIG. 5, and the same circuit elements as those are denoted by the same reference numerals and detailed description thereof will be omitted.

FIG. 13 shows the power management unit 5
FIG. 6 is a timing chart showing the operating characteristics of the delay locked loop circuit 20 when the frequencies of the clock signals CLK and PCLK are reduced by the instruction from FIG. Clock signal PCL in clock pulse generator 10
A phase difference corresponding to the delay time td1 is given to K and CLK and supplied to the clock wiring 4. The delay locked loop circuit 20 has its clock signals PCLK and CLK.
Are received by the clock input buffers 21 and 22. In FIG. 13, for convenience, the phases of the clock signals PCLKs and CLKs output from the clock input buffers 21 and 22 are illustrated as being the same as the clock signals PCLK and CLK. Before the time ti, the delay locked loop circuit 20 controls the delay time correction and holding operation so that the phases of the internal clock signals ICLK2 and ICLK2s coincide with the phase of the clock signal CLKs.
When a frequency reduction command is given to the clock pulse generator 10 by the control signal FLOW from the power management unit 5 at time ti, the clock signal PCL
The frequencies of K and CLK are reduced. As is clear from the description of FIGS. 3 and 4, the frequency of the clock signals PCLK and CLK is reduced by the operation of selecting its output path, and therefore the clock signal waveform does not substantially disturb. Even if the frequency is reduced, the delay time td1 is maintained as it is. Therefore, the clock signals PCLK, C
When the frequency of LK is changed (the mutual phase difference or the delay time is not changed), the phase difference detected by the phase comparison circuit 24 does not change, and the internal clock signal ICLK
2, ICLK2s is such an external clock signal PCL
The signal has a frequency that immediately follows the frequency changes of K and CLK. Since one of the comparison targets in the PLL circuit is an external clock signal and the other is an internal clock signal (feedback signal) reflecting the comparison result, a change in the frequency of the external clock signal causes a change in the internal control state of the PLL circuit. It takes a few hundred cycles of settling time for the synchronization to stabilize.

As is clear from the above description, the clock signal P having the same frequency and a constant phase difference (delay time).
CLK and CLK are used as master clock signals, and the peripheral circuits receive them by the delay locked loop circuit 20 to use internal clock signals ICLK2 and ICLK2s synchronized with the clock signal CLK as internal operation reference clock signals. The delay time set in the variable delay circuit 23 by the phase difference detected by the phase comparison circuit 24 is the input clock signals CLK and PCLK after that.
Of the internal clock signals ICLK2 and ICLK2s can be stably synchronized with the clock signal CLK (the same function as the PLL circuit in terms of stabilizing the synchronization). In addition, when the frequency of the clock signal supplied from the outside is changed, the internal clock signal can be made to follow so quickly that it cannot be compared with the PLL circuit. The other delay locked loop circuits 12 and 30 have the same configuration and operation as the delay locked loop circuit 20 described above as a representative.

FIG. 14 is a block diagram of a synchronous SRAM (static random access memory) as an example of the peripheral circuit 2. The synchronous SRAM shown in the figure is used for, for example, a cache memory, and has 32-bit data D0 to D0.
D31 can be input / output in parallel, and 15-bit address signals A0 to A14 are supplied. ADV is an enable signal for an internal address update operation for the burst operation, ADSC is an access instruction signal from a memory controller (not shown), and BW0 to BW3 indicate a write target byte for 32-bit data for one entry. CE1, CE2, CE are three chip enable signals. OE is an output enable signal, ADSP is an access instruction signal from the microprocessor, and these are access control signals supplied from the outside. The address signals A0 to A14 are held by the address input register AIR. The latch timing by the register AIR is AND gates AND13, AND11,
And the signals ADSP and C via the OR gate OR10.
E2, Follow the instructions given by ADSC. When the address signal at this time is the address signal for the write operation, the signals BW0 to BW3 designating the write target byte are synchronized with the internal clock signal ICLK2 via the OR gates OR11 to OR14 of the byte write registers BWR0 to BWR3. Latched. A write instruction by the signal ADSP is collectively issued to the byte write registers BWR0 to BWR3.
Latched on. Write data is internal clock signal IC
It is latched in the data input register DIR in synchronization with LK2. The write data is supplied to the byte write drivers BWD0 to BWD for each byte. In the byte write drivers BWD0 to BWD, the corresponding byte write registers BWR0 to BWR3 hold the write enable data and the enable register ER sets the enable level. When the data is held, the data from the data input register DIR can be input. Data output register DOR
All the byte write registers BWR0 to BWR3 hold disable data and enable register E
When R holds the enable level and the output is enabled by the OE signal, the memory block MBL
The read data from K can be output. COUNT
Is a 2-bit binary counter, AND gate A
The clock signal output from the ND 10 is counted, and the timing of the counting operation is given by the output of the AND gate AND11. The count value of the counter COUNT corresponds to bits and is a 2-input type exclusive OR gate EOR.
1 and EOR2 are supplied to one input. Of the address signals A0 to A14 output from the address input register AIR, the least significant 2 bits A0 and A1 are supplied to the other inputs of the exclusive OR gates EOR1 and EOR2,
As a result, the least significant 2 bits of the memory address are signal A
It is sequentially updated according to the instruction of continuous memory access by the DSP or ADSC.

FIG. 15 shows an example of the memory block MBLK. The memory block MBLK includes a memory cell array MARY in which static memory cells MC are arranged in a matrix. In the memory cell MC, the selection terminal is connected to the word line WLi for each row, and the data input / output terminal is connected to the complementary data lines BLj, BLj * for each column.
In FIG. 15, the memory cell is of a high resistance load type, for example, and has a resistance element R and an N-channel type MOS transistor Q.
A pair of series circuits with 1 are provided between the power supply terminal Vdd and the ground terminal Vss, and the gate of one MOS transistor Q1 is mutually coupled to the drain of the other MOS transistor Q1 to form a static latch. Of the complementary data lines BLj, BLj * via the selection MOS transistor Q2 whose drain is N-channel type.
And the gate of the selection MOS transistor Q2 is connected to the word line WLi. Complementary data line BL
A data line load transistor Q3 whose switch is controlled by a control signal φ is coupled to one end of each of j and BLj *.
The other ends of the complementary data lines BLj, BLj * are coupled to the complementary common data line CD via a column switch transistor forming a column switch circuit CSW. According to this embodiment, 32 pairs of complementary common data CD lines are provided.
A row address decoder RADE is used to select each word line.
This is performed based on the C decoded output. The selection of the complementary data lines to be conducted to the 32 pairs of complementary common data lines CD is performed by the decode signal by the column address decoder CADEC. The data read as the complementary common data CD is applied to the data output register DOR via a read circuit RC including a sense amplifier. The write data from the byte write drivers BWD0 to BWD3 is given to the complementary common data line CD via the write circuit WC.

FIG. 16 is an operation timing chart of single read (simple read) and burst read (continuous read) in the synchronous SRAM. The synchronous SRAM exchanges data with the microprocessor in synchronization with the rising edge of the clock signal CLK. Therefore, the timing design of the rise timing of the clock signal CLK and the setup time and hold time of the data, address signal, and control signal is a major factor that influences the characteristics of the entire system. Therefore, it is ideal that the clock signal CLK and the internal clock signal ICLK2 have the same phase. Synchronous SRAM is an internal clock signal IC
It operates on the basis of fetching information to the register in synchronization with the rising edge of LK2 and controlling the information output from the register. The first operation of FIG. 16 is a single read, and the low state of the signals ADSP and CE1 and the address signal are taken into the register at the rising edge of the clock signal PCLK2, whereby the read operation is performed. As a result, the data is read from the memory array MARY and transferred to the output register DOR. In this example, the microprocessor takes in data in synchronization with the next rising edge of the clock. ADS for continuous reading
When C and CE1 are at the low level and BWi is at the high level, the address signal is taken in and the read mode is set. Similar to the single reading, data is exchanged with the microprocessor in synchronization with the rising edge of the clock signal. The difference from the single read is that when the signal ADV is at a low level, the binary counter performs a counting operation in response to the rising change of the clock signal, and the data of the next address designated by the binary counter is read from the memory array. As a result, the data reading is sequentially performed four times. In FIG. 16, the clock signal frequency is reduced to about half during the burst read. Due to the operation of the delay locked loop circuit 20, the clock signal CL
Even if the frequencies of K and PCLK are changed, synchronous S
Since the internal clock signal ICLK2 of the RAM immediately follows the change, the burst read operation is not interrupted on the way.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. Yes. For example,
The settable range of the delay time by the variable delay means is not limited to eight stages as in the embodiment, and can be changed as appropriate. Further, the peripheral circuit is not limited to the synchronous SRAM, and can be changed to various clock synchronous type semiconductor integrated circuits such as other clock synchronous type memories, timer counters and coprocessors.

[0035]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

In other words, the phase difference detecting means receives the second clock signal (CLK) that has passed through the second clock input buffer.
s) and the internal clock signal (ICL) that has passed through the variable delay means.
K2s), and the delay control means determines the delay time of the internal clock signal (ICLK2s) by using the variable delay means so as to cancel the detected phase difference.
The phase of the internal clock signal (ICLK2s) is changed to the second clock signal (C) that has passed through the second clock input buffer.
LKs) phase. Then, this state is maintained constant even if the phases of the first clock signal (PCLK) and the second clock signal (CLK) are undesirably deviated within a range equal to or less than the phase difference detectable by the phase difference detection means. It That is, the delay time set by the variable delay means can be kept in the locked state. Therefore, the delay locked loop circuit can stabilize the internal clock signal synchronized with the external clock signal. When the first and second clock signal frequencies are changed (the mutual phase difference or delay time is not changed),
There is no change in the phase difference detected by the phase difference detecting means, and the internal clock signal can be a signal having a frequency that immediately follows the frequency change of the external clock signal.
As described above, the internal clock signal can be stabilized and synchronized with the external clock signal as in the PLL circuit,
Moreover, there is an effect that when the frequency of the clock signal supplied from the outside is changed, the internal clock signal can be tracked so quickly that it cannot be compared with the PLL circuit. As a result, it is possible to realize a data processing system capable of shortening the idle period of the system operation by switching the clock signal frequency of the system.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a microcomputer system in which a clock pulse generator is incorporated in a microprocessor.

FIG. 2 is a block diagram of an embodiment of a microcomputer system in which a clock pulse generator is separated from a microprocessor 1.

FIG. 3 is a block diagram of a clock pulse generator using a PLL circuit.

FIG. 4 is a block diagram of a clock pulse generator that does not use a PLL circuit.

FIG. 5 is a block diagram of an example of the delay locked loop circuit.

FIG. 6 is a logic circuit diagram of an example of a variable delay circuit.

FIG. 7 is a logic circuit diagram of an example of a phase comparison circuit.

FIG. 8 is an operation timing chart of an example of a phase comparison circuit.

FIG. 9 shows clock signals CLKs and ICLKs as a lock operation of a delay loop by a delay locked loop circuit.
FIG. 4 is an explanatory diagram showing an operating state when the phases are matched.

FIG. 10 is an explanatory diagram showing an operating state when the phase of the clock signal ICLK2s is first delayed from CLKs as the lock operation of the delay loop by the delay locked loop circuit.

FIG. 11 is an explanatory diagram showing an operation state when the phase of the clock signal ICLK2s is first advanced from CLKs as the lock operation of the delay loop by the delay locked loop circuit.

FIG. 12 is a block diagram showing another example of a delay locked loop circuit.

FIG. 13 is a timing chart showing operation characteristics of the delay locked loop circuit when the frequencies of the clock signals CLK and PCLK are lowered by an instruction from the power management unit.

FIG. 14 is a synchronous SRAM which is an example of a peripheral circuit.
2 is an overall block diagram of FIG.

FIG. 15 is an explanatory diagram showing an example of a memory block of a synchronous SRAM.

FIG. 16 is an operation timing chart of single read and burst read in the synchronous SRAM.

[Explanation of symbols]

1 Microprocessor 10 Clock Pulse Generator 11 Internal Circuit 12 Delay Locked Loop Circuit 2, 3 Peripheral Circuit 20, 30 Delay Locked Loop Circuit 21 Clock Input Buffer 22 Clock Input Buffer 23 Variable Delay Circuit 24 Phase Comparison Circuit 25 Binary Counter 26 Decoder 27 Charge Pump circuit 28 A / D converter 29 Register 5 Power management unit CLK Clock signal PCLK Clock signal ICLK1, ICLK2, ICLK3, ICLK4 Internal clock signal DBUS Data bus ABUS Address bus

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazumasa Yanagisawa 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Division (72) Inventor Koichiro Ishibashi 1-280, Higashi Koikeku, Kokubunji, Tokyo Address Hitachi, Ltd. Central Research Laboratory (72) Inventor Yoshitaka Kinoshita 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Division (72) Inventor Sadayuki Morita 5 Mizumizuhoncho, Kodaira-shi, Tokyo Inc. 20-21 Hitachi Ultra S.I.Engineering Co., Ltd. (72) Inventor Kiyoshi Nagai 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Division (56) Reference Documents JP-A-4-140812 (JP, A) JP-A-4-364609 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) G 06F 1/10 G06F 1/08 G06F 1/12

Claims (6)

(57) [Claims]
1. A clock pulse generator for generating a first clock signal and a second clock signal having a frequency equal to the frequency of the first clock signal and having phases mutually delayed by a certain time, the clock pulse generator being provided. A data processing system in which a plurality of circuit units each integrated into a semiconductor integrated circuit, which are operated in synchronization with each other in response to a first clock signal and a second clock signal, share a bus.
And a delay locked loop circuit that receives the second clock signal to form an internal clock signal, the delay locked loop circuit including a first clock input buffer that receives the first clock signal and a second clock signal. A second clock input buffer for receiving; variable delay means for variably delaying an output clock signal of the first clock input buffer to form an internal clock signal; and an output from the internal clock signal and the second clock input buffer Phase difference detecting means for detecting a phase difference with the clock signal to be generated, and an up-converter according to the detection result of the phase difference detecting means
A counter that counts down or down
Based on the count output of the counter
Therefore, the variable delay is set to cancel the detected phase difference.
Generate a control signal that can control the delay time by the delay means
For the variable delay means,
Selected by the control signal generated by the decoder
A delay time is selected to select the first clock input buffer.
Control logic to delay the output clock signal of the
Data processing system, characterized in that comprised comprise.
2. A plurality of circuit units each made into a semiconductor integrated circuit share a bus, and one circuit unit mutually has a first clock signal and a frequency equal to the frequency of the first clock signal. Second phase delayed by a certain time
And a clock pulse generator for generating a clock signal of the second clock signal, and an internal clock signal synchronized with the second clock signal is operated as an operation reference clock signal.
Delay locked loop circuit for receiving an internal clock signal from the delay locked loop circuit, the delay locked loop circuit including a first clock input buffer for receiving a first clock signal and a second clock input buffer for receiving a second clock signal. Clock input buffer, variable delay means for variably delaying the output clock signal of the first clock input buffer to form an internal clock signal, and clocks output from the internal clock signal and the second clock input buffer. phase difference detection means for detecting a phase difference between the signals, before
Depending on the detection result of the phase difference detection means
Is a counter that counts down and the counter
Detected by the phase difference detection means based on the output
In the variable delay means so as to cancel out the phase difference issued.
To generate a control signal whose delay time can be controlled by
A coder, wherein the variable delay means is the decoder
One delay selected by the control signal generated by
Select an extended time to output the first clock input buffer.
A data processing system comprising control logic for delaying a power clock signal .
3. The data processing system according to claim 2, wherein the one circuit unit is a microprocessor.
4. The clock pulse generator is capable of selecting both the first and second clock signal frequencies from a plurality of frequencies, and selects the first and second clock signal frequencies output by the clock pulse generator. 4. The data processing system according to claim 1, further comprising a power management unit that gives an instruction to reduce both.
5. A delay lock for forming an internal clock signal by receiving a first clock signal and a second clock signal having a frequency equal to that of the first clock signal and having phases mutually delayed by a predetermined time. Equipped with a droop circuit,
A semiconductor integrated circuit that operates in synchronization with the internal clock signal, wherein the delay locked loop circuit includes a first clock input buffer for receiving a first clock signal,
A second clock input buffer for receiving a second clock signal; variable delay means for variably delaying an output clock signal of the first clock input buffer to form an internal clock signal; phase difference detection means for detecting a phase difference between the clock signal output from the clock input buffer, detection of the phase difference detecting means
Count up or down depending on the result
Based on the counter and the count output of the counter,
Cancels the phase difference detected by the phase difference detecting means.
The delay time can be controlled by the variable delay means so that
A decoder for generating various control signals ,
The variable delay means is a control generated by the decoder.
Select one delay time selected by the signal and
Delay the output clock signal of 1 clock input buffer
A semiconductor integrated circuit characterized in that it comprises a control logic for controlling .
6. A delay lock for forming an internal clock signal by receiving a first clock signal and a second clock signal having a frequency equal to the frequency of the first clock signal and having phases mutually delayed by a predetermined time. Equipped with a droop circuit,
A semiconductor integrated circuit that operates in synchronization with the internal clock signal, wherein the delay locked loop circuit includes a first clock input buffer for receiving a first clock signal,
A second clock input buffer for receiving a second clock signal; variable delay means for variably delaying an output clock signal of the first clock input buffer to form an internal clock signal; Phase difference detecting means for detecting a phase difference with a clock signal output from the clock input buffer, a charge pump circuit for generating a direct current according to the detection result of the phase difference detecting means, and the charge pump circuit. A / D conversion circuit for converting the output signal of the digital signal into a digital value, a register capable of holding the digital value output from the A / D conversion circuit, and the phase difference detection means based on the output of the register. For generating a control signal capable of controlling the delay time by the variable delay means so as to cancel the phase difference detected by Control logic for delaying the output clock signal of the first clock input buffer by selecting one delay time selected by the control signal generated by the decoder. A semiconductor integrated circuit comprising:
JP17817095A 1995-06-21 1995-06-21 Data processing system and semiconductor integrated circuit Expired - Fee Related JP3479389B2 (en)

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JP4199473B2 (en) 2002-04-03 2008-12-17 株式会社ルネサステクノロジ Synchronous clock phase control circuit
KR100477809B1 (en) 2002-05-21 2005-03-21 주식회사 하이닉스반도체 Digital dll apparatus for correcting duty cycle and method thereof
JP4328319B2 (en) 2005-08-02 2009-09-09 富士通マイクロエレクトロニクス株式会社 Clock supply circuit
US20110050297A1 (en) * 2009-08-28 2011-03-03 Nel Frequency Controls, Inc. System employing synchronized crystal oscillator-based clock
JP6445286B2 (en) * 2014-09-08 2018-12-26 旭化成エレクトロニクス株式会社 Phase detector, phase adjustment circuit, receiver and transmitter

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