JP3876145B2 - Subtraction circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a subtraction circuit that calculates a voltage difference between two input signals.
[0002]
[Prior art]
FIG. 4 is a configuration circuit diagram of an example of a conventional subtraction circuit.
The subtracting circuit 30 shown in FIG. 2 calculates a voltage difference between the signal v1 and the signal v2, amplifies and outputs the signal VOUT, and is an N-type MOS transistor (hereinafter referred to as NMOS) for sampling the signals v1 and v2. ) 14a, 14b and holding capacitances 16a, 16b, an operational amplifier 18, NMOSs 20, 28, and a capacitance 22.
[0003]
Here, the NMOSs 14a and 14b are respectively connected between the signals v1 and v2 and the terminals on the left side of the capacitances 16a and 16b, and the terminals on the right side of the capacitances 16a and 16b are the negative terminal of the operational amplifier 18 and Connected to the + terminal. An NMOS 20 and a capacitance 22 are connected in parallel between the negative terminal and the output terminal of the operational amplifier 18. The NMOS 28 is connected between the terminals on the left side of the capacitances 16a and 16b in the drawing.
[0004]
The sampling clock φ1 is input to the gates of the NMOSs 14a, 14b, and 20, and the inverted clock φ2 of the sampling clock φ1 is input to the gate of the NMOS 28. The + terminal of the operational amplifier 18 is virtually grounded. In the following description, the capacitances of the capacitances 16a, 16b, and 22 are C1, C2, and C3, respectively.
[0005]
First, the NMOSs 14a, 14b, and 20 are turned on and the NMOS 28 is turned off while the sampling clock φ1 is at a high level, that is, the inverted clock φ2 is at a low level. At this time, the capacitances 16a and 16b are charged up to the voltages of the signals v1 and v2 through the NMOSs 14a and 14b, respectively, and the charge amounts are Q1 = C1 · v1 and Q2 = C2 · v2, respectively. Further, since both ends of the capacitance 22 have the same potential of 0 V, Q3 = 0.
[0006]
Subsequently, the NMOSs 14a, 14b, and 20 are turned off and the NMOS 28 is turned on while the sampling clock φ1 is at a low level, that is, the inverted clock φ2 is at a high level. At this time, the terminals on the left side of the capacitances 16a and 16b are short-circuited via the NMOS 28 and become v3 of the same potential. Thereby, the charge amounts of the capacitances 16a and 16b are Q1 ′ = C1 · v3 and Q2 ′ = C2 · v3, respectively.
[0007]
Since Q1 + Q2 = Q1 ′ + Q2 ′, C1 · v1 + C2 · v2 = C1 · v3 + C2 · v3, and thus v3 = (C1 · v1 + C2 · v2) / (C1 + C2). As described above, since Q1 ′ = C1 · v3, Q1 ′ = C1 · (C1 · v1 + C2 · v2) / (C1 + C2), and VOUT = (Q1−Q1 ′) / C3 = (C1 · v1) −C1 · (C1 · v1 + C2 · v2) / (C1 + C2)) / C3.
[0008]
Here, if C1 = C2 = C, VOUT = ((v1−v2) / 2) · C / C3, and the subtraction circuit 30 calculates a voltage difference between the signal v1 and the signal v2.
[0009]
By the way, the subtraction circuit 30 in the illustrated example has a capacitance 16a and a capacitance 22 connected in series in terms of structure.
[0010]
Therefore, when a relatively large load is not connected to the output terminal of the operational amplifier 18, as conceptually shown in FIG. 5, the sampling clock φ1 is in a high level, that is, the sampling period of the signals v1 and v2. In addition, there is a problem that the signal v1 leaks to the output VOUT side at a high frequency, and the calculation accuracy of the calculation circuit 30 is lowered.
[0011]
On the other hand, if a large load is connected to the output terminal of the operational amplifier 18, the high frequency component of the signal v <b> 1 can be absorbed and subtraction processing can be performed with high accuracy. When a large load is connected, there is a problem that the subtraction process cannot be performed at high speed.
[0012]
[Problems to be solved by the invention]
An object of the present invention is to provide a subtracting circuit that can solve the problems based on the prior art and perform subtraction processing with high accuracy and high speed.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides first and second switch elements for sampling first and second signals, respectively, and first and second switch elements sampled by the first and second switch elements, respectively. The first and second capacitive elements for holding the second and second signals, respectively, and the first and second input terminals are respectively connected to one terminal of the first and second capacitive elements, and the second An operational amplifier whose input terminal is virtually grounded, a third switch element and a third capacitive element connected in parallel between the output terminal of the operational amplifier and the first input terminal, and an output terminal of the operational amplifier A fourth switch element and a fourth capacitor element connected in series with the ground, and a fifth switch element connected between the other terminals of the first and second capacitor elements. And an element,
The first, second, third and fourth switching elements are turned on in synchronization with a sampling clock, and the fifth switching element is turned on in synchronization with an inverted clock of the sampling clock. A circuit is provided.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
In the following, the subtraction circuit of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.
[0015]
FIG. 1 is a configuration circuit diagram of an embodiment of a subtraction circuit of the present invention.
A subtracting circuit 10 shown in FIG. 1 amplifies and outputs a signal having a voltage difference between two signals v1 and v2 supplied from signal sources 12a and 12b, respectively, and is an N-type MOS transistor (hereinafter referred to as NMOS). 14a, 14b, 20, 24, 28, capacitances 16a, 16b, 22, 26, and an operational amplifier 18 are provided.
[0016]
The difference between the subtraction circuit 10 of the present invention shown in FIG. 1 and the conventional subtraction circuit 30 shown in FIG. 4 is that an NMOS 24 and a capacitance 26 are connected in series between the output terminal of the operational amplifier 18 and the ground. Only. Therefore, in the subtraction circuit 10 shown in FIG. 1, the same components as those of the subtraction circuit 30 shown in FIG.
[0017]
The signal sources 12a and 12b conceptually show the means for generating the two signals v1 and v2 supplied to the subtraction circuit 10, and the left terminal in the figure is connected to the ground. The signals v1 and v2 may be AC signals such as sine waves (sine waves) or DC signals. Further, the frequency and amplitude of the signals v1 and v2 are not limited at all.
[0018]
In the subtracting circuit 10 of the illustrated example, NMOSs 14a and 14b are switching elements for sampling the signals v1 and v2, respectively. The terminals on the right side of the signal sources 12a and 12b and the left side of the capacitances 16a and 16b, respectively. It is connected between the terminals.
[0019]
In the following, the capacitances 16a and 16b are capacitive elements that hold the voltages of the signals v1 and v2 sampled by the NMOSs 14a and 14b, respectively.
[0020]
The operational amplifier 18 amplifies and outputs a signal VOUT having a voltage difference between the voltages held by the capacitances 16a and 16b. The negative terminal and the positive terminal are respectively connected to the terminals on the right side of the capacitances 16a and 16b. ing. The + terminal of the operational amplifier 18 is virtually grounded in the same manner as the subtracting circuit 30 shown in FIG.
[0021]
Further, the capacitance 22 holds the voltage difference between the voltages held by the capacitances 16 a and 16 b, and is connected in parallel with the NMOS 20 between the output terminal and the − terminal of the operational amplifier 18. As described above, the NMOS 24 and the capacitance 26 are connected in series between the output terminal of the operational amplifier 18 and the ground. The NMOS 28 is connected between the terminals on the left side of the capacitances 16a and 16b in the drawing.
[0022]
The sampling clock φ1 is input to the gates of the NMOSs 14a, 14b, 20, and 24. The NMOSs 14a, 14b, 20, and 24 are turned on when the sampling clock φ1 is at a high level and turned off when the sampling clock φ1 is at a low level. . The inverted clock φ2 of the sampling clock φ1 is input to the gate of the NMOS 28, and the NMOS 28 is turned on when the inverted clock φ2 is at a high level and turned off when the inverted clock φ2 is at a low level.
[0023]
In the following description, the capacitances of the capacitances 16a, 16b, 22, and 26 are C1, C2, C3, and C4, respectively.
[0024]
Since the basic operation of the subtraction circuit 10 is the same as that of the subtraction circuit 30 shown in FIG. 4, only the parts different from the subtraction circuit 30 will be described in the following description.
[0025]
First, the NMOSs 14a, 14b, 20, and 24 are turned on and the NMOS 28 is turned off while the sampling clock φ1 is at a high level, that is, the inverted clock φ2 is at a low level.
[0026]
At this time, the capacitance 26 is electrically connected to the output terminal of the operational amplifier 18 via the NMOS 24. In the subtraction circuit 10 of this structure, the phenomenon that the high frequency component of the signal v1 leaks to the output terminal side of the operational amplifier 18 through the capacitances 16a and 22 occurs as described in the description of the prior art. is there. However, in the subtraction circuit 10 of the present invention, the high frequency component of the signal v1 is absorbed by the capacitance 26, so that the subtraction process can be performed with high accuracy.
[0027]
Subsequently, the NMOSs 14a, 14b, 20, and 24 are turned off and the NMOS 28 is turned on while the sampling clock φ1 is at a low level, that is, the inverted clock φ2 is at a high level.
[0028]
At this time, the capacitance 26 is electrically disconnected from the output terminal of the operational amplifier 18 by the NMOS 24 turned off. Therefore, after the sampling period, the subtraction process can be performed at high speed.
[0029]
Here, as shown in FIG. 2, the gain (gain) (dB) of the output signal VOUT of the operational amplifier 18 when the signals v1 and v2 are input to the subtraction circuit 10 via LPFs (low pass filters) 28a and 28b. And the frequency (f) is shown in the graph of FIG. As shown in this graph, in the conventional subtraction circuit 30, the gain rapidly increases in the high range, whereas in the subtraction circuit 10 of the present invention, the increase in gain in the high range can be suppressed, and the accuracy is high. Subtraction processing can be performed.
[0030]
In the above-described embodiment, NMOS is used as the switch element. However, the present invention is not limited to this, and a P-type MOS transistor may be used, or other switch elements that perform the same function may be used.
[0031]
The subtraction circuit of the present invention is basically as described above.
The subtraction circuit of the present invention has been described in detail above. However, the present invention is not limited to the above-described embodiment, and various improvements and modifications may be made without departing from the gist of the present invention. .
[0032]
【The invention's effect】
As described above in detail, the subtraction circuit of the present invention includes the switch element and the capacitor element connected in series between the output terminal of the operational amplifier and the ground, and through the switch element during the signal sampling period. The capacitive element is electrically connected to the output terminal of the operational amplifier, and after the sampling period, the capacitive element is electrically disconnected from the output terminal of the operational amplifier.
Thereby, according to the subtraction circuit of the present invention, the high frequency component of the signal leaking to the output terminal side of the operational amplifier can be absorbed during the sampling period, and the subtraction process can be performed with high accuracy and high speed after the sampling period. .
[Brief description of the drawings]
FIG. 1 is a configuration circuit diagram of an embodiment of a subtraction circuit according to the present invention.
FIG. 2 is a configuration circuit diagram of another embodiment of the subtraction circuit of the present invention.
FIG. 3 is a graph showing an example of frequency characteristics of the subtraction circuit of the present invention and the conventional subtraction circuit.
FIG. 4 is a configuration circuit diagram of an example of a conventional subtraction circuit.
FIG. 5 is a conceptual diagram illustrating an example of an operation during sampling of a conventional subtraction circuit.
[Explanation of symbols]
10, 30 Subtraction circuit 12a, 12b Signal source 14a, 14b, 20, 24, 28 N-type MOS transistor 16a, 16b, 22, 26 Capacitance 28a, 28b LPF
18 Op-amp φ1 Sampling clock φ2 Inverted clock v1, v2, VOUT Signals C1, C2, C3, C4 Capacitance

Claims (1)

First and second switching elements for sampling the first and second signals, respectively, and first and second signals for holding the first and second signals respectively sampled by the first and second switching elements. An operational amplifier in which a second capacitive element, first and second input terminals are respectively connected to one terminal of the first and second capacitive elements, and the second input terminal is virtually grounded, and the operational amplifier A third switch element and a third capacitor connected in parallel between the output terminal of the operational amplifier and the first input terminal, and a fourth switch connected in series between the output terminal of the operational amplifier and the ground. Switch element and fourth capacitor element, and a fifth switch element connected between the other terminals of the first and second capacitor elements, the first, second, and third elements Preliminary fourth switch element is turned on in synchronization with the sampling clock, subtracting circuit the fifth switching element is characterized in that which is turned on synchronously with the inverted clock of the sampling clock.

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