KR101295190B1 - Switched capacitor operation amplifier - Google Patents

Abstract

The present invention relates to a switched capacitor operational amplifier, the present invention receives a clock (CLK) for the operation of the switched capacitor operational amplifier to generate a clock signal (PH1) (PH2), the rising of the clock signal (PH1) ( Or a clock generator 800 which performs the falling (or rising) transition of the clock signal PH2 at the same time so that the clock signals PH1 and PH2 are reversed to each other. The clock generator 800 receives a buffer 510 including two inverters to buffer the input clock CLK, and receives the output signal of the buffer 510 and outputs the clock signal PH1 through a NAND latch. A first clock generator 520 and a second clock generator 530 that receives an output signal of the buffer 510 and outputs a clock signal PH2 that is in phase with the clock signal PH1 through a NOR latch. . The present invention can generate an accurate clock by eliminating the delay error at the time of clock generation.

Description

Switched Capacitor Operational Amplifiers {SWITCHED CAPACITOR OPERATION AMPLIFIER}

TECHNICAL FIELD The present invention relates to circuits for signal processing, and more particularly, to switched capacitor operational amplifiers.

As digital technology advances, switched capacitor circuits are widely used to realize precision filters, A / D converters, and D / A converters as integrated circuits (ICs).

The switched capacitor circuit is precisely determined by a clock, and thus, when applied to a filter, the switched capacitor circuit is implemented to apply the correct clock even using expensive components.

1 illustrates an embodiment of a conventional clock generation circuit. As shown in FIG. 1, an inverter 130 for inverting the input clock CLK and a NAND gate 111 for generating a high level clock signal PH1 when the input clock CLK is low. The inverter 112, 113, and the NAND gate 121 and the inverter 122, 123 that generate a high level clock signal PH2 when the output signal of the inverter 130 is low.

The clock signal PH2 is applied to one terminal of the NAND gate 111, and the clock signal PH1 is applied to one terminal of the NAND gate 121.

Referring to the waveforms of FIG. 2 and FIG. 3 for the operation of the embodiment of the prior art as follows.

First, when the input clock CLK is low, the output signal of the NAND gate 111 becomes high and the high output signal is output as the high level clock signal PH1 through the inverters 112 and 113.

At this time, the high output signal of the inverter 130 to which the low input clock CLK is input and the output signal of the NAND gate 121 to which the high level clock signal PH1 is input are low and the low output signal is low. The inverter 122 outputs the low level clock signal PH2 through the inverters 122 and 123.

Accordingly, the output signal of the NAND gate 111 to which the low level clock signal PH2 is applied to one input terminal is maintained at a high level until the input clock CLK becomes high, and the clock signal PH1 is also high. The level is maintained, and the clock signal PH2 also maintains a low level.

Thereafter, when the input clock CLK becomes high, the output signal of the inverter 130 becomes low so that the output signal of the NAND gate 121 becomes high, and the high output signal becomes high level through the inverters 122 and 123. Clock signal PH2 is output.

Accordingly, the output signal of the NAND gate 111 to which the high level input clock CLK and the high level clock signal PH2 are inputted becomes low until the input clock CLK becomes low, and the low output signal. The low level clock signal PH1 is output through the inverters 112 and 113.

That is, the output signals of the NAND gates 111 and 121 are fed back to the input terminals of the respective NAND gates through two inverters 112 and 113 and 122 and 123 so that the inverse clock signals PH1 and PH2 are reversed. It happens.

In addition, FIG. 4 illustrates an inverter 430 for inverting the input clock CLK as shown in another embodiment of a conventional clock generation circuit, and a low level clock signal when the input clock CLK is high. Noah gate 411, inverter 412, 413 for generating PH1, and noah gate 421, inverter for generating low-level clock signal PH2 when the output signal of the inverter 430 is high. 422 and 423.

The clock signal PH2 is applied to one terminal of the noble gate 411, and the clock signal PH1 is applied to one terminal of the noble gate 421.

Referring to the operation of the other embodiment of the prior art as follows.

FIG. 2 replaces the NAND gates 111 and 121 with the NOR gates 411 and 421 in the circuit of FIG. 1, so that the output signal of the NOA gate 411 becomes low while the input clock CLK is high. The clock signal PH1 goes low and the clock signal PH2 goes high.

In addition, while the input clock CLK is low, the output signal of the inverter 430 becomes high so that the output signal of the NOA gate 421 becomes low so that the clock signal PH2 becomes low and the clock signal PH1 becomes high. It becomes a level.

That is, in the circuit of FIG. 2, the output signals of the NOA gates 411 and 421 are fed back to the input terminals of the relative NOA gates through two inverters 412, 413, and 422 and 423, respectively. ) Is generated.

However, in the related art of FIG. 1, a delay occurs in an inverter 130 connected between an input clock CLK and an input terminal of a NAND gate 111 and 121, and the NAND gate 111 and 121 are delayed. By outputting a low signal when both inputs are high, the clock signals PH1 and PH2 are waveforms of FIGS. 2 and 3 when the level of the input clock CLK changes from high to low or from low to high. As illustrated in FIG. 2, there is a problem in that accurate clock generation is not performed.

In addition, in the related art of FIG. 2, the NAND gate is replaced by the noar gate in the circuit of FIG. 1, so that only the waveforms of the clock signals PH1 and PH2 are opposite to those of FIG. Since the delay occurs in the inverters 430 connected between the 421s, as in the circuit of FIG. 1, the clock signals PH1 and PH2 overlap with each other when the level of the input clock CLK is switched to achieve accurate clock generation. There is a problem.

An object of the present invention is to devise a switched capacitor operational amplifier capable of generating an accurate clock by eliminating a delay error at the time of clock generation.

In addition, the present invention is to improve the accuracy by improving the clock feedthrough of the transfer switch used in the switched capacitor operational amplifier by eliminating the overlap error (clock error) when the clock generation by improving the existing clock generation circuit. The purpose is to.

In order to achieve the above object, the present invention generates two clock signals PH1 and PH2 by receiving a clock CLK, but the rising (or falling) transition of the clock signal PH1 and the clock signal ( A clock generator for performing a fall (or rise) transition of PH2 at the same time so that the clock signals PH1 and PH2 are in phase with each other; When clock signal PH1 goes from high to low and clock signal PH2 goes from low to high, it switches to auto zeroing mode, cancels its own offset to '0', and clock signal. When (PH1) goes from low to high, and clock signal (PH2) goes from high to low, it is converted into the comparison mode and differentially amplifies the reference signal (Vref) applied to one input terminal and the input signal input to the other input terminal. ; When the clock signal PH1 is low and the clock signal PH2 is high, the input signal Va is applied to the first capacitor connected between the first input signal Va terminal and the other input terminal of the operational amplifier. And a third transfer switch for shorting the other input terminal and the output terminal of the operational amplifier when the clock signal PH1 is low and the clock signal PH2 is high, and the clock signal PH1 is low. And a fifth transfer switch configured to apply a reference signal Vref to a second capacitor connected in parallel with the first capacitor to the other input terminal of the operational amplifier when the clock signal PH2 is high to discharge the second capacitor. A first switch unit comprising a; And a second transfer switch for applying the second input signal Vda to the first capacitor when the clock signal PH1 is high and the clock signal PH2 is low, and the clock signal PH1 is high and the clock signal ( And a second switch unit including a fourth transfer switch connecting the second capacitor between the other input terminal and the output terminal of the operational amplifier when PH2) is low.

The clock generator includes a first buffer circuit having an even number of inverters connected in series to buffer an input clock CLK, an output signal of the buffer, and outputs a clock signal PH1 through a NAND latch, and outputs the input clock CLK. The first clock generator for compensating for the delay error through the NAND latch and the output signal of the buffer are input through the NAND latch, and the clock signal PH2 that is in phase with the clock signal PH1 is reversed through the NOR latch. And a second clock generator for outputting and compensating for a delay error through the NOR latch when the level of the input clock CLK is switched.

The first clock generator includes a first inverter for inverting the input clock CLK passing through the first buffer circuit, an output signal of the first buffer circuit to one input terminal, and an output signal of the first buffer circuit. A first NAND gate for outputting a high signal when the signal is low, a second buffer circuit having an even number of inverters connected in series to buffer the output signal of the first NAND gate, and output a clock signal PH1, and the first inverter The NAND gate outputting the high signal when the output signal or the clock signal PH1 becomes low and the output signal of the second NAND gate are buffered and applied to the other input terminal of the first NAND gate. Preferably, the inverter includes a third buffer circuit connected in series.

The second clock generator includes a sixth inverter for inverting the input clock CLK that has passed through the first buffer circuit, and an output signal of the sixth inverter is input high by receiving an output signal of the sixth inverter at one input terminal. And a fourth buffer circuit having an even number of inverters connected in series to output a clock signal PH2 by buffering an output signal of the first gate. When the output signal or the clock signal PH2 becomes high, an even number of inverters output a low signal and an even number of inverters to buffer the output signal of the second NOA gate to the other input terminal of the first NOR gate. Preferably includes a fifth buffer circuit in series.

The present invention having the above configuration has the effect of enabling accurate operation by generating an accurate clock without overlap by eliminating the delay error at the time of clock generation existing in the existing clock generation circuit.

In addition, the present invention improves the clock feedthrough of the transmission gator by generating an accurate non-overlapping clock, thereby improving the accuracy of the switched capacitor operational amplifier.

1 is a conventional clock generation circuit diagram.
2 and 3 are waveform diagrams showing the occurrence of overlap in FIG.
Figure 4 is a circuit diagram showing another embodiment of the prior art.
5 is a clock generation circuit diagram according to an embodiment of the present invention.
6 and 7 are waveform diagrams at the time of clock generation in FIG.
8 is a circuit diagram of a switched capacitor operational amplifier according to an embodiment of the present invention.
9 is a timing diagram according to the operation of FIG. 8.

Hereinafter, an embodiment of a switched capacitor operational amplifier according to the present invention will be described in detail with reference to the accompanying drawings.

In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

8 is a diagram illustrating an embodiment of a switched capacitor operational amplifier according to the present invention.

As shown in FIG. 8, an embodiment of the switched capacitor operational amplifier according to the present invention receives a clock CLK to generate two clock signals PH1 and PH2, and the clock signal PH1 rises. (Or falling) the clock generator 800 and the clock signal 800 to perform the falling (or rising) transition of the clock signal PH2 at the same time point so that the clock signals PH1 and PH2 are reversed to each other. When PH1 is low and the clock signal PH2 is high, it switches to the auto zeroing mode to cancel its offset, and the clock signal PH1 is high and the clock signal PH2. When is low, the operation mode (OP) and the clock signal (PH1) is switched to the compare mode (compare mode) to differentially amplify the reference signal (Vref) applied to one input terminal and the input signal input to the other input terminal A capacitor connected to the other input terminal of the operational amplifier OP when the low and clock signals PH2 are high. A transfer switch SW1 that applies an input signal Va to the capacitor C1 and charges the reference signal Vref when the clock signal PH1 is low and the clock signal PH2 is high. A transfer switch SW5 that is applied to the capacitor C2 connected to the other input terminal of the circuit and discharges the capacitor C2, and when the clock signal PH1 is low and the clock signal PH2 is high. The transfer switch Sw3 which shorts the other input terminal and the output terminal out of the OP), and the input signal Vda when the clock signal PH1 is high and the clock signal PH2 is low. The other end of the capacitor C2 is connected to the output terminal out of the operational amplifier OP when the transfer switch SW2 and the clock signal PH1 are high and the clock signal PH2 is low. It includes a transfer switch (SW4).

The transfer gates SW1 to SW5 are formed of a combination of a PMOS field effect transistor (FET) and an NMOS FET.

As illustrated in the configuration diagram of FIG. 5, the clock generator 800 includes a buffer 510 including two inverters for buffering an input clock CLK, and a NAND signal when an output signal of the buffer 510 is input. The clock generator 520 outputs the clock signal PH1 through the latch, and the clock generator 530 outputs the clock signal PH2 through the NOR latch when the output signal of the buffer 510 is input.

The clock generator 520 generates a first inverter 521 for inverting the input clock CLK passing through the buffer 510, and generates a high level clock signal PH1 when the input clock CLK is low. A second NAND gate logic operation of the first NAND gate 522 and the second and third inverters, the output signal of the first inverter, the clock signal PH1, and applying the output signal to the first NAND gate; 523 and fourth and fifth inverters.

The clock generator 530 receives a sixth inverter 531 for inverting the input clock CLK passing through the buffer 510 and an output signal of the sixth inverter when the input clock CLK is low. The first NOR gate 532 and the seventh and eighth inverters for generating the low level clock signal PH2, the output signal of the buffer 510, and the clock signal PH2 are logic-operated to generate the output signal. The second NOR gate 533 and the ninth and tenth inverters applied to the first NOR gate 532 are configured.

Referring to the operation and effect of the embodiment of the present invention configured as described in detail as follows.

First, when the operation of the clock generator 800 of FIG. 5 is described, when the input clock CLK is low, the clock signal is buffered through the buffer 510 and the low signal is simultaneously input to the clock generators 520 and 530.

At this time, the clock generator 520 has a high output signal of the first NAND gate 522, to which the low signal of the buffer 510 is input, and its high output signal is a high level clock signal through the second and third inverters. It is output as (PH1).

The second NAND gate 523 outputs a low signal by calculating the high signal of the first inverter 521 which inverts the low signal of the buffer 510 and the high clock signal PH1, and outputs the low signal. The output signal of the first NAND gate 522 is kept high by being input to the first NAND gate 522 through fourth and fifth inverters.

In addition, since the low signal of the buffer 510 is inverted by the sixth inverter 531 and becomes the high signal, the clock generator 530 outputs the low signal and the low signal of the seventh and fifth signals is generated. 8 The inverter outputs the low level clock signal PH2.

At this time, the second NOR gate 533 outputs a high signal by calculating the low signal of the buffer 510 and the low clock signal PH2, and the high signal is the first NOR gate through the ninth and tenth inverters. Since it is input to 532, the output signal of the first NOR gate 532 is kept low.

Thereafter, when the input clock CLK is changed from low to high, a high signal is input to the clock generators 520 and 530 through the buffer 510.

In this case, the clock generator 520 is connected to the first NAND gate 522 because the output signals through the second NAND gate 523 and the fourth and fifth inverters maintain a low level during the delay time of the first inverter 521. The clock signal PH1 through the second and third inverters maintains a high level for a predetermined time. Thereafter, when the output signal of the first inverter 521 becomes low, the output signal of the second NAND gate 523 becomes high and the high signal is input to the first NAND gate 522 through the fourth and fifth inverters. The output signal of the first NAND gate 522 having a high signal input to both input terminals becomes low and is output as a low level clock signal PH1 through the second and third inverters.

In addition, when the high signal of the buffer 510 is input, the clock generator 530 becomes the output signal of the second NOR gate 533, and the low signal is the first NOR gate 532 through the seventh and eighth inverters. When the delay time of the sixth inverter 531 elapses and the output signal of the sixth inverter 531 becomes low, the first noble gate 532 in which the low signal is input to both input terminals is applied. The output signal of the signal becomes high and the high signal is output as the high level clock signal PH2 through the ninth and tenth inverters.

That is, even when the input clock CLK is switched from low to high, the clock signals PH1 and PH2 overlap as shown in the waveform diagram of FIG. 7 due to the difference in the delay time of each of the clock generators 520 and 530. It happens without this. In other words, referring to the waveform of FIG. 7, when the clock signal PH1 goes from high to low, the clock signal PH2 goes from low to high at a trip voltage near 2V, so the clock signal PH1 (PH2). It can be seen that is generated without overlap.

Similarly, when the input clock CLK is changed from high to low, the clock signals PH1 and PH2 are generated without overlapping through the same operation as described above. Referring to the waveform diagram of FIG. 6, the clock signal PH1 is generated. It can be seen that the clock signal PH2 also goes from high to low at a trip voltage near 2V when this low goes high.

8 is a diagram illustrating a configuration of a switched capacitor operational amplifier according to an exemplary embodiment of the present invention, in which the clock generator 800 of FIG. 5 is applied.

In FIG. 8, the output signal level of the operational amplifier OP is calculated by an operation as shown in Equation 1 below.

여기서, C1, C2는 캐패시터 용량, Va, Vda는 제,제2 입력신호, Vref는 기준신호이다.

Here, C1 and C2 are capacitor capacitances, Va and Vda are first and second input signals, and Vref is a reference signal.

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First, when the clock signal PH1 is low and the clock signal PH2 is high, the transfer gates SW1, SW3, and SW5 are turned on and the transfer gates SW2 and SW4 are turned off.

At this time, the operational amplifier OP is in an auto zeroing mode, and its own offset of the operational amplifier OP is canceled to '0', and at the same time, the input signal in the compare mode. All of the voltages charged in the capacitor C2 are discharged and the voltage of the input signal Va is charged in the capacitor C1 so that the difference Va-Vda is exactly achieved.

Thereafter, when the clock signal PH1 goes high and the clock signal PH2 goes low, the transfer gates SW1, SW3, and SW5 are turned off, and the transfer gates SW2 and SW4 are turned on.

In this case, the operational amplifier OP is switched to a compare mode, and the operational amplifier OP performs the actual amplification operation while the input signal Vda is applied to the capacitor C1.

For example, the capacitances of the capacitors C1 and C2 are set to 800fF and 100fF, the reference signal Vref is 1.65V, the first input signal Va is 1.06V, and the second input signal Vda is set to 1V, respectively. The simulation result is the same as the operation timing of FIG.

Subsequently, the output signal (out) value of the operational amplifier OP is obtained by substituting the set value in Equation 1 as shown in Equation 2 below.

여기서, 상기 [수학식 2]를 살펴보면 기준신호(Vref), 제1,제2 입력신호(Va)(Vda)의 값이 일정함으로 캐패시터(C1)(C2)의 용량을 가변함에 의해 연산증폭기(OP)의 출력신호(out) 레벨을 원하는 값으로 조정할 수 있음을 알 수 있다.

Here, referring to [Equation 2], the value of the reference signal (Vref), the first, second input signal (Va) (Vda) is constant so that the capacitance of the capacitor (C1) (C2) by varying the operational amplifier ( It can be seen that the output signal (out) level of OP) can be adjusted to a desired value.

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Therefore, when comparing the result of Equation 2 with the waveform of FIG. 9 (d), it can be seen that the output signal (out) of the operational amplifier OP is identical.

That is, the present invention eliminates the overlap error in generating the clock applied to the switched capacitor operational amplifier, thereby improving the clock feedthrough of the transfer gates SW1 to SW5 as well as improving the operation precision of the switched capacitor operational amplifier. It is to let.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be possible.

510: buffer 520,530: clock generator
800: clock generator OP: operational amplifier
SW1 ~ SW5: Transmission Gate

Claims (5)

Two clock signals PH1 and PH2 are generated by receiving the clock CLK, but the rising (or falling) transition of the clock signal PH1 and the falling (or rising) transition of the clock signal PH2 are the same. A clock generator which performs at a point in time so that the clock signals PH1 and PH2 are reversed with each other;
When a level shift (hereinafter, referred to as a 'first transition mode') of the clock signals PH1 and PH2 occurs, the self offset is canceled to '0', and is inversely opposite to the level of the first transition mode. When a level shift (hereinafter referred to as a 'second transition mode') of the clock signals PH1 and PH2 occurs, differentially amplifying the reference signal Vref applied to one input terminal and an input signal input to the other input terminal. Operational amplifiers;
A first transfer switch configured to apply and charge the input signal Va to a first capacitor connected between a first input signal Va terminal and the other input terminal of the operational amplifier, the other input terminal and the output terminal of the operational amplifier; A third transfer switch for shorting the circuit and a fifth transfer switch for applying the reference signal Vref to the second capacitor connected in parallel with the first capacitor to the other input terminal of the operational amplifier to discharge the second capacitor. A first switch unit operating in a first transition mode of the clock signals PH1 and PH2;
A second transfer switch for applying a second input signal Vda to the first capacitor and a fourth transfer switch for connecting the second capacitor between the other input terminal and the output terminal of the operational amplifier include a clock signal PH1. And a second switch unit operating in the second transition mode of the PH2. The clock generator of claim 1, wherein the clock generator
A first buffer circuit for buffering the input clock CLK,
A first clock generator which receives the output signal of the first buffer circuit as a set signal of a NAND latch and outputs a clock signal PH1;
And a second clock generator which receives the output signal of the first buffer circuit as a set signal of a NOR latch and outputs a clock signal PH2 that is in phase with the clock signal PH1. The method of claim 2, wherein the first clock generator
A first inverter for inverting the input clock CLK passing through the first buffer circuit,
A first NAND gate that receives an output signal of the first buffer circuit to one input terminal and outputs a high signal when the output signal of the first buffer circuit becomes low;
A second buffer circuit which buffers an output signal of the first NAND gate to output a clock signal PH1;
A second NAND gate outputting a high signal when the output signal of the first inverter or the clock signal PH1 becomes low;
And a third buffer circuit configured to buffer the output signal of the second NAND gate and apply the buffered signal to the other input terminal of the first NAND gate. The method of claim 2, wherein the second clock generator
A sixth inverter for inverting the input clock CLK passing through the first buffer circuit,
A first noble gate which receives the output signal of the sixth inverter through one input terminal and outputs a low signal when the output signal of the sixth inverter becomes high;
A fourth buffer circuit for outputting a clock signal PH2 by buffering the output signal of the first NOR gate;
A second NOR gate outputting a low signal when the output signal of the first buffer circuit or the clock signal PH2 becomes high;
And a fifth buffer circuit for buffering an output signal of the second NOR gate and applying it to the other input terminal of the first NOR gate. 3. The switched capacitor operational amplifier of claim 2, wherein the first buffer circuit comprises an even number of inverters connected in series.

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