CN105336368B

CN105336368B - Non-overlapping four-phase clock generation circuit

Info

Publication number: CN105336368B
Application number: CN201410345853.9A
Authority: CN
Inventors: 张现聚; 丁冲; 苏志强; 张君宇
Original assignee: Zhaoyi Innovation Technology Group Co ltd
Current assignee: Zhaoyi Innovation Technology Group Co ltd
Priority date: 2014-07-18
Filing date: 2014-07-18
Publication date: 2022-11-18
Anticipated expiration: 2034-07-18
Also published as: CN105336368A

Abstract

The invention discloses a non-overlapping four-phase clock generation circuit which comprises a bias voltage circuit, an enabling control circuit, a non-overlapping delay circuit and a clock frequency circuit, wherein the bias voltage circuit comprises a first bias voltage circuit and a second bias voltage circuit, the first bias voltage circuit is used for providing a first bias voltage for the non-overlapping delay circuit and the clock frequency circuit, the second bias voltage circuit is used for providing a second bias voltage for the non-overlapping delay circuit and the clock frequency circuit, the enabling control circuit is used for controlling the non-overlapping delay circuit according to an enabling signal and the clock frequency output by the clock frequency circuit, the non-overlapping delay circuit is used for generating a non-overlapping four-phase signal, and the clock frequency circuit is used for generating the clock frequency for controlling the non-overlapping four-phase clock signal. The non-overlapped four-phase clock signal provided by the invention has better stability and does not fluctuate along with the fluctuation of the power supply voltage.

Description

Non-overlapping four-phase clock generation circuit

Technical Field

The invention relates to the technical field of storage, in particular to a non-overlapping four-phase clock generation circuit.

Background

Non-volatile memories (Flash memories) often require high voltage erasing and writing in design, and generally a charge pump generates high voltage, and the charge pump is driven by a non-overlapping four-phase clock signal to ensure that the charge pump can work normally.

In the prior art, a non-overlap four-phase clock is generated by using a CMOS transistor, and when the non-overlap time is required to be longer, the requirement is difficult to be met only by using a smaller parasitic capacitance of the CMOS transistor, so that the longer non-overlap time is usually ensured by inserting a CMOS delay. However, when the charge pump operates in a wide voltage range, for example, 1.6V to 3.8v, the current of the CMOS transistor device may change greatly, which results in a large delay difference between the CMOS transistor and the CMOS transistor, and a change of the non-overlapping four-phase clock with the fluctuation of the power supply voltage, thereby making it difficult to ensure the correct operation of the charge pump.

FIG. 1 is a block diagram of a non-overlapping four-phase clock generation circuit in the prior art, as shown in FIG. 1, the non-overlapping four-phase clock generation circuit is generated by a MOS transistor, the non-overlapping time and clock frequency are controlled by the same input end φ and are controlled by four output ends φ ₁ 、φ ₂ 、φ ₃ And phi ₄ Respectively outputting non-overlapping four-phase clock signals. However, the non-overlap time and the clock frequency of this non-overlap four-phase clock generation circuit cannot be independently set, and in one clock cycle, when the power supply voltage fluctuates, the four-phase non-overlap time varies due to the variation of the clock frequency, so that the non-overlap four-phase clock signal varies with the fluctuation of the power supply voltage.

Disclosure of Invention

In view of the above, the present invention provides a non-overlapping four-phase clock generation circuit to solve the problem of non-overlapping four-phase clock signal fluctuation along with the power supply voltage.

The present invention provides a non-overlapping four-phase clock generation circuit including a bias voltage circuit, an enable control circuit, a non-overlapping delay circuit, and a clock frequency circuit, wherein,

the bias voltage circuit comprises a first bias voltage circuit and a second bias voltage circuit, the first bias voltage circuit and the second bias voltage circuit are respectively connected with the non-overlapping delay circuit and the clock frequency circuit, the first bias voltage circuit is used for providing a first bias voltage for the non-overlapping delay circuit and the clock frequency circuit, and the second bias voltage circuit is used for providing a second bias voltage for the non-overlapping delay circuit and the clock frequency circuit;

the input end of the enabling control circuit is connected with the clock frequency circuit, the output end of the enabling control circuit is connected with the non-overlapping delay circuit, and the enabling control circuit is used for controlling the non-overlapping delay circuit according to an enabling signal and the clock frequency output by the clock frequency circuit;

the non-overlapping delay circuit is connected with the bias voltage circuit at a first end, connected with the output end of the enable control circuit at a second end and connected with the clock frequency circuit at a third end, and used for generating a non-overlapping four-phase signal;

the first end of the clock frequency circuit is connected with the bias voltage circuit, the second end of the clock frequency circuit is connected with the enable control circuit, the third end of the clock frequency circuit is connected with the non-overlapping delay circuit, and the clock frequency circuit is used for generating clock frequency for controlling non-overlapping four-phase signals.

Further, the non-overlapping delay circuit includes a first stage circuit, a second stage circuit, a third stage circuit, a fourth stage circuit, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter, a fifteenth inverter, a first NOR gate circuit, a second NAND gate circuit, and a third NAND gate circuit, wherein,

the first-stage circuit is connected between the second-stage circuit and the output end of the enabling control circuit, and the midpoint of a connecting line of the first-stage circuit and the second-stage circuit is a first-stage node;

the second-stage circuit is connected between the first-stage circuit and the third-stage circuit, and the midpoint of a connecting line of the second-stage circuit and the third-stage circuit is a second-stage node;

the third-stage circuit is connected between the second-stage circuit and the fourth-stage circuit, and the midpoint of the connecting line of the third-stage circuit and the fourth-stage circuit is a third-stage node;

the fourth-stage circuit is connected between the third-stage circuit and the clock frequency circuit, and the midpoint of the connecting line of the fourth-stage circuit and the clock frequency circuit is a fourth-stage node;

the input end of the second inverter is connected with the first-stage node, the output end of the second inverter is used for outputting a first inverted clock signal, the output end of the second inverter is connected with the input end of the third inverter, the output end of the third inverter is used for outputting a first clock signal, and the output end of the third inverter is connected with the first input end of the second NOR gate circuit and the first input end of the third NAND gate circuit;

the input end of the fourth inverter is connected with the second-stage node, the output end of the fourth inverter is used for outputting a second inverted clock signal, the output end of the fourth inverter is connected with the input end of the fifth inverter, the output end of the fourth inverter is connected with the first input end of the first NOR gate circuit and the first input end of the second NAND gate circuit, and the output end of the fifth inverter is used for outputting a second clock signal;

the input end of the sixth inverter is connected to the third-level node, the output end of the sixth inverter is configured to output a third inverted clock signal, the output end of the sixth inverter is connected to the input end of the seventh inverter, the output end of the seventh inverter is configured to output a third clock signal, and the output end of the seventh inverter is connected to the second input end of the first nor gate circuit and the second input end of the second nand gate circuit;

the input end of the eighth inverter is connected to the fourth node, the output end of the eighth inverter is configured to output a fourth inverted clock signal, the output end of the eighth inverter is connected to the input end of the ninth inverter, and is connected to the second input end of the second nor gate circuit and the second input end of the third nand gate circuit, and the output end of the ninth inverter is configured to output a fourth clock signal;

the output end of the first NOR gate circuit is connected with the input end of the tenth inverter, and the output end of the tenth inverter is used for outputting a first four-phase clock signal;

the output end of the second NAND gate circuit is connected with the input end of the eleventh inverter, the output end of the eleventh inverter is connected with the input end of the twelfth inverter, and the output end of the twelfth inverter is used for outputting a second phase clock signal;

an output end of the second nor gate circuit is connected with an input end of the thirteenth inverter, an output end of the thirteenth inverter is connected with an input end of the fourteenth inverter, and an output end of the fourteenth inverter is used for outputting a third phase clock signal;

and the output end of the third NAND gate circuit is connected with the input end of the fifteenth inverter, and the output end of the fifteenth inverter is used for outputting a fourth phase clock signal.

Further, the first stage circuit comprises a second PMOS tube, a third PMOS tube, a second NMOS tube and a third NMOS tube, wherein,

the grid electrode of the second PMOS tube is used for receiving first bias voltage generated by a first bias voltage circuit, the source electrode of the second PMOS tube is connected with a power supply, the drain electrode of the second PMOS tube is connected with the source electrode of the third PMOS tube, the grid electrode of the third PMOS tube is connected with the output end of an enable control circuit, the drain electrode of the third PMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the second NMOS tube is connected with the grid electrode of the third PMOS tube, the source electrode of the second NMOS tube is connected with the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube is used for receiving second bias voltage generated by a second bias voltage circuit, and the source electrode of the third NMOS tube is grounded;

the second-stage circuit comprises a fourth PMOS tube, a fifth PMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube, wherein,

the grid electrode of the fourth PMOS tube is used for receiving a first bias voltage generated by a first bias voltage circuit, the source electrode of the fourth PMOS tube is connected with a power supply, the drain electrode of the fourth PMOS tube is connected with the source electrode of the fifth PMOS tube, the grid electrode of the fifth PMOS tube is connected with the grid electrode of the fourth NMOS tube, the midpoint of the connecting line of the grid electrode of the fifth PMOS tube and the grid electrode of the fourth NMOS tube and the midpoint of the connecting line of the drain electrode of the third PMOS tube and the drain electrode of the second NMOS tube in the first-stage circuit are used as a first-stage node, the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is connected with the source electrode of the sixth NMOS tube, the grid electrode of the fifth NMOS tube is used for receiving a reverse enable signal, the drain electrode of the fifth NMOS tube is connected with the grid electrode of the fourth NMOS tube and the grid electrode of the fifth PMOS tube, and the grid electrode of the sixth NMOS tube is used for receiving a second bias voltage generated by a second bias voltage circuit;

the third stage circuit comprises a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a seventh NMOS tube and an eighth NMOS tube, wherein,

the gate of the sixth PMOS tube is used for receiving an enabling signal, the source of the sixth PMOS tube is connected with a power supply, the drain of the sixth PMOS tube is connected with the gate of the eighth PMOS tube, the source of the seventh PMOS tube is connected with the power supply, the gate of the seventh PMOS tube is used for receiving a first bias voltage generated by a first bias voltage circuit, the drain of the seventh PMOS tube is connected with the source of the eighth PMOS tube, the drain of the eighth PMOS tube is connected with the drain of the seventh NMOS tube, the midpoint of the connection line between the drain of the eighth PMOS tube and the drain of the seventh NMOS tube and the midpoint of the connection line between the drain of the fifth PMOS tube and the drain of the fourth NMOS tube in the second-stage circuit are used as a second-stage node, the gate of the seventh NMOS tube is connected with the gate of the eighth PMOS tube, the source of the seventh NMOS tube is connected with the drain of the eighth NMOS tube, the gate of the eighth NMOS tube is used for receiving a second bias voltage generated by a second bias voltage circuit, and the source of the eighth NMOS tube is grounded;

the fourth stage circuit comprises a ninth PMOS tube, a tenth PMOS tube, a ninth NMOS tube, a tenth NMOS tube and an eleventh NMOS tube, wherein,

the gate of the ninth PMOS transistor is configured to receive a first bias voltage generated by a first bias voltage circuit, the source of the ninth PMOS transistor is connected to a power supply, the drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor, the gate of the tenth PMOS transistor is connected to the gate of the tenth NMOS transistor, a midpoint between a connection line between the gates of the tenth PMOS transistor and the gate of the tenth NMOS transistor and a midpoint between a connection line between the drains of the eighth PMOS transistor and the drain of the seventh NMOS transistor in the third stage circuit are used as a third stage node, the drain of the tenth PMOS transistor is connected to the drain of the tenth NMOS transistor, the source of the tenth NMOS transistor is connected to the drain of the eleventh NMOS transistor, a connection line between the source of the tenth NMOS transistor and the drain of the eleventh NMOS transistor and a midpoint between connection lines of the clock frequency circuits are used as a fourth stage node, the gate of the ninth NMOS transistor is configured to receive a reverse enable signal, the drain of the ninth NMOS transistor is connected to the gate of the tenth NMOS transistor, the source of the ninth NMOS transistor is grounded, the gate of the ninth NMOS transistor is configured to receive a reverse enable signal, the drain of the eleventh NMOS voltage, the eleventh NMOS transistor is configured to receive the second bias voltage, and the source of the ninth NMOS transistor is configured to ground, and the second bias voltage of the eleventh NMOS transistor.

Further, the clock frequency circuit includes a fifth stage circuit and a sixth stage circuit, wherein,

the fifth-stage circuit is connected between the fourth-stage circuit and the sixth-stage circuit, and the midpoint of the connecting line of the fifth-stage circuit and the sixth-stage circuit is a fifth-stage node;

the sixth-stage circuit is connected between the fifth-stage circuit and the enabling control circuit, and the midpoint of a connecting line of the sixth-stage circuit and the enabling control circuit is a sixth-stage node.

Further, the fifth stage circuit includes an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, and a first capacitor, wherein,

the gate of the eleventh PMOS transistor is used for receiving an enable signal, the source of the eleventh PMOS transistor is connected to a power supply, the drain of the eleventh PMOS transistor is connected to the gate of the thirteenth PMOS transistor, the gate of the twelfth PMOS transistor is connected to the gate of the first PMOS transistor, the source of the twelfth PMOS transistor is connected to the power supply, the drain of the twelfth PMOS transistor is connected to the source of the thirteenth PMOS transistor, the drain of the thirteenth PMOS transistor is connected to the drain of the twelfth NMOS transistor, the source of the twelfth NMOS transistor is connected to the drain of the thirteenth NMOS transistor, the gate of the thirteenth NMOS transistor is used for receiving a second bias voltage generated by a second bias voltage circuit, the source of the thirteenth NMOS transistor is grounded, the first end of the first capacitor is connected to the fifth-stage node, and the second end of the first capacitor is grounded;

the sixth stage circuit comprises a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube and a second capacitor,

a gate of the fourteenth PMOS transistor is configured to receive a first bias voltage generated by a first bias voltage circuit, a source of the fourteenth PMOS transistor is connected to a power supply, a drain of the fourteenth PMOS transistor is connected to a source of the fifteenth PMOS transistor, a gate of the fifteenth PMOS transistor is connected to a gate of the fifteenth NMOS transistor, a connection line between the gate of the fifteenth PMOS transistor and the gate of the fifteenth NMOS transistor is connected to a midpoint of a connection line between a drain of a thirteenth PMOS transistor and a source of the twelfth NMOS transistor in the fifth-stage circuit, and the gate of the fourteenth NMOS transistor is configured to receive an inverted enable signal, the drain of the fourteenth NMOS transistor is connected to the gate of the fifteenth NMOS transistor, and the source of the fourteenth NMOS transistor is grounded, the source of the fifteenth NMOS transistor is connected with the drain of the sixteenth NMOS transistor, the gate of the sixteenth NMOS transistor is used for receiving a second bias voltage generated by a second bias voltage circuit, the source of the sixteenth NMOS transistor is grounded, the midpoint of the connection line of the drain of the fifteenth PMOS transistor and the drain of the fifteenth NMOS transistor and the midpoint of the connection line of the enable control circuit are a sixth-level node, the first end of the second capacitor is connected with the sixth-level node, the second end of the second capacitor is grounded, the source of the sixteenth PMOS transistor is connected with a power supply, the gate of the sixteenth PMOS transistor is used for receiving an enable signal, and the drain of the sixteenth PMOS transistor is connected with the sixth-level node and the midpoint of the connection line of the enable control circuit.

Furthermore, the first stage circuit, the second stage circuit, the third stage circuit and the fourth stage circuit respectively include at least one capacitor, a first end of the at least one capacitor is connected to any one of the first stage node, the second stage node, the third stage node and the fourth stage node, and a second end of the at least one capacitor is grounded.

Further, the first capacitor, the second capacitor and the at least one capacitor include any one of a MOS capacitor, a MIM capacitor, a PIP capacitor and a MIP capacitor.

Furthermore, the clock frequency circuit further comprises at least one stage of circuit, and the at least one stage of circuit is sequentially connected between the fifth stage of circuit and the sixth stage of circuit.

The non-overlapping four-phase clock generation circuit provided by the invention has the advantages that the non-overlapping delay circuit controls the delay time of the non-overlapping four-phase clock signal, the clock frequency circuit controls the clock frequency of the non-overlapping four-phase clock signal, so that the non-overlapping time and the clock frequency can be set independently, as long as the clock frequency is stable, the non-overlapping time between four phases can keep good stability and cannot fluctuate along with the fluctuation of the power supply voltage, and the stable non-overlapping four-phase clock signal which does not change along with the fluctuation of the power supply voltage is generated.

Drawings

The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:

FIG. 1 is a block diagram of a non-overlapping four-phase clock generation circuit in the prior art;

FIG. 2 is a block diagram of a non-overlapping four-phase clock generation circuit according to an embodiment of the present invention;

FIG. 3 is a block diagram of the bias voltage circuit in a non-overlapping four-phase clock generating circuit according to a second embodiment of the present invention;

FIG. 4 is a block diagram of the enable control circuit in a non-overlapping four-phase clock generation circuit according to a second embodiment of the present invention;

5 a-5 c are block diagrams of the non-overlap delay circuit in a non-overlap four-phase clock generation circuit according to a second embodiment of the present invention;

fig. 6 is a structural diagram of the time frequency circuit in the non-overlapping four-phase clock generating circuit according to the second embodiment of the present invention;

fig. 7 is a timing diagram of clock signals and phase clock signals in a non-overlapping four-phase clock generation circuit according to a second embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some but not all of the relevant aspects of the present invention are shown in the drawings.

Example one

Fig. 2 is a structural diagram of a non-overlapping four-phase clock generation circuit according to an embodiment of the present invention, and as shown in fig. 2, the non-overlapping four-phase clock generation circuit may be applied to an integrated circuit chip for in-line electrical erasing and electrical writing of a non-volatile memory, and includes a bias voltage circuit 11, an enable control circuit 12, a non-overlapping delay circuit 13, and a clock frequency circuit 14.

The bias voltage circuit 11 includes a first bias voltage circuit 111 and a second bias voltage circuit 112, the first bias voltage circuit 111 and the second bias voltage circuit 112 are respectively connected to the non-overlap delay circuit 13 and the clock frequency circuit 14, the first bias voltage circuit 111 is configured to provide a first bias voltage VBP for the non-overlap delay circuit 13 and the clock frequency circuit 14, and the second bias voltage circuit 112 is configured to provide a second bias voltage VBN for the non-overlap delay circuit 13 and the clock frequency circuit 14.

In this embodiment, the magnitudes of the first bias voltage VBP and the second bias voltage VBN can be achieved by providing a constant current source in the first bias circuit 111, providing a constant current source in the second bias circuit 112, and controlling the magnitudes of the constant currents generated by the two constant current sources. By controlling the first bias voltage VBP and the second bias voltage VBN, the magnitude of the charging and discharging current in each stage of the circuit in the non-overlapping delay circuit 13 can be controlled, and then the non-overlapping delay time can be determined according to the magnitude of the parasitic capacitance in each stage of the circuit in the non-overlapping delay circuit 13.

The enable control circuit 12 has an input terminal connected to the clock frequency circuit 14 and an output terminal connected to the non-overlapping delay circuit 13, and the enable control circuit 12 is configured to control the non-overlapping delay circuit 13 according to an enable signal and the clock frequency output by the clock frequency circuit 14.

In this embodiment, the clock frequency output by the clock frequency circuit 14 may be determined by changing the node capacitance in each stage of the clock frequency circuit 14 to determine the charging and discharging time, so as to obtain the clock frequency in the clock frequency circuit 14.

The non-overlapping delay circuit 13 has a first terminal connected to the bias voltage circuit 11, a second terminal connected to the output terminal of the enable control circuit 12, and a third terminal connected to the clock frequency circuit 14, wherein the non-overlapping delay circuit 13 is configured to generate a non-overlapping four-phase signal.

In this embodiment, the non-overlap delay circuit 13 may control the magnitude of the constant current source in the bias voltage circuit 11 and the magnitude of the parasitic capacitance in each stage circuit in the non-overlap delay circuit 13 to jointly determine the non-overlap delay, and the clock frequency circuit 14 obtains the clock frequency, where the clock frequency and the non-overlap delay are independent of each other, so that as long as the clock frequency is stable, the non-overlap time between four phases can be kept stable, thereby generating a stable non-overlap four-phase clock signal.

The clock frequency circuit 14 has a first terminal connected to the bias voltage circuit 11, a second terminal connected to the enable control circuit 12, and a third terminal connected to the non-overlapping delay circuit 13, and is configured to generate a clock frequency for controlling a non-overlapping four-phase signal.

The clock frequency circuit 14 can change the charging and discharging time of the nodes of each stage of circuit in the clock frequency by changing the capacitance of the nodes in each stage of circuit, thereby controlling the clock frequency.

In the non-overlapping four-phase clock generating circuit provided by the first embodiment of the present invention, the non-overlapping delay circuit controls the delay time of the non-overlapping four-phase signal, and the clock frequency circuit controls the clock frequency of the non-overlapping four-phase clock generating circuit, so that the non-overlapping time and the clock frequency can be set independently, and as long as the clock frequency is stable, the non-overlapping time between four phases can maintain good stability and does not fluctuate with the fluctuation of the power supply voltage, thereby generating a stable non-overlapping four-phase clock signal that does not change with the fluctuation of the power supply voltage.

Example two

Fig. 3 to fig. 6 are structural diagrams of a non-overlapping four-phase clock generation circuit according to a second embodiment of the present invention, where the non-overlapping four-phase clock generation circuit includes a bias voltage circuit 11, an enable control circuit 12, a non-overlapping delay circuit 13, and a clock frequency circuit 14, where the bias voltage circuit 11 includes a first bias voltage circuit 111 and a second bias voltage circuit 112.

In this embodiment, the first bias voltage circuit 111 is configured to provide a first bias voltage VBP for the non-overlapping delay circuit 13 and the clock frequency circuit 14, and the second bias voltage circuit 112 is configured to provide a second bias voltage VBN for the non-overlapping delay circuit 13 and the clock frequency circuit 14, and each bias voltage circuit may be composed of a MOS transistor and a constant current source to increase the bias voltage. The first bias voltage circuit and the second bias voltage circuit may be in various forms, and fig. 3 is a structural diagram of the bias voltage circuit in a non-overlapping four-phase clock generating circuit according to a second embodiment of the present invention, as shown in fig. 3, the first bias voltage circuit 111 in the bias voltage circuit 11 may include a first PMOS transistor P1 and a first constant current source D1, wherein,

the source electrode of the first PMOS tube P1 is connected with a power supply VDD, the drain electrode of the first PMOS tube P1 is connected with the first end of a first constant current source D1, the grid electrode of the first PMOS tube P1 is connected with a non-overlapping delay circuit 13 and a clock frequency circuit 14, the substrate of the first PMOS tube P1 is connected with the power supply VDD, the second end of the first constant current source D1 is grounded, and the first bias voltage circuit 111 is used for outputting a first bias voltage VBP.

The second bias voltage circuit 112 may include a first NMOS transistor N1 and a second constant current source D2, wherein,

the drain electrode of the first NMOS tube N1 is connected with the second end of the second constant current source D2, the source electrode of the first NMOS tube N1 is grounded with the substrate, the grid electrode of the first NMOS tube N1 is connected with the non-overlapping delay circuit 13 and the clock frequency circuit 14, and the first end of the second constant current source D2 is connected with the power supply VDD.

The first constant current source D1 and the second constant current source D2 can provide a fixed current and have a very large internal resistance, so that they are often used in electronic circuits to provide a stable bias voltage, which can greatly improve the stability and output gain of the circuit.

By controlling the magnitudes of the currents of the first and second constant current sources D1 and D2, the magnitudes of the first and second bias voltages VBP and VBN generated by the first and second

bias voltage circuits

111 and 112 can be controlled.

It should be noted that, there are many ways for the first constant current source D1 and the second constant current source D2 to generate the constant current, and the method is not limited to a specific circuit form, as long as the constant current required by the present invention can be generated, for example, the circuits of the first constant current source D1 and the second constant current source D2 can be implemented by a Bipolar Junction Transistor (BJT) or a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), and the technology for generating the constant current by the constant current source is the prior art, and is not described herein again.

IN this embodiment, the enable control circuit is used for controlling the non-overlap delay circuit according to the enable signal AND the clock frequency output by the clock frequency circuit, fig. 4 is a structural diagram of the enable control circuit IN a non-overlap four-phase clock generation circuit according to a second embodiment of the present invention, as shown IN fig. 4, the enable control circuit 12 may include a first input terminal IN1, a second input terminal EN, a first nand gate AND1, a first inverter INVO1, a first output terminal OUT1, AND a second output terminal ENB, wherein,

the first input terminal IN1 is connected to the clock frequency circuit 14 AND a first input terminal of the first nand gate AND1, the second input terminal EN is connected to a second input terminal of the first nand gate AND1 AND an input terminal of the first inverter INVO1, the second input terminal EN is an enable signal input terminal for inputting an enable signal, the output terminal of the first inverter INVO is a second output terminal ENB for outputting a reverse enable signal, AND the output terminal of the first nand gate AND1 is a first output terminal OUT1 connected to the non-overlap delay circuit 13.

It should be noted that the second input terminal EN in the enable control circuit 12 is used for inputting an enable signal for controlling the non-overlapping four-phase clock generation circuit, when the circuit is in operation, the second input terminal EN inputs a high level, when the circuit is not in operation, the second input terminal EN inputs a low level, and the clock cycle of the non-overlapping delay circuit is controlled by the clock frequency circuit 14.

In the present embodiment, the non-overlap delay circuit 13 is used to generate a non-overlap four-phase signal, AND fig. 5a to 5c are block diagrams of the non-overlap delay circuit in a non-overlap four-phase clock generation circuit according to a second embodiment of the present invention, AND as shown in fig. 5a, the non-overlap delay circuit 13 may include a first stage circuit 131, a second stage circuit 132, a third stage circuit 133, a fourth stage circuit 134, a second inverter INVO2, a third inverter INVO3, a fourth inverter INVO4, a fifth inverter INVO5, a sixth inverter INVO6, a seventh inverter INVO7, an eighth inverter INVO8, a ninth inverter INVO9, a tenth inverter vo10, an eleventh inverter inv 11, a twelfth inverter INVO12, a thirteenth inverter INVO13, a fourteenth inverter INVO14, a fifteenth inverter INVO15, a first nor gate OR1, a second nor gate OR2, a second nand gate AND a third nand gate AND a 3.

Fig. 5a is a structural diagram of each stage of the non-overlapping delay circuit in the non-overlapping four-phase clock generating circuit according to the second embodiment of the present invention, as shown in fig. 5a, the first stage circuit 131 is connected between the second stage circuit 132 and the output terminal of the enable control circuit 12, specifically, may be connected between the second stage circuit 132 and the first output terminal OUT1 of the enable control circuit in fig. 4, and a midpoint of a connection line between the first stage circuit 131 and the second stage circuit 132 is a first stage node NI1; the second-stage circuit 132 is connected between the first-stage circuit 131 and the third-stage circuit 133, and a midpoint of a connection line between the second-stage circuit 132 and the third-stage circuit 133 is a second-stage node NI2; the third-stage circuit 133 is connected between the second-stage circuit 132 and the fourth-stage circuit 134, and a midpoint of a connection line between the third-stage circuit 133 and the fourth-stage circuit 134 is a third-stage node NI3; the fourth stage circuit 134 is connected between the third stage circuit 133 and the clock frequency circuit 14, and a midpoint of a connection line between the fourth stage circuit 134 and the clock frequency circuit 14 is a fourth stage node NI4.

Fig. 5b is a circuit structure diagram of each stage of the non-overlap delay circuit in the non-overlap four-phase clock generating circuit according to the second embodiment of the present invention, as shown in fig. 5b, the first node NI1 is connected to two inverters connected in series, the first inverted clock signal CLKB1 is generated via the second inverter INVO2, the first clock signal CLK1 is generated via the third inverter INVO3, the second node NI2 is connected to two inverters connected in series, the second inverted clock signal CLKB2 is generated via the fourth inverter INVO4, the second clock signal CLK2 is generated via the fifth inverter INVO5, the third node NI3 is connected to an input terminal of the sixth inverter INVO6, an output terminal of the sixth inverter INVO6 is used for outputting the third inverted clock signal CLKB3, an output terminal of the sixth inverter INVO6 is connected to an input terminal of the seventh inverter INVO7, an output terminal of the seventh inverter INVO7 is used for outputting the third clock signal CLK3, the fourth node NI4 is connected to an input terminal of the eighth inverter 8, an output terminal of the fourth inverter 8 is used for outputting the ninth inverter clkvo signal CLKB, and an output terminal of the ninth inverter 9 is used for outputting the ninth inverter CLK 8.

Fig. 5c is a circuit configuration diagram of each stage of the non-overlap delay circuit in the non-overlap four-phase clock generating circuit according to the second embodiment of the present invention, as shown in fig. 5c, a first input terminal of the first nor gate OR1 is connected to an output terminal of a fourth inverter INVO4, a second input terminal of the first nor gate OR1 is connected to an output terminal of a seventh inverter INVO7, an output terminal of the first nor gate OR1 is connected to an input terminal of a tenth inverter INVO10, and an output terminal of the tenth inverter INVO10 is used for outputting the first four-phase clock signal PCLK1. That is, the second inverted clock signal CLKB2 output from the second stage node NI2 and the third clock signal CLK3 output from the third stage node NI3 output the first phase clock signal PCLK1 through the first nor gate OR 1.

The first input end of the second nand-gate AND2 is connected with the output end of the fourth inverter INVO4, the second input end of the first nand-gate OR1 is connected with the output end of the seventh inverter INVO7, the output end of the second nand-gate AND2 is connected with the input end of the eleventh inverter INVO11, the output end of the eleventh inverter INVO11 is connected with the input end of the twelfth inverter INVO12, AND the output end of the twelfth inverter INVO12 is used for outputting a second four-phase clock signal PCLK2. That is, the second inverted clock signal CLKB2 output by the second stage node NI2 AND the third clock signal CLK3 output by the third stage node NI3 output the second phase clock signal PCLK2 through the second nand gate AND 2.

A first input end of the second nor-gate OR2 is connected with an output end of the third inverter INVO3, a second input end of the second nor-gate OR2 is connected with an output end of the eighth inverter INVO8, an output end of the second nor-gate OR2 is connected with an input end of the thirteenth inverter INVO13, an output end of the thirteenth inverter INVO13 is connected with an input end of the fourteenth inverter INVO14, and an output end of the fourteenth inverter INVO14 is used for outputting the third phase clock signal PCLK3. That is, the first clock signal CLK1 output by the first stage node NI1 and the fourth inverted clock signal CLKB4 output by the fourth stage node NI4 output the third phase clock signal PCLK3 through the second nor gate OR 2.

A first input end of the third nand gate AND3 is connected with an output end of the third inverter INVO3, a second input end of the third nand gate AND3 is connected with an output end of the eighth inverter INVO8, an output end of the third nand gate AND3 is connected with an input end of the fifteenth inverter INVO15, AND an output end of the fifteenth inverter INVO15 is used for outputting a fourth phase clock signal PCLK4. That is, the first clock signal CLK1 output by the first stage node NI1 AND the fourth inverted clock signal CLKB4 output by the fourth stage node NI4 output the fourth phase clock signal PCLK4 through the third nand gate AND3.

Note that, the delay time of the clock signal output from each stage node is determined by changing the magnitudes of the constant current sources in the first bias circuit 111 and the second bias circuit 112 and/or the magnitudes of the parasitic capacitances in each stage circuit of the first stage node NI1, the second stage node NI2, the third stage node NI3, and the fourth stage node NI4.

Specifically, the first stage circuit 131 may include a second PMOS transistor P2, a third PMOS transistor P3, a second NMOS transistor N2, and a third NMOS transistor N3.

The gate of the second PMOS transistor P2 is configured to receive a first bias voltage VBP generated by the first bias voltage circuit 111, specifically, the gate of the second PMOS transistor may be connected to the gate of the first PMOS transistor in the first bias voltage circuit in fig. 1, the source of the second PMOS transistor P2 is connected to a power supply VDD, the drain of the second PMOS transistor P2 is connected to the source of the third PMOS transistor P3, the substrate of the second PMOS transistor P2 is connected to the substrate of the third PMOS transistor P3 and the power supply VDD, the gate of the third PMOS transistor P3 is connected to the output end of the enable control circuit 22, specifically, the gate of the third PMOS transistor P3 may be connected to the first output end OUT1 of the enable control circuit 22 in fig. 4, the drain of the third PMOS transistor P3 is connected to the drain of the second NMOS transistor N2, the gate of the second NMOS transistor N2 is connected to the gate of the third PMOS transistor P3, the source of the second NMOS transistor N2 is connected to the drain of the third NMOS transistor N3, the substrate of the second PMOS transistor N2 is grounded, the third NMOS transistor N3 is configured to receive a second bias voltage VBP 3, the gate of the NMOS transistor N3, and the drain of the NMOS transistor N3 is grounded, the second PMOS transistor N2 is configured to receive a second bias voltage VBP 3, the gate of the second bias voltage VBP 3, and the second bias voltage VBP 3, the drain of the second NMOS transistor N3, the second PMOS transistor N3 is connected to the second NMOS transistor N3, and the second NMOS transistor substrate is connected to ground, and the NMOS transistor N3, and the second NMOS transistor substrate is configured to receive a ground, the second bias voltage VBN 3, and the second bias voltage VBN 3;

the second stage circuit 132 includes a fourth PMOS transistor P4, a fifth PMOS transistor P5, a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6, wherein,

a gate of the fourth PMOS transistor N4 is configured to receive the first bias voltage VBP, and specifically, may be connected to the gate of the first PMOS transistor in fig. 1 for inputting the first bias voltage VBP, a source of the fourth PMOS transistor P4 is connected to the power supply VDD, a drain of the fourth PMOS transistor P4 is connected to the source of the fifth PMOS transistor P5, a substrate of the fourth PMOS transistor P4 is connected to the substrate of the fifth PMOS transistor P5 and the power supply VDD, a gate of the fifth PMOS transistor P5 is connected to the gate of the fourth NMOS transistor N4, a midpoint of a connection line between the gate of the fifth PMOS transistor P5 and the gate of the fourth NMOS transistor N4 and a midpoint of a connection line between the drain of the third PMOS transistor P3 and the drain of the second NMOS transistor N2 in the first-stage circuit 231 are used as a first-stage node NI1, and a drain of the fifth PMOS transistor P5 is connected to the drain of the fourth NMOS transistor N4, a source of the fourth NMOS transistor N4 is connected to a source of the sixth NMOS transistor N6, a substrate of the fourth NMOS transistor N4 is grounded, a gate of the fifth NMOS transistor N5 is configured to receive the enable signal ENB output by the enable control circuit 22, and specifically, may be connected to the second output end ENB of the enable control circuit in fig. 4, a drain of the fifth NMOS transistor N5 is connected to a gate of the fourth NMOS transistor N4 and a gate of the fifth PMOS transistor P5, a source of the fifth NMOS transistor N5 and the substrate are grounded, a gate of the sixth NMOS transistor N6 is configured to receive the second bias voltage VBN generated by the second bias voltage circuit 112, and specifically, may be connected to a gate of the first NMOS transistor N1 in the second bias voltage circuit 112 in fig. 1, and a source of the sixth NMOS transistor N6 and the substrate are grounded;

the third stage circuit 133 includes a sixth PMOS transistor P6, a seventh PMOS transistor P7, an eighth PMOS transistor P8, a seventh NMOS transistor N7, and an eighth NMOS transistor N8, wherein,

a gate of the sixth PMOS transistor P6 is configured to receive the enable signal EN, and in particular, may be connected to the second input terminal EN of the enable control circuit in fig. 4, a source of the sixth PMOS transistor P6 is connected to the power supply VDD, a drain of the sixth PMOS transistor P6 is connected to a gate of the eighth PMOS transistor P8, a substrate of the sixth PMOS transistor P6 is grounded, a source and a substrate of the seventh PMOS transistor P7 are connected to the power supply VDD, a gate of the seventh PMOS transistor P7 is configured to receive the first bias voltage VBP generated by the first bias voltage circuit 111, and in particular, may be connected to a gate of the first PMOS transistor and configured to input the first bias voltage VBP, a drain of the seventh PMOS transistor P7 is connected to a source of the eighth PMOS transistor P8, a substrate of the seventh PMOS transistor P7 is connected to a substrate of the eighth PMOS transistor P8 and the power supply VDD, the drain electrode of the eighth PMOS transistor P8 is connected to the drain electrode of the seventh NMOS transistor N7, the midpoint of the connection line between the drain electrode of the eighth PMOS transistor P8 and the drain electrode of the seventh NMOS transistor N7 is connected to the midpoint of the connection line between the drain electrode of the fifth PMOS transistor P5 and the drain electrode of the fourth NMOS transistor N4 in the second-stage circuit 232, and is used as a second-stage node NI2, the gate electrode of the seventh NMOS transistor N7 is connected to the gate electrode of the eighth PMOS transistor P8, the source electrode of the seventh NMOS transistor N7 is connected to the drain electrode of the eighth NMOS transistor N8, the substrate of the seventh NMOS transistor N7 is grounded, the gate electrode of the eighth NMOS transistor N8 is used to receive the second bias voltage VBN generated by the second bias voltage circuit 112, specifically, the gate electrode of the first NMOS transistor N1 in the second bias voltage circuit 112 in fig. 1 may be connected, and the source electrode of the eighth NMOS transistor N8 is grounded;

the fourth stage circuit 134 includes a ninth PMOS transistor P9, a tenth PMOS transistor P10, a tenth NMOS transistor N10, and an eleventh NMOS transistor N11, wherein,

the gate of the ninth PMOS transistor N9 is used for receiving the first bias voltage VBP generated by the first bias voltage circuit 111, and specifically, may be connected to the gate of the first PMOS transistor in fig. 1, the source of the ninth PMOS transistor P9 is connected to the substrate of the tenth PMOS transistor P10 and the power supply VDD, the drain of the ninth PMOS transistor P9 is connected to the source of the tenth PMOS transistor P10, the gate of the tenth PMOS transistor P10 is connected to the gate of the tenth NMOS transistor N10, the midpoint of the connection line between the gate of the tenth PMOS transistor P10 and the gate of the tenth NMOS transistor N10 and the midpoint of the connection line between the drain of the eighth PMOS transistor P8 and the drain of the seventh NMOS transistor P7 in the third stage circuit 133 are used as a third stage node NI3, the drain of the tenth PMOS transistor P10 is connected to the drain of the tenth NMOS transistor N10, the source of the tenth NMOS transistor N10 is connected to the drain of the eleventh NMOS transistor N11, a midpoint of a connection line between a source of the tenth PMOS transistor P10 and a drain of the eleventh NMOS transistor N11 and a midpoint of a connection line of the clock frequency circuit 14 are used as a fourth-stage node NI4, a substrate of the tenth NMOS transistor N10 is grounded, a gate of the ninth NMOS transistor N9 is configured to receive the enable signal ENB output by the enable control circuit 12, and specifically, may be connected to the second output end ENB in fig. 4, a drain of the ninth NMOS transistor N9 is connected to a gate of the tenth NMOS transistor N10, a source of the ninth NMOS transistor N9 is grounded, a substrate of the ninth NMOS transistor N9 is connected to a source of the ninth NMOS transistor N9, a gate of the eleventh NMOS transistor N11 is configured to receive the second bias voltage VBN generated by the second bias voltage circuit 112, and specifically, a gate of the eleventh NMOS transistor may be connected to a gate of the first NMOS transistor N1, and a source and a substrate of the eleventh NMOS transistor N11 are grounded.

It should be noted that, delay times between the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3 and the fourth clock signal CLK4 respectively generated at the first stage node NI1, the second stage node NI2, the third stage node NI3 and the fourth stage node NI4 may be controlled by adjusting current magnitudes of the first constant current source D1 and the second constant current source D2, so that magnitudes of the first bias voltage VBP and the second bias voltage VBN may be controlled, and further magnitudes of charging and discharging currents to the NI nodes NI1, NI2, NI3 and NI4 may be controlled; in addition, the parasitic capacitance of the MOS transistor in each stage of the first to fourth stage circuits 131 to 134 is controlled by controlling the current levels of the first and second constant current sources D1 and 134, and then the parasitic capacitance of the MOS transistor in each stage of the circuits is adjusted, so that the delay time between the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, and the fourth clock signal CLK4 can be adjusted.

The clock frequency circuit 14 is configured to generate a clock frequency for controlling a non-overlapping four-phase signal, and fig. 6 is a structural diagram of the time frequency circuit in the non-overlapping four-phase clock generating circuit according to the second embodiment of the present invention, and as shown in fig. 6, the clock frequency circuit 14 includes a fifth stage circuit 141 and a sixth stage circuit 142.

The fifth-stage circuit 141 is connected between the fourth-stage circuit 134 and the sixth-stage circuit 142, and a midpoint of a connection line between the fifth-stage circuit 141 and the sixth-stage circuit 142 is a fifth-stage node NI5.

The sixth stage circuit 142 is connected between the fifth stage circuit 141 and the enable control circuit 12, and specifically, may be connected between the fifth stage circuit 141 and the first input terminal IN1 of the enable control circuit IN fig. 4, and a midpoint of a connection line of the sixth stage circuit 142 and the first input terminal IN1 of the enable control circuit 12 is a sixth stage node NI6.

The clock frequency circuit 14 controls the clock frequency of the entire non-overlapping four-phase clock generation circuit by generating the clock frequency by the fifth stage circuit 141 and the sixth stage circuit 142.

Specifically, the fifth stage circuit 141 and the sixth stage circuit 142 may generate a clock frequency by the following circuits. The fifth stage circuit 141 includes an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, and a first capacitor C1.

The gate of the eleventh PMOS transistor P11 is configured to receive an enable signal EN, and specifically, may be connected to the second input end EN of the enable control circuit in fig. 4, the source of the eleventh PMOS transistor P11 is connected to the substrate of the eleventh PMOS transistor P11 and the power supply VDD, the drain of the eleventh PMOS transistor P11 is connected to the gate of the thirteenth PMOS transistor P13, the gate of the twelfth PMOS transistor P12 is connected to the gate of the first PMOS transistor P1, the source of the twelfth PMOS transistor P12 is connected to the power supply VDD, the drain of the twelfth PMOS transistor P12 is connected to the source of the thirteenth PMOS transistor P13, the substrate of the twelfth PMOS transistor P12 is connected to the substrate of the thirteenth PMOS transistor P13 and the power supply VDD, the drain of the thirteenth PMOS transistor P13 is connected to the drain of the twelfth NMOS transistor N12, the source of the twelfth NMOS transistor N12 is connected to the drain of the thirteenth NMOS transistor N13, the substrate of the twelfth NMOS transistor N12 is grounded, the gate of the thirteenth PMOS transistor N13 is configured to receive the second bias voltage 112 generated by the second bias circuit, the gate of the thirteenth NMOS transistor N12 is connected to the ground, the gate of the fifth NMOS transistor C1, and the fifth NMOS transistor C1 are connected to the ground, the second end of the second input end of the first NMOS transistor C1;

the sixth stage circuit 142 includes a fourteenth PMOS transistor P14, a fifteenth PMOS transistor P15, a sixteenth PMOS transistor P16, a fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, and a second capacitor C2.

The gate of the fourteenth PMOS transistor P14 is configured to receive the first bias voltage VBP generated by the first bias voltage circuit 111, and specifically, may be connected to the gate of the first PMOS transistor IN fig. 1, the source of the fourteenth PMOS transistor P14 is connected to the power supply VDD, the drain of the fourteenth PMOS transistor P14 is connected to the source of the fifteenth PMOS transistor P15, the substrate of the fourteenth PMOS transistor P14 is connected to the substrate of the fifteenth PMOS transistor P15 and the power supply VDD, the gate of the fifteenth PMOS transistor P15 is connected to the gate of the fifteenth NMOS transistor N15, a connection line between the gate of the fifteenth PMOS transistor P15 and the gate of the fifteenth NMOS transistor N15 is connected to a connection line between the drain of the thirteenth PMOS transistor P13 and the source of the twelfth NMOS transistor N12 IN the fifth stage circuit 141, and serves as a midpoint NI5 of the fifth stage node, the gate of the fourteenth NMOS transistor N14 is connected to receive the enable signal ENB output by the enable circuit, and specifically, and may be connected to the second output terminal ENB of the enable control circuit IN fig. 4, the drain of the fourteenth NMOS transistor N14 is connected to the gate of the fifteenth NMOS transistor N15, the source of the fourteenth NMOS transistor N14 is grounded, the substrate of the fourteenth NMOS transistor N14 is connected to the source of the fourteenth NMOS transistor N14, the source of the fifteenth NMOS transistor N15 is connected to the drain of the sixteenth NMOS transistor N16, the substrate of the fifteenth NMOS transistor N15 is grounded, the gate of the sixteenth NMOS transistor N16 is configured to receive the second bias voltage VBN generated by the second bias voltage circuit 112, and IN particular, may be connected to the gate of the first NMOS transistor IN fig. 1, the source and the substrate of the sixteenth NMOS transistor N16 are grounded, the midpoint between the connection line between the drain of the fifteenth PMOS transistor P15 and the drain of the fifteenth NMOS transistor N15 and the connection line between the enable control circuit 12 is the sixth-level node 6 NI, and IN between the connection line between the drain of the fifteenth PMOS transistor P15 and the drain of the fifteenth NMOS transistor N15 and the first input terminal 1 of the enable control circuit 12 is the sixth-level node 6 NI, the first end of the second capacitor C2 is connected to the sixth-level node NI6, the second end of the second capacitor C2 is grounded, the source of the sixteenth PMOS transistor P16 is connected to the substrate and the power supply VDD, the gate of the sixteenth PMOS transistor P16 is configured to receive the enable signal EN, and specifically, may be connected to the second input terminal EN in fig. 4, and the drain of the sixteenth PMOS transistor P16 is connected to the midpoint of the connection line between the sixth-level node NI6 and the enable control circuit 12.

The first capacitor C1 and the second capacitor C2 may include any one of a MOS capacitor, a MIM capacitor, a PIP capacitor, or an MIP capacitor.

It should be noted that the first capacitor C1 and the second capacitor C2 in the clock frequency circuit 14 and the MOS transistors in the fifth stage circuit 141 and the sixth stage circuit 142 respectively form an oscillator, and the output clock frequency can be adjusted by changing the size of the first capacitor C1 or the second capacitor C2, so as to control the period of each clock signal in the non-overlapping delay circuit 13.

Fig. 7 is a timing diagram of clock signals and phase clock signals in a non-overlapping four-phase clock generation circuit according to a second embodiment of the present invention, as shown in fig. 7.

Delays occur between the first, second, third, and fourth clock signals CLK1, CLK2, CLK3, and CLK4, which are determined by the sizes of the first and second constant current sources D1 and TD and parasitic capacitances at the first, second, third, and fourth stage nodes NI1, NI2, NI3, and NI 4; the clock frequencies of the first, second, third and fourth clock signals CLK1, CLK2, CLK3 and CLK4 are determined by the sizes of the first and second capacitors C1 and C2 at the fifth and sixth stage nodes NI5 and NI6, and thus, the clock frequencies of the first to fourth clock signals CLK1 to CLK4 can be adjusted by changing the sizes of the capacitors at the fifth and sixth stage nodes NI5 and NI6.

Referring to fig. 7, in the period T1, the first clock signal CLK1 is at a high level, the second clock signal CLK2, the third clock signal CLK3 AND the fourth clock signal CLK4 are all at a low level, so that the first four-phase clock signal PCLK1 output by the first inverted clock signal CLKB1 AND the third clock signal CLK3 after passing through the first nor gate OR1 is at a low level, the second four-phase clock signal PCLK2 output by the second nand gate AND2 is at a high level, the third four-phase clock signal PCLK3 output by the first clock signal CLK1 AND the fourth inverted clock signal CLKB4 after passing through the second nor gate OR2 is at a low level, AND the fourth four-phase clock signal PCLK4 output by the third nand gate AND3 is at a low level.

In the period T2, the second clock signal CLK2 goes high after the delay of the period T1, and correspondingly, the first four-phase clock signal PCLK1 and the second four-phase clock signal PCLK2 go high, and the third four-phase clock signal PCLK3 and the fourth four-phase clock signal PCLK4 keep the waveform in the period T1 unchanged.

In the period T3, the third clock signal CLK3 changes to the high level after a delay of the period T2, the second four-phase clock signal PCLK2 changes to the low level, and the first, third, and fourth four-phase clock signals PCLK1, PCLK3, and PCLK4 keep the waveform in the period T2 unchanged.

In the T4 period, the fourth clock signal CLK4 becomes high level after the delay of the T3 time, the fourth four-phase clock signal PCLK4 becomes high level, and the first, second, and third four-phase clock signals PCLK1, PCLK2, and PCLK3 keep the waveform in the T3 period unchanged.

By analogy, when the clock frequency generated by the clock frequency circuit 14 is stable, the non-overlap time of the non-overlap four-phase clock signal generated by the non-overlap delay circuit 13 can be kept stable regardless of the fluctuation of the power supply voltage.

In a preferred embodiment of the present embodiment, the first stage circuit 131, the second stage circuit 132, the third stage circuit 133 and the fourth stage circuit 134 in the non-overlapping delay circuit 13 further include at least one capacitor, a first end of the at least one capacitor is connected to any one of the first stage node NI1, the second stage node NI2, the third stage node NI3 and the fourth stage node NI4, and a second end of the at least one capacitor is grounded. Preferably, the at least one capacitor may include any one of a MOS capacitor, a MIM capacitor, a PIP capacitor, or a MIP capacitor.

In the preferred embodiment of the present embodiment, when the non-overlap time required by the non-overlap delay circuit 13 is longer, and the parasitic capacitances of the MOS transistors in the first stage circuit 131, the second stage circuit 132, the third stage circuit 133, and the fourth stage circuit 134 are smaller, the charging and discharging in each stage circuit is terminated quickly, so that the longer non-overlap time cannot be ensured, and the charging and discharging time of each stage circuit can be prolonged by increasing the capacitance, so that the non-overlap time is prolonged.

In another preferred embodiment of the present embodiment, the clock frequency circuit 14 may further include at least one stage circuit, and the at least one stage circuit is sequentially connected between the fifth stage circuit 141 and the sixth stage circuit 142.

All of the at least one stage circuits are used to determine the clock frequency of the clock frequency circuit 14 in cooperation with the fifth stage circuit 141 and the sixth stage circuit 142. The at least one stage circuit includes at least one PMOS transistor, at least one NMOS transistor, and a capacitor, and the circuit structure is the same as the fifth stage circuit 141 and the sixth stage circuit 142.

In the non-overlapping four-phase clock generating circuit provided by the second embodiment of the present invention, the non-overlapping delay circuit controls the delay time of the non-overlapping four-phase signal, and the clock frequency circuit controls the clock frequency of the non-overlapping four-phase clock generating circuit, so that the non-overlapping time and the clock frequency can be set independently, and as long as the clock frequency is stable, the non-overlapping time between the four phases can be kept stable and does not fluctuate with the fluctuation of the power supply voltage, thereby generating a stable non-overlapping four-phase clock signal which does not change with the fluctuation of the power supply voltage.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A non-overlapping four-phase clock generation circuit comprising a bias voltage circuit, an enable control circuit, a non-overlapping delay circuit, and a clock frequency circuit, wherein,

the non-overlapping delay circuit is connected with the bias voltage circuit at a first end, connected with the output end of the enable control circuit at a second end and connected with the clock frequency circuit at a third end, and is used for generating a non-overlapping four-phase signal;

the first end of the clock frequency circuit is connected with the bias voltage circuit, the second end of the clock frequency circuit is connected with the enabling control circuit, the third end of the clock frequency circuit is connected with the non-overlapping delay circuit, and the clock frequency circuit is used for generating clock frequency for controlling non-overlapping four-phase signals.

2. The non-overlapping four-phase clock generating circuit according to claim 1, wherein the non-overlapping delay circuit comprises a first stage circuit, a second stage circuit, a third stage circuit, a fourth stage circuit, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, a twelfth inverter, a thirteenth inverter, a fourteenth inverter, a fifteenth inverter, a first NOR gate circuit, a second NAND gate circuit, and a third NAND gate circuit, wherein,

the third-stage circuit is connected between the second-stage circuit and the fourth-stage circuit, and the midpoint of a connecting line of the third-stage circuit and the fourth-stage circuit is a third-stage node;

the fourth-stage circuit is connected between the third-stage circuit and the clock frequency circuit, and the midpoint of a connecting line of the fourth-stage circuit and the clock frequency circuit is a fourth-stage node;

the output end of the second nor gate circuit is connected with the input end of the thirteenth inverter, the output end of the thirteenth inverter is connected with the input end of the fourteenth inverter, and the output end of the fourteenth inverter is used for outputting a third phase clock signal;

3. The non-overlapping four-phase clock generation circuit of claim 2, wherein the first stage circuit comprises a second PMOS transistor, a third PMOS transistor, a second NMOS transistor, and a third NMOS transistor, wherein,

the grid electrode of the second PMOS tube is used for receiving a first bias voltage generated by a first bias voltage circuit, the source electrode of the second PMOS tube is connected with a power supply, the drain electrode of the second PMOS tube is connected with the source electrode of the third PMOS tube, the grid electrode of the third PMOS tube is connected with the output end of an enable control circuit, the drain electrode of the third PMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the second NMOS tube is connected with the grid electrode of the third PMOS tube, the source electrode of the second NMOS tube is connected with the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube is used for receiving a second bias voltage generated by a second bias voltage circuit, and the source electrode of the third NMOS tube is grounded;

the grid electrode of the fourth PMOS tube is used for receiving a first bias voltage generated by a first bias voltage circuit, the source electrode of the fourth PMOS tube is connected with a power supply, the drain electrode of the fourth PMOS tube is connected with the source electrode of the fifth PMOS tube, the grid electrode of the fifth PMOS tube is connected with the grid electrode of the fourth NMOS tube, the midpoint of the connecting line of the grid electrodes of the fifth PMOS tube and the fourth NMOS tube and the midpoint of the connecting line of the drain electrodes of the third PMOS tube and the second NMOS tube in the first-stage circuit are used as a first-stage node, the drain electrode of the fifth PMOS tube is connected with the drain electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is connected with the source electrode of the sixth NMOS tube, the grid electrode of the fifth NMOS tube is used for receiving a reverse enabling signal, the drain electrode of the fifth NMOS tube is connected with the grid electrode of the fourth NMOS tube and the grid electrode of the fifth PMOS tube, and the grid electrode of the sixth NMOS tube is used for receiving a second bias voltage generated by a second bias voltage circuit;

the fourth-stage circuit comprises a ninth PMOS tube, a tenth PMOS tube, a ninth NMOS tube, a tenth NMOS tube and an eleventh NMOS tube, wherein,

the gate of the ninth PMOS transistor is configured to receive a first bias voltage generated by a first bias voltage circuit, the source of the ninth PMOS transistor is connected to the power supply, the drain of the ninth PMOS transistor is connected to the source of the tenth PMOS transistor, the gate of the tenth PMOS transistor is connected to the gate of the tenth NMOS transistor, the midpoint between the connection lines of the gates of the tenth PMOS transistor and the eighth PMOS transistor in the third stage circuit is connected to the midpoint between the connection lines of the drains of the seventh NMOS transistor and the eighth PMOS transistor in the third stage circuit is used as a third stage node, the drain of the tenth PMOS transistor is connected to the drain of the tenth NMOS transistor, the source of the tenth NMOS transistor is connected to the drain of the eleventh NMOS transistor, the connection line between the source of the tenth PMOS transistor and the drain of the eleventh NMOS transistor is connected to the midpoint between the clock frequency circuit as a fourth stage node, the gate of the ninth NMOS transistor is configured to receive a reverse enable signal, the drain of the ninth NMOS transistor is connected to the gate of the tenth NMOS transistor, the source of the ninth NMOS transistor is connected to the ground, the ninth NMOS transistor is configured to receive a second bias voltage, and the eleventh NMOS transistor is configured to generate a fourth stage node.

4. The non-overlapping four-phase clock generation circuit of claim 2, wherein the clock frequency circuit comprises a fifth stage circuit and a sixth stage circuit, wherein,

5. The non-overlapping four-phase clock generation circuit of claim 4, wherein the fifth stage circuit comprises an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, and a first capacitor, wherein,

the gate of the eleventh PMOS transistor is used for receiving an enable signal, the source of the eleventh PMOS transistor is connected with a power supply, the drain of the eleventh PMOS transistor is connected with the gate of the thirteenth PMOS transistor, the gate of the twelfth PMOS transistor is connected with the gate of the first PMOS transistor, the source of the twelfth PMOS transistor is connected with the power supply, the drain of the twelfth PMOS transistor is connected with the source of the thirteenth PMOS transistor, the drain of the thirteenth PMOS transistor is connected with the drain of the twelfth NMOS transistor, the source of the twelfth NMOS transistor is connected with the drain of the thirteenth NMOS transistor, the gate of the thirteenth NMOS transistor is used for receiving a second bias voltage generated by a second bias voltage circuit, the source of the thirteenth NMOS transistor is grounded, the first end of the first capacitor is connected with the fifth-stage node, and the second end of the first capacitor is grounded;

a gate of the fourteenth PMOS transistor is configured to receive a first bias voltage generated by a first bias voltage circuit, a source of the fourteenth PMOS transistor is connected to a power supply, a drain of the fourteenth PMOS transistor is connected to a source of the fifteenth PMOS transistor, a gate of the fifteenth PMOS transistor is connected to a gate of the fifteenth NMOS transistor, a connection line between the gate of the fifteenth PMOS transistor and the gate of the fifteenth NMOS transistor is connected to a midpoint of a connection line between a drain of a thirteenth PMOS transistor and a source of the twelfth NMOS transistor in the fifth-stage circuit, and the gate of the fourteenth NMOS transistor is configured to receive an inverted enable signal, the drain of the fourteenth NMOS transistor is connected to the gate of the fifteenth NMOS transistor, and the source of the fourteenth NMOS transistor is grounded, the source of the fifteenth NMOS tube is connected with the drain of the sixteenth NMOS tube, the gate of the sixteenth NMOS tube is used for receiving a second bias voltage generated by a second bias voltage circuit, the source of the sixteenth NMOS tube is grounded, the midpoint of a connecting line between the drain of the fifteenth PMOS tube and the drain of the fifteenth NMOS tube and the midpoint of a connecting line between the enable control circuits are sixth-level nodes, the first end of the second capacitor is connected with the sixth-level nodes, the second end of the second capacitor is grounded, the source of the sixteenth PMOS tube is connected with the power supply, the gate of the sixteenth PMOS tube is used for receiving enable signals, and the drain of the sixteenth PMOS tube is connected with the sixth-level nodes and the midpoint of a connecting line between the enable control circuits.

6. The non-overlapping four-phase clock generation circuit of claim 3, wherein the first stage circuit, the second stage circuit, the third stage circuit, and the fourth stage circuit each further comprise at least one capacitor, a first terminal of the at least one capacitor is connected to any one of the first stage node, the second stage node, the third stage node, and the fourth stage node, and a second terminal of the at least one capacitor is connected to ground.

7. The non-overlapping four-phase clock generation circuit according to claim 5 or 6, wherein the capacitor comprises any one of a MOS capacitor, a MIM capacitor, a PIP capacitor, and a MIP capacitor.

8. The non-overlapping four-phase clock generation circuit of claim 4, wherein the clock frequency circuit further comprises at least one stage of circuitry serially connected between the fifth stage of circuitry and the sixth stage of circuitry.