CN102280127A - Clock generation circuit and charge pump system - Google Patents
Clock generation circuit and charge pump system Download PDFInfo
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Abstract
The invention relates to a clock generation circuit and a charge pump system. The clock generation circuit comprises: a voltage source device comprising a first voltage source for providing first power supply voltage and a power supply voltage stabilizing unit, wherein the power supply voltage stabilizing unit is provided for adjusting the first power supply voltage to obtain second power supply voltage; a clock oscillation unit provided for generating a reference clock signal; a clock conversion unit provided for converting the reference clock signal into a first type clock signal and a second type clock signal through adopting the first power supply voltage as the driving voltage; a clock driving apparatus, wherein the clock driving apparatus comprises: a first clock driving unit provided for enhancing the first type clock signal through adopting the second power supply voltage as the driving voltage; a second clock driving unit provided for enhancing the second type clock signal through adopting the first power supply voltage and the second power supply voltage as the driving voltages. Compared to the prior art, with the present invention, the first clock driving unit and the second clock driving unit are arranged respectively and independently, and different power supply voltages are provided, such that charging efficiency and transmission efficiency are improved.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of clock generation circuit and charge pump system.
Background technology
In the information age, information stores is one of most important technology contents in the infotech.Storeies such as DRAM, EEPROM, flash memory obtain application more and more widely.
Based on low-power consumption, requirement cheaply, the supply voltage VDD of storer is lower usually, for example 2.5V, 1.8V etc., yet " writing " and " wiping " in order to realize information, usually need be far above program voltage and the erasing voltage of supply voltage VDD, for example 8V, 11V etc.Therefore, charge pump system is widely used in the storer, is used for obtaining higher program voltage and erasing voltage by lower supply voltage VDD.
With reference to figure 1, show a kind of synoptic diagram of charge pump unit, described charge pump unit comprises two voltage-boosting stages, wherein, first voltage-boosting stage comprises: first K switch 1 that transfer clock drives, first capacitor C 1 that is connected in described first K switch 1 constitute, the other end of described first capacitor C 1 is driven by the charging clock, and charging clock high level voltage is the lifting voltage V of charge pump system.During charge pump system work, when the charging clock is low level, power supply Vin is by 1 charging of 1 pair first capacitor C of first K switch, after charging finishes, the top crown voltage of first capacitor C 1 is Vin, and when the charging clock was high level, the bottom crown voltage of first capacitor C 1 was V, because electric capacity has the character that the two poles of the earth voltage difference can not be suddenlyd change, this moment, the top crown voltage jump of first capacitor C 1 was V+Vin.Afterwards, first capacitor C 1 is charged to second capacitor C 2 by second switch K2 again ..., like this, electric charge has just passed to the right from the left side.Like this, along with the increase of charge pump progression, electric charge just continuously from the power source transition to the output terminal, thereby obtain having the output voltage V out of high-voltage value.
Fig. 2 has shown charge pump system synoptic diagram in one embodiment in the prior art.As shown in Figure 2, in the prior art, described charge pump system comprises clock oscillation unit 10, clock converting unit 12, clock drive unit 14 and charge pump unit 16, wherein, clock oscillation unit 10 is controlled by supply voltage VDD, is used to produce initial clock signal clk; Clock converting unit 12 is controlled by supply voltage VDD, be used for the clock signal that clock oscillation unit 10 the produces shaping that overlaps, output charging clock signal (CLK1_L, CLK3_L) and transmit clock signal (CLK2_L, CLK4_L); Clock drive unit 14, controlled by supply voltage VDD, be used at receive clock converting unit 12 output ground charging clock signal (CLK1_L, CLK3_L) and transmit clock signal (CLK2_L, CLK4_L) carry out the signal enhancement process after, output charging clock signal (CLK1, CLK3) and transmit clock signal (CLK2 is CLK4) to charge pump unit 16.Wherein, through clock converting unit 12 output ground charging clock signal (CLK1_L, CLK3_L) and transmit clock signal (CLK2_L, CLK4_L) marking current is lower, and the charging clock signal (CLK1 that after clock drive unit 14 is handled, exports, CLK3) and transmit clock signal (CLK2, electric current CLK4) is higher.In the above-described embodiments, owing to be used to control the magnitude of voltage lower (1.08V to 1.98V) of the supply voltage VDD of clock drive unit 14, provide the ability of charging charge and transmission charge just on the weak side, comparatively speaking, charge efficiency and transfer efficiency are also just lower.In addition, because clock drive unit 14 is used to drive two class clock signals (first kind clock signal and the second type clock signal), cause power consumption bigger, therefore needing provides big electric current to clock drive unit 14, but existing supply voltage VDD can't meet the demands.
Fig. 3 has shown charge pump system synoptic diagram in another embodiment in the prior art.As shown in Figure 3, similar with Fig. 2, described charge pump system comprises clock oscillation unit 20, clock converting unit 22, clock drive unit 24 and charge pump unit 26.Especially, the described charge pump system among Fig. 3 also comprises power supply voltage regulation unit 25, is used for the output supply voltage VDDQ_R after adjusting with supply voltage VDDQ, offers clock drive unit 24.This shows that the supply voltage VDD that the supply voltage VDDQ_R in the charge pump system shown in Figure 3 is compared in the charge pump system shown in Figure 2 has bigger magnitude of voltage, and bigger electric current can be provided.But, because clock drive unit 24 still is used to drive two class clock signals (first kind clock signal and the second type clock signal), also can cause power consumption bigger inevitably, therefore power supply voltage regulation unit 25 needs to provide big electric current to clock drive unit 24, this needs the conducting resistance of power supply voltage regulation unit 25 smaller usually, in order to realize less conducting resistance, generally adopt the power supply voltage regulation unit 25 of big breadth length ratio, this can cause the size of power supply voltage regulation unit 25 bigger.Simultaneously, because clock drive unit 24 can extract the electric currents of power supply voltage regulation units 25 in a large number, the tertiary voltage VDDQ_R that power supply voltage regulation unit 25 is exported can descend to some extent, and this can cause the clock high level of clock drive unit 24 outputs to reduce, and can influence the efficient of charge transfer in the charge pump system; The charging clock is lower, then can cause charging clock high level to be lower than the switching voltage of NMOS pipe, makes the charge pump system can't operate as normal.
Summary of the invention
The problem that the present invention solves is charge efficiency and the low problem of transfer efficiency in the existing charge pump system.
For addressing the above problem, the invention provides a kind of charge pump system, comprise: voltage source device, comprise first voltage source and power supply voltage regulation unit that first supply voltage is provided, described power supply voltage regulation unit is used to adjust first supply voltage of described first voltage source output to obtain second source voltage; The clock oscillation unit is used to produce reference clock signal; The clock converting unit is connected with described clock oscillation unit,, is used for converting the reference clock signal that described clock oscillation unit produces to first kind clock signal and the second type clock signal as driving voltage with first supply voltage; With the clock drive unit that described clock converting unit is connected, described clock drive unit comprises: as driving voltage, be used to strengthen the first clock driver element of first kind clock signal with second source voltage; And, with first supply voltage and second source voltage as driving voltage, be used to strengthen the second clock driver element of the second type clock signal, described second clock driver element is with first supply voltage and the second source voltage sum high value as its driving voltage.
Alternatively, described second clock driver element comprises the driving voltage converting unit, described driving voltage converting unit comprises: first phase inverter, electric capacity, second phase inverter, an and PMOS pipe, wherein, the voltage input end of described first phase inverter receives described first supply voltage, the input end of described first phase inverter is connected with the input end of second phase inverter, the output terminal of described first phase inverter links to each other with first electrode of electric capacity, second electrode of described electric capacity and the voltage input end of described second phase inverter, the drain electrode of a described PMOS pipe connects, the output terminal of described second phase inverter is connected with the grid of a described PMOS pipe, and the source electrode of a described PMOS pipe receives described second source voltage.
Alternatively, described second phase inverter comprises the 2nd PMOS pipe and NMOS pipe, the grid of the grid of described the 2nd PMOS pipe and NMOS pipe is connected in the input end of described first phase inverter jointly, the source electrode of described the 2nd PMOS pipe is connected with the drain electrode of a described PMOS pipe, the drain electrode of described the 2nd PMOS pipe is connected with the source electrode of NMOS pipe, the grounded drain of described NMOS pipe.
Alternatively, described first supply voltage offers described clock oscillation unit.
Alternatively, described voltage source device also comprises second voltage source that is used to provide the 3rd supply voltage; Described the 3rd supply voltage offers described clock oscillation unit.
Alternatively, the range of voltage values of described the 3rd supply voltage is 1.08V to 1.98V, and the range of voltage values of described first supply voltage is 2.5 volts to 5.5 volts, and the range of voltage values of described second source voltage is 2.5 volts to 3.6 volts.
Alternatively, described first kind clock signal is the charging clock signal, and the described second type clock signal is a transmit clock signal.
The present invention provides a kind of charge pump system that comprises above-mentioned clock generation circuit in addition, and described charge pump system also comprises charge pump unit, and described clock generation circuit is used for providing the first kind clock signal and the second type clock signal to charge pump unit.
Alternatively, described first kind clock signal is the charging clock signal, and the described second type clock signal is a transmit clock signal.
Compared with prior art, the present invention has the following advantages: will be used to export first clock driver element of first kind clock signal (clock signal of promptly charging) and the discrete setting of second clock driver element that is used to export the second type clock signal (being transmit clock signal), wherein the first clock driver element with second source voltage as driving voltage, current loading is less, can improve charge efficiency; The second clock driver element is made driving voltage with first supply voltage and second source voltage sum, because first supply voltage and second source voltage have high value, can improve transfer efficiency.
Description of drawings
Fig. 1 has shown the circuit theory diagrams of charge pump system in the prior art;
Fig. 2 has shown charge pump system synoptic diagram in one embodiment in the prior art;
Fig. 3 has shown charge pump system synoptic diagram in another embodiment in the prior art;
Fig. 4 has shown the synoptic diagram of charge pump system of the present invention in first embodiment;
Fig. 5 has shown the circuit diagram of second clock driver element 342 shown in Figure 4;
Fig. 6 has shown charge pump system of the present invention synoptic diagram in a second embodiment.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Set forth a lot of details in the following description so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
Just as described in the background section, prior art is used for the charge pump system of storer, be to utilize to be subjected to the same clock drive unit of same supply voltage control to produce charging clock signal and transmit clock signal, can cause the reduction of charge efficiency and/or transfer efficiency.
At the problems referred to above, the invention provides a kind of charge pump system.With reference to figure 4, shown the synoptic diagram in charge pump system one embodiment of the present invention.
As shown in Figure 4, described charge pump system comprises clock generation circuit 3 and the charge pump unit 4 that is connected with clock generation circuit, described clock generation circuit 3 comprises: clock oscillation unit 30, clock converting unit 32, clock drive unit and voltage source device, wherein, described clock drive unit more comprises the first clock driver element 341 and second clock driver element 342, and described voltage source device more comprises first voltage source 31, power supply voltage regulation unit 33 and second voltage source 35.
Power supply voltage regulation unit 33 is connected in first voltage source 31, is used to receive the first supply voltage VDDQ that first voltage source 31 provides and the described first supply voltage VDDQ is adjusted, and is able to the second source voltage VDDQ_R that output ripple is less, magnitude of voltage is higher.
In the present embodiment, the magnitude of voltage of the described first supply voltage VDDQ is greater than the magnitude of voltage of described the 3rd supply voltage VDD, and the magnitude of voltage of described second source voltage VDDQ_R is greater than the magnitude of voltage of described the 3rd supply voltage VDD.Specifically, the range of voltage values of described the 3rd supply voltage is 1.08V to 1.98V, and the range of voltage values of described first supply voltage is 2.5 volts to 5.5 volts, and the range of voltage values of described second source voltage is 2.5 volts to 3.6 volts.
Described clock drive unit is used to strengthen the driving force of clock signal, comprises the first clock driver element 341 and second clock driver element 342.
Particularly, the first clock driver element 341, be connected with clock converting unit 32,, be used for behind charging clock signal clk 1_L, the CLK3_L that receive clock converting unit 32 produces it is carried out charging clock signal clk 1, the CLK3 that output after the signal enhancement process has bigger drive current as driving voltage with second source voltage VDDQ_R.
In the present embodiment, the first clock driver element 341 is provided by second source voltage VDDQ_R special use, because described second source voltage VDDQ_R utilizes power supply voltage regulation unit 33 that the first supply voltage VDDQ is carried out voltage stabilizing and handles the back generation, the ripple of described second source voltage VDDQ_R is less, charging clock signal clk 1, CLK3 that the clock driver element 341 of winning is provided have good stable, can make for example electric capacity in the charge pump unit 4 obtain the stable charging transfer amount, and then finally obtain stable output voltage; Therefore in addition, described second source voltage VDDQ_R has kept the high-voltage value of the first supply voltage VDDQ, makes the voltage of charging clock signal clk 1 that the clock driver element 341 of winning provided, CLK3 higher; Simultaneously, the first clock driver element 341 is exclusively used in provides the charging of charge pump unit 4 clock signal, like this, load current by the first clock driver element 341 of second source voltage VDDQ_R control just can reduce, charging clock signal clk 1, CLK3 can obtain bigger electric current, can charge into more electric charge for for example electric capacity in the charge pump unit 36, corresponding raising charge efficiency.
In addition, the load of power supply voltage regulation unit 33 has only the first clock driver element 341, and load is less relatively, so power supply voltage regulation unit 33 need not the electric current that provides bigger, and the size of power supply voltage regulation unit 33 can meet the demands under less situation.
Second clock driver element 342, be connected with clock converting unit 32,, be used for behind transmit clock signal CLK2_L, the CLK4_L that receive clock converting unit 32 produces it is carried out transmit clock signal CLK2, the CLK4 that output after the signal enhancement process has bigger drive current as driving voltage with the first supply voltage VDDQ and second source voltage VDDQ_R.In actual applications, second clock driver element 342 is with the first supply voltage VDDQ and the second source voltage VDDQ_R sum high value as its driving voltage.
In the present embodiment, second clock driver element 342 is provided jointly by described first supply voltage VDDQ and described second source voltage VDDQ_R.In the present embodiment, described first supply voltage VDDQ and described second source voltage VDDQ_R have high-voltage value, like this, second clock driver element 342 just can obtain the maximum output valve (VDDQ+VDDQ_R) of the first supply voltage VDDQ and described second source voltage VDDQ_R sum as driving voltage; In addition, second clock driver element 342 is exclusively used in the transmit clock signal that charge pump unit 4 is provided, and the load current of second clock driver element 342 just can reduce.So, the transmit clock signal CLK2, the CLK4 that carry out exporting after the signal enhancement process through second clock driver element 342 can obtain bigger electric current, the switch in the conducting charge pump unit better 4 (for example NMOS pipe), corresponding raising transfer efficiency.
Charge pump unit 4, transmit clock signal CLK2, CLK4 booster tension that charging clock signal clk 1, CLK3 and the second clock driver element 342 that is used for providing according to the first clock driver element 341 provides are exported the target voltage more much higher than initial voltage.Described target voltage can for example be program voltage or erasing voltage in storer.Clock oscillation circuit clocking CLK1, CLK2, CLK3, CLK4, the amplitude of described each clock generally equates with supply voltage VDD.
Specifically, and simultaneously with reference to figure 1, with transmit clock signal CLK2, CLK4 respectively as the transfer clock of control first K switch 1 and second switch K2 among Fig. 1, with charging clock signal clk 1, CLK3 respectively as among Fig. 1 to the charging clock of first capacitor C 1, second capacitor C 2.
During charge pump unit 4 work, when transmit clock signal CLK2 is high level, 1 conducting of first K switch; When charging clock signal clk 1 was low level, power supply Vin was by 1 pair first capacitor C of first K switch, 1 charging of conducting, and after charging finished, the top crown voltage of first capacitor C 1 was Vin; And when charging clock signal clk 1 was high level, the bottom crown voltage of first capacitor C 1 was V, because electric capacity has the character that the two poles of the earth voltage difference can not be suddenlyd change, this moment, the top crown voltage jump of first capacitor C 1 was V+Vin.Afterwards, when transmit clock signal CLK4 is high level, second switch K2 conducting; When charging clock signal clk 3 was low level, the top crown voltage V+Vin on first capacitor C 1 charged to second capacitor C 2 by the second switch K2 of conducting, and after charging finished, the top crown voltage of second capacitor C 2 was V+Vin; And when charging clock signal clk 3 was high level, the bottom crown voltage of second capacitor C 2 was V, because electric capacity has the character that the two poles of the earth voltage difference can not be suddenlyd change, this moment, the top crown voltage jump of second capacitor C 2 was 2V+Vin.Like this, electric charge has just passed to the right from the left side, along with the increase of charge pump progression, electric charge just continuously from the power source transition to the output terminal, thereby obtain having the output voltage V out of high-voltage value.
With reference to figure 5, it shows the circuit diagram of middle second clock driver element 342 shown in Figure 4 at an embodiment.Described second clock driver element 342 comprises the driving voltage converting unit, in the present embodiment, the quantity of described driving voltage converting unit is two, be used for being applicable to respectively two transmit clock signals, promptly a driving voltage converting unit is used to receive transmit clock signal CLK2_L, after the signal enhancement process, output transmit clock signal CLK2, another driving voltage converting unit is used to receive transmit clock signal CLK4_L, after the signal enhancement process, output transmit clock signal CLK4.Each described driving voltage converting unit more comprises: first phase inverter 343, electric capacity 344, second phase inverter and PMOS pipe 345.
Particularly, first phase inverter 343 receives the described first supply voltage VDDQ, the input end of first phase inverter 343 is connected with the input end of second phase inverter, is used for the signal input part as the transmit clock signal CLK2_L/CLK4_L of receive clock converting unit 32 generations; The output terminal of first phase inverter 343 links to each other with first electrode of electric capacity 344; Second electrode of electric capacity 344 is connected with the drain electrode of the voltage input end of described second phase inverter, PMOS pipe 345; The output terminal of described second phase inverter is connected with the grid of PMOS pipe 345, is used for the signal output part as output transmit clock signal CLK2/CLK4; The source electrode of a described PMOS pipe receives described second source voltage VDDQ_R.
In the present embodiment, described second phase inverter comprises the 2nd PMOS pipe 346 and NMOS pipe 347, the grid of the grid of the 2nd PMOS pipe 346 and NMOS pipe 347 is connected in the input end of described first phase inverter jointly, is used for the signal input part as described second phase inverter; The source electrode of the 2nd PMOS pipe 346 is connected with the drain electrode of PMOS pipe 345; The source electrode of the 2nd PMOS pipe 346 is used for the voltage input end as described second phase inverter; The drain electrode of the 2nd PMOS pipe 346 is connected with the source electrode of NMOS pipe 347; The grounded drain power supply VSS of NMOS pipe 347.
During 342 work of second clock driver element, the transmit clock signal CLK2_L/CLK4_L that the signal input part receive clock converting unit 32 of second clock driver element 342 produces, when transmit clock signal CLK2_L/CLK4_L is high level, the output end voltage of first phase inverter 343 is a low level, and then the first electrode voltage V1 of electric capacity is a low level; In addition, when transmit clock signal CLK2_L/CLK4_L is high level, NMOS manages 347 conductings, the 2nd PMOS pipe 346 ends, and the signal output part of second clock driver element 342 is a low level, and described low level transfers to the grid of PMOS pipe 345, then a PMOS manages 345 conductings, because it is second source voltage VDDQ_R that a PMOS manages 345 source voltages, then electric capacity 344 second electrode voltage V2 are VDDQ_R, so the voltage at electric capacity 344 two ends is VDDQ_R.
When transmit clock signal CLK2_L/CLK4_L is low level, the output end voltage of first phase inverter 343 is the first supply voltage VDDQ of voltage input end, then the first electrode voltage V1 of electric capacity is VDDQ, because the voltage at electric capacity two ends can not suddenly change, then the second electrode voltage V2 is VDDQ+VDDQ_R; In addition, when transmit clock signal CLK2_L/CLK4_L is low level, NMOS pipe 347 ends, the 2nd PMOS manages 346 conductings, the signal output part of second clock driver element 342 is exported the second electrode voltage V2 (being VDDQ+VDDQ_R), described high level transfers to the grid of PMOS pipe 345, and then PMOS pipe 345 ends.Like this, second clock driver element 342 just can obtain the supply voltage of high value, acquisition has the transmit clock signal CLK2/CLK4 of the high level voltage of high value, can overcome in the charge pump unit 4 the inclined to one side effect of lining as the nmos pass transistor of switch, improves the transfer efficiency of electric charge.
In addition, please continue to consult Fig. 5, in the present embodiment, voltage voltage regulation unit 33 and second clock driver element 342 be combined, also possess the function of mutual compensation.Specifically, transmit clock signal CLK2_L/CLK4_L is during by low uprising, the one PMOS manages 345 conductings, be accumulated in the second electrode voltage V2 electric charge some flow to second source voltage VDDQ_R, thereby can the bucking voltage voltage stabilizer owing to current loading causes voltage drop.
Like this, charge pump for the driving of four phase clock signals, transmission signals CLK2_L, CLK4_L are anti-phase each other, therefore, when the transmission signals CLK2_L in driving voltage converting unit is transmitted backward by high step-down, electric charge, transmission signals CLK4_L in another driving voltage converting unit will be uprised by low, can be used for compensating second source voltage VDDQ_R; Otherwise when the transmission signals CLK4_L in another driving voltage converting unit is transmitted backward by high step-down, electric charge, getting transmission signals CLK2_L in the driving voltage converting unit will be uprised by low, can be used for compensating second source voltage VDDQ_R.In other words, at synchronization, the driving voltage of a driving voltage converting unit output high value is always arranged in second driver element, another driving voltage converting unit is then carried out charge compensation to second source voltage VDDQ_R.This compensation will reduce the waste of electric charge, thereby improves the efficient of charge pump.
To sum up, the invention provides a kind of clock generation circuit and the charge pump system that includes described clock generation circuit, than prior art, the present invention by with the first clock driver element with the discrete setting of second clock driver element and different supply voltages is provided, improve charge efficiency and transfer efficiency, and can make charge pump system have that size is little, the advantage of compact conformation.
Please consult Fig. 6 again, it has shown charge pump system of the present invention synoptic diagram in a second embodiment.As shown in Figure 6, described charge pump system comprises clock generation circuit 3 and the charge pump unit 4 that is connected with clock generation circuit, described clock generation circuit comprises: clock oscillation unit 30, clock converting unit 32, clock drive unit and voltage source device, wherein, described clock drive unit more comprises the first clock driver element 341 and second clock driver element 342, and described voltage source device more comprises first voltage source 31 and power supply voltage regulation unit 33.
Compare with charge pump system shown in Figure 4, in Fig. 6, being used for above-mentioned each unit (comprising clock oscillation unit 30, clock converting unit 32, the first clock driver element 341 and second clock driver element 342) to clock generation circuit 3, what working power was provided is first voltage source 31 and power supply voltage regulation unit 33.Described first voltage source 31 is used to produce the first supply voltage VDDQ, and power supply voltage regulation unit 33 is used for the described first supply voltage VDDQ is adjusted to obtain second source voltage VDDQ_R.Like this, whole charge pump system only needs a voltage source device, makes charge pump system to be applicable to and has enlarged its usable range relatively under the hardware environment that disposes the univoltage source apparatus.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection domain of technical solution of the present invention according to technical spirit of the present invention.
Claims (9)
1. a clock generation circuit is characterized in that, comprising: clock oscillation unit, clock converting unit,
Clock drive unit and voltage source device, wherein,
Voltage source device comprises first voltage source and power supply voltage regulation unit that first supply voltage is provided, and described power supply voltage regulation unit is used to adjust first supply voltage of described first voltage source output to obtain second source voltage;
The clock oscillation unit is used to produce reference clock signal;
The clock converting unit is connected with described clock oscillation unit,, is used for converting the reference clock signal that described clock oscillation unit produces to first kind clock signal and the second type clock signal as driving voltage with first supply voltage;
With the clock drive unit that described clock converting unit is connected, described clock drive unit comprises:
As driving voltage, be used to strengthen the first clock driver element of first kind clock signal with second source voltage;
And, with first supply voltage and second source voltage as driving voltage, be used to strengthen the second clock driver element of the second type clock signal, described second clock driver element is with first supply voltage and the second source voltage sum high value as its driving voltage.
2. clock generation circuit as claimed in claim 1, it is characterized in that described second clock driver element comprises the driving voltage converting unit, described driving voltage converting unit comprises: first phase inverter, electric capacity, second phase inverter and PMOS pipe, wherein
The voltage input end of described first phase inverter receives described first supply voltage, the input end of described first phase inverter is connected with the input end of second phase inverter, the output terminal of described first phase inverter links to each other with first electrode of electric capacity, second electrode of described electric capacity and the voltage input end of described second phase inverter,
The drain electrode of a described PMOS pipe connects, and the output terminal of described second phase inverter is connected with the grid of a described PMOS pipe, and the source electrode of a described PMOS pipe receives described second source voltage.
3. clock generation circuit as claimed in claim 2, it is characterized in that, described second phase inverter comprises the 2nd PMOS pipe and NMOS pipe, the grid of the grid of described the 2nd PMOS pipe and NMOS pipe is connected in the input end of described first phase inverter jointly, the source electrode of described the 2nd PMOS pipe is connected with the drain electrode of a described PMOS pipe, the drain electrode of described the 2nd PMOS pipe is connected with the source electrode of NMOS pipe, the grounded drain of described NMOS pipe.
4. clock generation circuit as claimed in claim 1 is characterized in that, described first supply voltage offers described clock oscillation unit.
5. clock generation circuit as claimed in claim 1 is characterized in that, described voltage source device also comprises second voltage source that is used to provide the 3rd supply voltage; Described the 3rd supply voltage offers described clock oscillation unit.
6. clock generation circuit as claimed in claim 5, it is characterized in that, the range of voltage values of described the 3rd supply voltage is 1.08V to 1.98V, and the range of voltage values of described first supply voltage is 2.5 volts to 5.5 volts, and the range of voltage values of described second source voltage is 2.5 volts to 3.6 volts.
7. clock generation circuit as claimed in claim 1 is characterized in that, described first kind clock signal is the charging clock signal, and the described second type clock signal is a transmit clock signal.
8. one kind comprises the charge pump system as clock generation circuit as described in arbitrary in the claim 1 to 7, described charge pump system also comprises charge pump unit, and described clock generation circuit is used for providing the first kind clock signal and the second type clock signal to charge pump unit.
9. charge pump system as claimed in claim 8 is characterized in that, described first kind clock signal is the charging clock signal, and the described second type clock signal is a transmit clock signal.
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| CN105336368A (en) * | 2014-07-18 | 2016-02-17 | 北京兆易创新科技股份有限公司 | Non-overlapping four-phase clock generation circuit |
| CN106935262A (en) * | 2015-12-29 | 2017-07-07 | 北京兆易创新科技股份有限公司 | A kind of programmed method of memory cell |
| CN116545239A (en) * | 2023-07-06 | 2023-08-04 | 芯耀辉科技有限公司 | Charge pump system, power supply device, memory and electronic equipment |
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| JP2005352497A (en) * | 2005-06-17 | 2005-12-22 | Rohm Co Ltd | Power source unit for driving display device, and display device |
| CN101364118A (en) * | 2007-08-08 | 2009-02-11 | 海力士半导体有限公司 | Regulator and high voltage generator |
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| CN105206297A (en) * | 2014-06-25 | 2015-12-30 | 华邦电子股份有限公司 | Internal voltage generation device |
| CN105206297B (en) * | 2014-06-25 | 2018-12-18 | 华邦电子股份有限公司 | Builtin voltage generation device |
| CN105336368A (en) * | 2014-07-18 | 2016-02-17 | 北京兆易创新科技股份有限公司 | Non-overlapping four-phase clock generation circuit |
| CN105336368B (en) * | 2014-07-18 | 2022-11-18 | 兆易创新科技集团股份有限公司 | Non-overlapping four-phase clock generation circuit |
| CN106935262A (en) * | 2015-12-29 | 2017-07-07 | 北京兆易创新科技股份有限公司 | A kind of programmed method of memory cell |
| CN116545239A (en) * | 2023-07-06 | 2023-08-04 | 芯耀辉科技有限公司 | Charge pump system, power supply device, memory and electronic equipment |
| CN116545239B (en) * | 2023-07-06 | 2024-01-16 | 芯耀辉科技有限公司 | Charge pump system, power supply device, memory and electronic equipment |
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