CN102280127B - Clock generation circuit and charge pump system - Google Patents
Clock generation circuit and charge pump system Download PDFInfo
- Publication number
- CN102280127B CN102280127B CN201010203862.6A CN201010203862A CN102280127B CN 102280127 B CN102280127 B CN 102280127B CN 201010203862 A CN201010203862 A CN 201010203862A CN 102280127 B CN102280127 B CN 102280127B
- Authority
- CN
- China
- Prior art keywords
- clock
- voltage
- clock signal
- supply voltage
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Dc-Dc Converters (AREA)
Abstract
The invention relates to a clock generation circuit and a charge pump system. The clock generation circuit comprises: a voltage source device comprising a first voltage source for providing first power supply voltage and a power supply voltage stabilizing unit, wherein the power supply voltage stabilizing unit is provided for adjusting the first power supply voltage to obtain second power supply voltage; a clock oscillation unit provided for generating a reference clock signal; a clock conversion unit provided for converting the reference clock signal into a first type clock signal and a second type clock signal through adopting the first power supply voltage as the driving voltage; a clock driving apparatus, wherein the clock driving apparatus comprises: a first clock driving unit provided for enhancing the first type clock signal through adopting the second power supply voltage as the driving voltage; a second clock driving unit provided for enhancing the second type clock signal through adopting the first power supply voltage and the second power supply voltage as the driving voltages. Compared to the prior art, with the present invention, the first clock driving unit and the second clock driving unit are arranged respectively and independently, and different power supply voltages are provided, such that charging efficiency and transmission efficiency are improved.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of clock generation circuit and charge pump system.
Background technology
In the information age, information storage is one of most important technology contents in infotech.The storeies such as DRAM, EEPROM, flash memory obtain applying more and more widely.
Based on low-power consumption, requirement cheaply, the supply voltage VDD of storer is conventionally lower, such as 2.5V, 1.8V etc., but in order to realize information " writing " and " wiping ", conventionally need to such as, far above the program voltage of supply voltage VDD and erasing voltage, 8V, 11V etc.Therefore, charge pump system is widely used in storer, obtains higher program voltage and erasing voltage for the supply voltage VDD by lower.
With reference to figure 1, show a kind of schematic diagram of charge pump unit, described charge pump unit comprises two voltage-boosting stages, wherein, first voltage-boosting stage comprises: the first K switch 1 that transfer clock drives, the first capacitor C 1 that is connected in described the first K switch 1 form, the other end of described the first capacitor C 1 is driven by the clock that charges, the lifting voltage V that charging clock high level voltage is charge pump system.When charge pump system work, in the time that charging clock is low level, power supply Vin charges to the first capacitor C 1 by the first K switch 1, after charging finishes, the top crown voltage of the first capacitor C 1 is Vin, and in the time that charging clock is high level, the bottom crown voltage of the first capacitor C 1 is V, because electric capacity has the character that the two poles of the earth voltage difference can not be suddenlyd change, now the top crown voltage jump of the first capacitor C 1 is V+Vin.Afterwards, the first capacitor C 1 is charged to the second capacitor C 2 by second switch K2 again ..., like this, electric charge has just passed to the right from the left side.Like this, along with the increase of charge pump progression, electric charge just continuously from power source transition to output terminal, thereby obtain having the output voltage V out of high-voltage value.
Fig. 2 has shown charge pump system schematic diagram in one embodiment in prior art.As shown in Figure 2, in prior art, described charge pump system comprises clock oscillation unit 10, clock converting unit 12, clock drive unit 14 and charge pump unit 16, wherein, clock oscillation unit 10, is controlled by supply voltage VDD, for generation of initial clock signal clk; Clock converting unit 12, controlled by supply voltage VDD, carry out overlapping shaping for the clock signal that clock oscillation unit 10 is produced, output charging clock signal (CLK1_L, and transmit clock signal (CLK2_L, CLK4_L) CLK3_L); Clock drive unit 14, controlled by supply voltage VDD, for the clock signal (CLK1_L that charges in receive clock converting unit 12 with exporting, and transmit clock signal (CLK2_L CLK3_L), CLK4_L) after, carry out signal and strengthen processing, output charging clock signal (CLK1, CLK3) and transmit clock signal (CLK2, CLK4) are to charge pump unit 16.Wherein, through the clock converting unit 12 clock signal (CLK1_L that charges with exporting, and transmit clock signal (CLK2_L CLK3_L), CLK4_L) marking current is lower, and the charging clock signal (CLK1 exporting after clock drive unit 14 is processed, CLK3) and the electric current of transmit clock signal (CLK2, CLK4) higher.In the above-described embodiments, due to the magnitude of voltage lower (1.08V to 1.98V) of the supply voltage VDD for controlling clock drive unit 14, provide the ability of charging charge and transmission charge just on the weak side, comparatively speaking, charge efficiency and transfer efficiency are also just lower.In addition, because clock drive unit 14 is for driving two class clock signals (first kind clock signal and Second Type clock signal), cause power consumption larger, therefore needing provides larger electric current to clock drive unit 14, but existing supply voltage VDD cannot meet the demands.
Fig. 3 has shown charge pump system schematic diagram in another embodiment in prior art.As shown in Figure 3, similar with Fig. 2, described charge pump system comprises clock oscillation unit 20, clock converting unit 22, clock drive unit 24 and charge pump unit 26.Especially, the described charge pump system in Fig. 3 also comprises power supply voltage regulation unit 25, for by supply voltage VDDQ output supply voltage VDDQ_R after adjusting, offers clock drive unit 24.As can be seen here, the supply voltage VDD that the supply voltage VDDQ_R in the charge pump system shown in Fig. 3 is compared in the charge pump system shown in Fig. 2 has larger magnitude of voltage, and larger electric current can be provided.But, because clock drive unit 24 is still for driving two class clock signals (first kind clock signal and Second Type clock signal), inevitably also can cause power consumption larger, therefore power supply voltage regulation unit 25 need provide larger electric current to clock drive unit 24, this needs the conducting resistance of power supply voltage regulation unit 25 smaller conventionally, in order to realize less conducting resistance, generally adopt the power supply voltage regulation unit 25 of large breadth length ratio, this can cause the size of power supply voltage regulation unit 25 larger.Simultaneously, due to clock drive unit 24 electric currents of extraction power supply voltage regulation units 25 in a large number, the tertiary voltage VDDQ_R that power supply voltage regulation unit 25 is exported can decline to some extent, and this can cause the clock high level that clock drive unit 24 is exported to reduce, and can affect the efficiency of electric charge transmission in charge pump system; Charging clock is lower, can cause the switching voltage of charging clock high level lower than NMOS pipe, and charge pump system cannot normally be worked.
Summary of the invention
The problem that the present invention solves is charge efficiency and the low problem of transfer efficiency in existing charge pump system.
For addressing the above problem, the invention provides a kind of charge pump system, comprise: voltage source device, comprise the first voltage source of the first supply voltage and power supply voltage regulation unit are provided, the first supply voltage that described power supply voltage regulation unit is used for adjusting described the first voltage source output is to obtain second source voltage; Clock oscillation unit, for generation of reference clock signal; Clock converting unit, is connected with described clock oscillation unit, using the first supply voltage as driving voltage, converts first kind clock signal and Second Type clock signal to for the reference clock signal that described clock oscillation unit is produced; With the clock drive unit that described clock converting unit is connected, described clock drive unit comprises: using second source voltage as driving voltage, for strengthening the first clock driver element of first kind clock signal; And, using the first supply voltage and second source voltage as driving voltage, for strengthening the second clock driver element of Second Type clock signal, the high value of described second clock driver element using the first supply voltage and second source voltage sum as its driving voltage.
Alternatively, described second clock driver element comprises driving voltage converting unit, described driving voltage converting unit comprises: the first phase inverter, electric capacity, the second phase inverter, an and PMOS pipe, wherein, the voltage input end of described the first phase inverter receives described the first supply voltage, the input end of described the first phase inverter is connected with the input end of the second phase inverter, the output terminal of described the first phase inverter is connected with the first electrode of electric capacity, the second electrode of described electric capacity and the voltage input end of described the second phase inverter, the drain electrode of a described PMOS pipe connects, the output terminal of described the second phase inverter is connected with the grid of a described PMOS pipe, the source electrode of a described PMOS pipe receives described second source voltage.
Alternatively, described the second phase inverter comprises the 2nd PMOS pipe and NMOS pipe, the grid of the grid of described the 2nd PMOS pipe and NMOS pipe is connected in the input end of described the first phase inverter jointly, the source electrode of described the 2nd PMOS pipe is connected with the drain electrode of a described PMOS pipe, the drain electrode of described the 2nd PMOS pipe is connected with the source electrode of NMOS pipe, the grounded drain of described NMOS pipe.
Alternatively, described the first supply voltage offers described clock oscillation unit.
Alternatively, described voltage source device also comprises the second voltage source for the 3rd supply voltage is provided; Described the 3rd supply voltage offers described clock oscillation unit.
Alternatively, the range of voltage values of described the 3rd supply voltage is 1.08V to 1.98V, and the range of voltage values of described the first supply voltage is 2.5 volts to 5.5 volts, and the range of voltage values of described second source voltage is 2.5 volts to 3.6 volts.
Alternatively, described first kind clock signal is charging clock signal, and described Second Type clock signal is transmit clock signal.
The present invention separately provides a kind of charge pump system that comprises above-mentioned clock generation circuit, and described charge pump system also comprises charge pump unit, and described clock generation circuit is for providing first kind clock signal and Second Type clock signal to charge pump unit.
Alternatively, described first kind clock signal is charging clock signal, and described Second Type clock signal is transmit clock signal.
Compared with prior art, the present invention has the following advantages: will be used for exporting the first clock driver element of first kind clock signal (clock signal of charging) and for exporting the discrete setting of second clock driver element of Second Type clock signal (being transmit clock signal), wherein the first clock driver element is using second source voltage as driving voltage, current loading is less, can improve charge efficiency; Second clock driver element is made driving voltage with the first supply voltage and second source voltage sum, because the first supply voltage and second source voltage have high value, can improve transfer efficiency.
Brief description of the drawings
Fig. 1 has shown the circuit theory diagrams of charge pump system in prior art;
Fig. 2 has shown charge pump system schematic diagram in one embodiment in prior art;
Fig. 3 has shown charge pump system schematic diagram in another embodiment in prior art;
Fig. 4 has shown the schematic diagram of charge pump system of the present invention in the first embodiment;
Fig. 5 has shown the circuit diagram of the second clock driver element 342 shown in Fig. 4;
Fig. 6 has shown charge pump system of the present invention schematic diagram in a second embodiment.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, implemented but the present invention can also adopt other to be different from alternate manner described here, therefore the present invention is not subject to the restriction of following public specific embodiment.
Just as described in the background section, prior art is for the charge pump system of storer, be to utilize to be subject to the same clock drive unit of same supply voltage control to produce charging clock signal and transmit clock signal, can cause the reduction of charge efficiency and/or transfer efficiency.
For the problems referred to above, the invention provides a kind of charge pump system.With reference to figure 4, show the schematic diagram in charge pump system one embodiment of the present invention.
As shown in Figure 4, described charge pump system comprises clock generation circuit 3 and the charge pump unit 4 being connected with clock generation circuit, described clock generation circuit 3 comprises: clock oscillation unit 30, clock converting unit 32, clock drive unit and voltage source device, wherein, described clock drive unit more comprises the first clock driver element 341 and second clock driver element 342, and described voltage source device more comprises the first voltage source 31, power supply voltage regulation unit 33 and second voltage source 35.
The first voltage source 31, for providing the first supply voltage VDDQ.
Power supply voltage regulation unit 33, is connected in the first voltage source 31, for receiving the first supply voltage VDDQ that the first voltage source 31 provides and described the first supply voltage VDDQ being adjusted, is able to the second source voltage VDDQ_R that output ripple is less, magnitude of voltage is higher.
Second voltage source 35, for providing the 3rd supply voltage VDD.
In the present embodiment, the magnitude of voltage of described the first supply voltage VDDQ is greater than the magnitude of voltage of described the 3rd supply voltage VDD, and the magnitude of voltage of described second source voltage VDDQ_R is greater than the magnitude of voltage of described the 3rd supply voltage VDD.Specifically, the range of voltage values of described the 3rd supply voltage is 1.08V to 1.98V, and the range of voltage values of described the first supply voltage is 2.5 volts to 5.5 volts, and the range of voltage values of described second source voltage is 2.5 volts to 3.6 volts.
Clock oscillation unit 30, taking described the 3rd supply voltage VDD as driving voltage, for generation of reference clock signal CLK.
Clock converting unit 32, be connected with clock oscillation unit 30, using the first supply voltage VDDQ as driving voltage, carry out overlapping shaping for reference clock signal that clock oscillation unit 30 is produced, output as charging clock signal to the first clock driver element 341 of first kind clock signal and output as the transmit clock signal of Second Type clock signal to second clock driver element 342.In the present embodiment, now taking four phase clock signals as example, be CLK1_L, CLK3_L as the charging clock signal of first kind clock signal, be CLK2_L and CLK4_L as the transmit clock signal of Second Type clock signal, wherein, charging clock signal clk 1_L, the dutycycle of CLK3_L are not identical with the dutycycle of transmit clock signal CLK2_L, CLK4_L.Charging clock signal clk 1_L, CLK3_L are anti-phase each other, and transmit clock signal CLK2_L, CLK4_L are anti-phase each other.
Described clock drive unit, for strengthening the driving force of clock signal, comprises the first clock driver element 341 and second clock driver element 342.
Particularly, the first clock driver element 341, be connected with clock converting unit 32, using second source voltage VDDQ_R as driving voltage, after charging clock signal clk 1_L, the CLK3_L producing for receive clock converting unit 32, it is carried out exporting and having more charging clock signal clk 1, the CLK3 of large-drive-current after signal enhancing is processed.
In the present embodiment, the first clock driver element 341 is by special the providing of second source voltage VDDQ_R, because described second source voltage VDDQ_R utilizes power supply voltage regulation unit 33, the first supply voltage VDDQ is carried out after voltage stabilizing is processed producing, the ripple of described second source voltage VDDQ_R is less, charging clock signal clk 1, CLK3 that the first clock driver element 341 is provided have good stability, can make for example electric capacity in charge pump unit 4 obtain stable charging transfer amount, and then finally obtain stable output voltage; In addition, described second source voltage VDDQ_R has kept the high-voltage value of the first supply voltage VDDQ, therefore makes the voltage of charging clock signal clk 1 that the first clock driver element 341 provides, CLK3 higher; Simultaneously, the first clock driver element 341 is exclusively used in provides the charging of charge pump unit 4 clock signal, like this, the load current of the first clock driver element 341 of being controlled by second source voltage VDDQ_R just can reduce, charging clock signal clk 1, CLK3 can obtain larger electric current, can be filled with more electric charge, corresponding raising charge efficiency for for example electric capacity in charge pump unit 36.
In addition, the load of power supply voltage regulation unit 33 only has the first clock driver element 341, and load is relatively little, and therefore power supply voltage regulation unit 33 is without providing larger electric current, and the size of power supply voltage regulation unit 33 can meet the demands less in the situation that.
Second clock driver element 342, be connected with clock converting unit 32, using the first supply voltage VDDQ and second source voltage VDDQ_R as driving voltage, after transmit clock signal CLK2_L, the CLK4_L producing for receive clock converting unit 32 to its carry out signal strengthen process after output there is more transmit clock signal CLK2, the CLK4 of large-drive-current.In actual applications, the high value of second clock driver element 342 using the first supply voltage VDDQ and second source voltage VDDQ_R sum as its driving voltage.
In the present embodiment, second clock driver element 342 is provided jointly by described the first supply voltage VDDQ and described second source voltage VDDQ_R.In the present embodiment, described the first supply voltage VDDQ and described second source voltage VDDQ_R have high-voltage value, like this, the maximum output valve (VDDQ+VDDQ_R) that second clock driver element 342 just can obtain the first supply voltage VDDQ and described second source voltage VDDQ_R sum is as driving voltage; In addition, second clock driver element 342 is exclusively used in the transmit clock signal that charge pump unit 4 is provided, and the load current of second clock driver element 342 just can reduce.So, the transmit clock signal CLK2, the CLK4 that carry out exporting after signal strengthens processing through second clock driver element 342 can obtain larger electric current, switch (for example NMOS pipe) in conducting charge pump unit better 4, corresponding raising transfer efficiency.
Charge pump unit 4, the transmit clock signal CLK2, the CLK4 booster tension that provide for the charging clock signal clk 1, CLK3 and the second clock driver element 342 that provide according to the first clock driver element 341, export the target voltage more much higher than initial voltage.Described target voltage can be for example program voltage or erasing voltage in storer.Clock oscillation circuit clocking CLK1, CLK2, CLK3, CLK4, the amplitude of described each clock generally equates with supply voltage VDD.
Specifically, and simultaneously with reference to figure 1, using transmit clock signal CLK2, CLK4 respectively as the transfer clock of controlling the first K switch 1 and second switch K2 in Fig. 1, using charge clock signal clk 1, CLK3 respectively as the charging clock to the first capacitor C 1, the second capacitor C 2 in Fig. 1.
When charge pump unit 4 is worked, in the time that transmit clock signal CLK2 is high level, the first K switch 1 conducting; In the time that charging clock signal clk 1 is low level, power supply Vin charges to the first capacitor C 1 by the first K switch 1 of conducting, and after charging finishes, the top crown voltage of the first capacitor C 1 is Vin; And in the time that charging clock signal clk 1 is high level, the bottom crown voltage of the first capacitor C 1 is V, because electric capacity has the character that the two poles of the earth voltage difference can not be suddenlyd change, now the top crown voltage jump of the first capacitor C 1 is V+Vin.Afterwards, when transmit clock signal CLK4 is high level, second switch K2 conducting; In the time that charging clock signal clk 3 is low level, the top crown voltage V+Vin in the first capacitor C 1 charges to the second capacitor C 2 by the second switch K2 of conducting, and after charging finishes, the top crown voltage of the second capacitor C 2 is V+Vin; And in the time that charging clock signal clk 3 is high level, the bottom crown voltage of the second capacitor C 2 is V, because electric capacity has the character that the two poles of the earth voltage difference can not be suddenlyd change, now the top crown voltage jump of the second capacitor C 2 is 2V+Vin.Like this, electric charge has just passed to the right from the left side, along with the increase of charge pump progression, electric charge just continuously from power source transition to output terminal, thereby obtain having the output voltage V out of high-voltage value.
With reference to figure 5, it shows middle second clock driver element 342 shown in Fig. 4 at the circuit diagram of an embodiment.Described second clock driver element 342 comprises driving voltage converting unit, in the present embodiment, the quantity of described driving voltage converting unit is two, for being applicable to respectively two transmit clock signals, a driving voltage converting unit is used for receiving transmit clock signal CLK2_L, after signal strengthens processing, output transmit clock signal CLK2, another driving voltage converting unit is used for receiving transmit clock signal CLK4_L, after signal strengthens processing, output transmit clock signal CLK4.Described in each, driving voltage converting unit more comprises: the first phase inverter 343, electric capacity 344, the second phase inverter and PMOS pipe 345.
Particularly, the first phase inverter 343 receives described the first supply voltage VDDQ, the input end of the first phase inverter 343 is connected with the input end of the second phase inverter, for the signal input part of the transmit clock signal CLK2_L/CLK4_L that produces as receive clock converting unit 32; The output terminal of the first phase inverter 343 is connected with the first electrode of electric capacity 344; The second electrode of electric capacity 344 is connected with the drain electrode of the voltage input end of described the second phase inverter, a PMOS pipe 345; The output terminal of described the second phase inverter is connected with the grid of a PMOS pipe 345, for the signal output part as output transmit clock signal CLK2/CLK4; The source electrode of a described PMOS pipe receives described second source voltage VDDQ_R.
In the present embodiment, described the second phase inverter comprises the 2nd PMOS pipe 346 and NMOS pipe 347, the grid of the grid of the 2nd PMOS pipe 346 and NMOS pipe 347 is connected in the input end of described the first phase inverter jointly, for the signal input part as described the second phase inverter; The source electrode of the 2nd PMOS pipe 346 is connected with the drain electrode of a PMOS pipe 345; The source electrode of the 2nd PMOS pipe 346 is for the voltage input end as described the second phase inverter; The drain electrode of the 2nd PMOS pipe 346 is connected with the source electrode of NMOS pipe 347; The grounded drain power supply VSS of NMOS pipe 347.
When second clock driver element 342 is worked, the transmit clock signal CLK2_L/CLK4_L that the signal input part receive clock converting unit 32 of second clock driver element 342 produces, in the time that transmit clock signal CLK2_L/CLK4_L is high level, the output end voltage of the first phase inverter 343 is low level, and the first electrode voltage V1 of electric capacity is low level; In addition, in the time that transmit clock signal CLK2_L/CLK4_L is high level, NMOS manages 347 conductings, the 2nd PMOS pipe 346 cut-offs, the signal output part of second clock driver element 342 is low level, described low level transfers to the grid of a PMOS pipe 345, a PMOS manages 345 conductings, be second source voltage VDDQ_R because a PMOS manages 345 source voltages, electric capacity 344 second electrode voltage V2 are VDDQ_R, and therefore the voltage at electric capacity 344 two ends is VDDQ_R.
In the time that transmit clock signal CLK2_L/CLK4_L is low level, the output end voltage of the first phase inverter 343 is the first supply voltage VDDQ of voltage input end, the first electrode voltage V1 of electric capacity is VDDQ, because the voltage at electric capacity two ends can not suddenly change, the second electrode voltage V2 is VDDQ+VDDQ_R; In addition, in the time that transmit clock signal CLK2_L/CLK4_L is low level, 347 cut-offs of NMOS pipe, the 2nd PMOS manages 346 conductings, the signal output part of second clock driver element 342 is exported the second electrode voltage V2 (being VDDQ+VDDQ_R), described high level transfers to the grid of a PMOS pipe 345, PMOS pipe 345 cut-offs.Like this, second clock driver element 342 just can obtain the supply voltage of high value, acquisition has the transmit clock signal CLK2/CLK4 of the high level voltage of high value, can overcome in charge pump unit 4 body bias effect as the nmos pass transistor of switch, improves the transfer efficiency of electric charge.
In addition, please continue to refer to Fig. 5, in the present embodiment, voltage voltage regulation unit 33 and second clock driver element 342 are combined, also possess the function of mutual compensation.Specifically, transmit clock signal CLK2_L/CLK4_L is during by low uprising, the one PMOS manages 345 conductings, be accumulated in the second electrode voltage V2 electric charge some flow to second source voltage VDDQ_R, thereby can bucking voltage voltage stabilizer because current loading causes voltage drop.
Like this, for the charge pump of four phase clock signal drivers, signal transmission CLK2_L, CLK4_L are anti-phase each other, therefore, when signal transmission CLK2_L in a driving voltage converting unit is transmitted backward by high step-down, electric charge, signal transmission CLK4_L in another driving voltage converting unit will be uprised by low, can be used for compensating second source voltage VDDQ_R; Otherwise in the time that the signal transmission CLK4_L in another driving voltage converting unit is transmitted backward by high step-down, electric charge, obtaining signal transmission CLK2_L in a driving voltage converting unit will be uprised by low, can be used for compensating second source voltage VDDQ_R.In other words, at synchronization, always have the driving voltage of a driving voltage converting unit output high value in the second driver element, another driving voltage converting unit is carried out charge compensation to second source voltage VDDQ_R.This compensation will reduce the waste of electric charge, thereby improves the efficiency of charge pump.
To sum up, the invention provides a kind of clock generation circuit and the charge pump system that includes described clock generation circuit, than prior art, the present invention is by by the first clock driver element and the discrete setting of second clock driver element and different supply voltages is provided, improve charge efficiency and transfer efficiency, and can make charge pump system have advantages of that size is little, compact conformation.
Referring again to Fig. 6, it has shown charge pump system of the present invention schematic diagram in a second embodiment.As shown in Figure 6, described charge pump system comprises clock generation circuit 3 and the charge pump unit 4 being connected with clock generation circuit, described clock generation circuit comprises: clock oscillation unit 30, clock converting unit 32, clock drive unit and voltage source device, wherein, described clock drive unit more comprises the first clock driver element 341 and second clock driver element 342, and described voltage source device more comprises the first voltage source 31 and power supply voltage regulation unit 33.
Compared with the charge pump system shown in Fig. 4, in Fig. 6, for the above-mentioned each unit to clock generation circuit 3 (comprising clock oscillation unit 30, clock converting unit 32, the first clock driver element 341 and second clock driver element 342), what working power was provided is the first voltage source 31 and power supply voltage regulation unit 33.Described the first voltage source 31 is for generation of the first supply voltage VDDQ, and power supply voltage regulation unit 33 is for adjusting to obtain second source voltage VDDQ_R to described the first supply voltage VDDQ.Like this, whole charge pump system only needs a voltage source device, makes charge pump system can be applicable to dispose under the hardware environment of univoltage source apparatus, has relatively expanded its usable range.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and amendment to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection domain of technical solution of the present invention.
Claims (8)
1. a clock generation circuit, is characterized in that, comprising: clock oscillation unit, clock converting unit, clock drive unit and voltage source device, wherein,
Voltage source device, comprises the first voltage source of the first supply voltage and power supply voltage regulation unit is provided, and the first supply voltage that described power supply voltage regulation unit is used for adjusting described the first voltage source output is to obtain second source voltage;
Clock oscillation unit, for generation of reference clock signal;
Clock converting unit, is connected with described clock oscillation unit, using the first supply voltage as driving voltage, converts first kind clock signal and Second Type clock signal to for the reference clock signal that described clock oscillation unit is produced;
With the clock drive unit that described clock converting unit is connected, described clock drive unit comprises:
Using second source voltage as driving voltage, for strengthening the first clock driver element of first kind clock signal;
And, using the first supply voltage and second source voltage as driving voltage, for strengthening the second clock driver element of Second Type clock signal, the high value of described second clock driver element using the first supply voltage and second source voltage sum as its driving voltage, described second clock driver element comprises driving voltage converting unit, described driving voltage converting unit comprises: the first phase inverter, electric capacity, the second phase inverter, an and PMOS pipe, wherein, the voltage input end of described the first phase inverter receives described the first supply voltage, the input end of described the first phase inverter is connected with the input end of the second phase inverter, the output terminal of described the first phase inverter is connected with the first electrode of electric capacity, the second electrode of described electric capacity and the voltage input end of described the second phase inverter, the drain electrode of a described PMOS pipe connects, the output terminal of described the second phase inverter is connected with the grid of a described PMOS pipe, the source electrode of a described PMOS pipe receives described second source voltage.
2. clock generation circuit as claimed in claim 1, it is characterized in that, described the second phase inverter comprises the 2nd PMOS pipe and NMOS pipe, the grid of the grid of described the 2nd PMOS pipe and NMOS pipe is connected in the input end of described the first phase inverter jointly, the source electrode of described the 2nd PMOS pipe is connected with the drain electrode of a described PMOS pipe, the drain electrode of described the 2nd PMOS pipe is connected with the source electrode of NMOS pipe, the grounded drain of described NMOS pipe.
3. clock generation circuit as claimed in claim 1, is characterized in that, described the first supply voltage offers described clock oscillation unit.
4. clock generation circuit as claimed in claim 1, is characterized in that, described voltage source device also comprises the second voltage source for the 3rd supply voltage is provided; Described the 3rd supply voltage offers described clock oscillation unit.
5. clock generation circuit as claimed in claim 4, it is characterized in that, the range of voltage values of described the 3rd supply voltage is 1.08V to 1.98V, and the range of voltage values of described the first supply voltage is 2.5 volts to 5.5 volts, and the range of voltage values of described second source voltage is 2.5 volts to 3.6 volts.
6. clock generation circuit as claimed in claim 1, is characterized in that, described first kind clock signal is charging clock signal, and described Second Type clock signal is transmit clock signal.
7. one kind comprises as the charge pump system of clock generation circuit as described in arbitrary in claim 1 to 6, it is characterized in that, described charge pump system also comprises charge pump unit, and described clock generation circuit is for providing first kind clock signal and Second Type clock signal to charge pump unit.
8. charge pump system as claimed in claim 7, is characterized in that, described first kind clock signal is charging clock signal, and described Second Type clock signal is transmit clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010203862.6A CN102280127B (en) | 2010-06-09 | 2010-06-09 | Clock generation circuit and charge pump system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010203862.6A CN102280127B (en) | 2010-06-09 | 2010-06-09 | Clock generation circuit and charge pump system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102280127A CN102280127A (en) | 2011-12-14 |
| CN102280127B true CN102280127B (en) | 2014-07-09 |
Family
ID=45105529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010203862.6A Active CN102280127B (en) | 2010-06-09 | 2010-06-09 | Clock generation circuit and charge pump system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102280127B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105206297B (en) * | 2014-06-25 | 2018-12-18 | 华邦电子股份有限公司 | Builtin voltage generation device |
| CN105336368B (en) * | 2014-07-18 | 2022-11-18 | 兆易创新科技集团股份有限公司 | Non-overlapping four-phase clock generation circuit |
| CN106935262A (en) * | 2015-12-29 | 2017-07-07 | 北京兆易创新科技股份有限公司 | A kind of programmed method of memory cell |
| CN116545239B (en) * | 2023-07-06 | 2024-01-16 | 芯耀辉科技有限公司 | Charge pump system, power supply device, memory and electronic equipment |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364118A (en) * | 2007-08-08 | 2009-02-11 | 海力士半导体有限公司 | Regulator and high voltage generator |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6937517B2 (en) * | 2002-07-18 | 2005-08-30 | Micron Technology, Inc. | Clock regulation scheme for varying loads |
| JP2005352497A (en) * | 2005-06-17 | 2005-12-22 | Rohm Co Ltd | Power source unit for driving display device, and display device |
-
2010
- 2010-06-09 CN CN201010203862.6A patent/CN102280127B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101364118A (en) * | 2007-08-08 | 2009-02-11 | 海力士半导体有限公司 | Regulator and high voltage generator |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2005-352497A 2005.12.22 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102280127A (en) | 2011-12-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104205594B (en) | Charge pump circuit and its operating method comprising multi-gated transistor | |
| CN103270682B (en) | Due to the charge pump system of the shared poor efficiency minimizing of the electric charge between electric capacity | |
| CN101247076B (en) | Voltage doubler and method for outputting current | |
| CN101098105A (en) | Booster circuit | |
| CN109039059B (en) | A kind of efficient multi-mode charge pump | |
| CN103856044B (en) | A kind of charge pump circuit and output voltage Automatic adjustment method thereof | |
| TW522648B (en) | Charge pump circuit | |
| CN101303832B (en) | Power supply circuit, liquid crystal drive device, liquid crystal display device | |
| CN101159412A (en) | Electronic device including boosting circuit | |
| CN102280127B (en) | Clock generation circuit and charge pump system | |
| CN101951144A (en) | Efficient charge pump and working method thereof | |
| CN101114524B (en) | Step-up booster circuit | |
| CN102237788B (en) | Charge pump circuit and memory | |
| TW200426834A (en) | Voltage generating circuit | |
| CN103107695A (en) | Charge pump circuit and memorizer | |
| CN102751867B (en) | PMOS (P-channel Metal Oxide Semiconductor) positive high-voltage charge pump | |
| CN110601528B (en) | Charge pump and storage device | |
| CN104883052A (en) | Lifting capacitance circuit and charge pump | |
| CN102487244A (en) | High voltage generator and method of generating high voltage | |
| CN104091613B (en) | Charge pump system and memory | |
| CN101005236A (en) | Booster circuit | |
| US9225238B2 (en) | Multiple level charge pump generating voltages with distinct levels and associated methods | |
| CN102710122B (en) | Positive high-voltage charge pump | |
| CN102263499B (en) | Clock generation circuit and charge pump system | |
| CN102280997A (en) | Charge pump system and memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140219 |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20140219 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech Park No. 1399 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
|
| TA01 | Transfer of patent application right | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |