CN102237788B - Charge pump circuit and memory - Google Patents
Charge pump circuit and memory Download PDFInfo
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- CN102237788B CN102237788B CN201010168837.9A CN201010168837A CN102237788B CN 102237788 B CN102237788 B CN 102237788B CN 201010168837 A CN201010168837 A CN 201010168837A CN 102237788 B CN102237788 B CN 102237788B
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- charge pump
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Abstract
The invention provides a charge pump circuit and a memory. The charge pump circuit comprises a clock driver and a charge pump unit, wherein the charge pump unit is used for providing voltages for a first type of loads and a second type of loads under the drive of the clock driver; the clock driver comprises a first clock driver and a second clock driver; the drive capacity of the first clock driver is more than that of the second clock driver; the first clock driver is used for driving the charge pump unit to provide the voltages for the first type of loads; and the second clock driver is used for driving the charge pump unit to provide the voltages for the second type of loads. When the charge pump circuit provides voltages for small loads, the clock driver with the weak drive capacity is used; and the clock driver with the weak drive capacity has lower parasitic capacitance due to adopting a small-size device, so the clock driver with the weak drive capacity can be reduced in power consumption when the charge pump circuit provides the voltages for the small loads.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of charge pump circuit and memory.
Background technology
In the information age, information storage is one of most important technology contents in information technology.The memories such as DRAM, EEPROM, flash memory obtain applying more and more widely.
Based on low-power consumption, requirement cheaply, the supply voltage of memory is conventionally lower, such as 2.5V, 1.8V etc., but in order to realize information " writing " and " removing ", conventionally need to such as, far above the program voltage of supply voltage and erasing voltage, 8V or 11V etc.Therefore, charge pump circuit is widely used in memory, obtains higher program voltage, erasing voltage for the supply voltage by lower.
With reference to figure 1, show two-stage Dickson charge pump schematic diagram.As shown in Figure 1, each voltage-boosting stage of Dickson charge pump by the NMOS pipe (grid connects drain electrode) of a diode connection, be connected in the electric capacity formation of NMOS pipe source electrode, the other end of electric capacity is connected in clock oscillation circuit.Wherein, the electric capacity of each voltage-boosting stage is equivalent coupling capacitance, and clock oscillation circuit produces
the not overlapping clock of two-phase, the amplitude of clock generally equates with supply voltage VDD.When charge pump work, when
for low level, power supply V
dDby NMOS pipe, C1 is charged, when
during for high level, C1 top crown voltage jump is 2V
dD, to C2 charging, like this, electric charge has just passed to the right from the left side.And work as
while being low level again, due to the unidirectional general character of diode connection NMOS pipe, electric charge cannot transmit go back to the left side from the right, and like this, along with the increase of charge pump progression, electric charge is just delivered to output from power supply continuously, thereby obtains required high pressure.In prior art, conventionally need clock driver, to control the opening and closing of NMOS pipe.
With reference to figure 2, show prior art and be applied to the schematic diagram of the charge pump circuit of memory.As shown in Figure 2, in prior art, in the programming and erase process of memory, adopt same clock driver 200 and same charge pump unit 100 that program voltage and erasing voltage are provided.Between charge pump unit 100 and memory cell array 400, comprise a selector 300: in programming process, charge pump circuit provides program voltage to memory cell array 400, and selector 300 makes the programming incoming end conducting in output and the memory cell array 400 of charge pump unit 100; In erase process, charge pump circuit provides erasing voltage to memory, and selector 300 makes to wipe incoming end conducting in the output of charge pump unit 100 and memory cell array 400.For described memory cell array 400, its programming incoming end and to wipe incoming end different conventionally, for example, for " floating boom " type memory, programming incoming end is the transistorized source electrode of floating boom, is the transistorized drain electrode of floating boom and wipe incoming end.So, charge pump circuit is providing in the process of program voltage and erasing voltage, and the load that electric charge delivery side of pump connects is different.
Because electric current is extracted in the load meeting of charge pump output, and in order to make charge pump maintenance work, drive current must be greater than load current, this just needs clock driver to have stronger driving force, so that larger drive current to be provided, especially for heavy load, the driving force of corresponding clock driver requires higher.Charge pump circuit as shown in Figure 2 only includes a clock driver, described clock driver is in order to be applicable to drive the different situation of big or small load in programming and erase process, the driving force of clock driver needs enough by force to drive compared with the situation of heavy load, just can meet the demands, and in order to obtain larger driving force, conventionally need the conducting resistance of clock driver smaller, in order to realize less conducting resistance, the general clock driver that adopts large breadth length ratio, but, the parasitic capacitance of large breadth length ratio device can be larger, parasitic capacitance conference causes larger power consumption.
Summary of the invention
The problem that the present invention solves is to provide a kind of charge pump circuit, to improve the problem that power consumption is larger.
For addressing the above problem, the invention provides a kind of charge pump circuit, comprising: clock driver and charge pump unit, wherein, described charge pump unit for providing voltage to the first kind and Second Type load under the driving of clock driver; Described clock driver comprises the first clock driver and second clock driver, and the driving force of described the first clock driver is greater than the driving force of second clock driver, described the first clock driver is used for driving charge pump unit to provide voltage to first kind load, and described second clock driver is used for driving charge pump unit to provide voltage to Second Type load.
Optionally, described charge pump unit is the first charge pump being all connected with second clock driver with the first clock driver.
Optionally, charge pump unit comprises: the first charge pump being connected with the first clock driver and the second charge pump being connected with second clock driver, described the first charge pump provides voltage to first kind load under the first clock driver drives, and described the second charge pump provides voltage to Second Type load under second clock driver drives.
Comprise a memory for described charge pump circuit, described memory also comprises memory cell array, and described clock driver is used for driving charge pump unit to provide program voltage and erasing voltage to memory cell array respectively.
Optionally, the first clock driver drives charge pump unit to provide program voltage to the programming incoming end of memory cell array, and second clock driver drives charge pump unit provides erasing voltage to the incoming end of wiping of memory cell array.
Optionally, the first clock driver drives charge pump unit to provide erasing voltage to the incoming end of wiping of memory cell array, and second clock driver drives charge pump unit provides program voltage to the programming incoming end of memory cell array.
Optionally, described memory also comprises controller and selector, described controller is for providing respectively programming instruction or erasing instruction to the first clock driver and second clock driver, first, second clock driver triggers respectively charge pump circuit unit and provides program voltage or erasing voltage to memory cell array, described controller also provides programming instruction or erasing instruction to selector, described selector is connected with charge pump unit and memory cell array, under the triggering of described programming instruction or erasing instruction, the programming incoming end of the output of corresponding connection charge pump unit and memory cell array or wipe incoming end.
Comprise a memory for described charge pump circuit, described memory also comprises controller, and described controller, for providing programming instruction to the first clock driver and the first charge pump, provides erasing instruction to second clock driver and the second charge pump; Or described controller, for providing erasing instruction to the first clock driver and the first charge pump, provides programming instruction to second clock driver and the second charge pump.
Compared with prior art, the present invention has the following advantages: when providing voltage to little load, adopt the weak clock driver of driving force, and the weak clock driver of driving force is owing to adopting small size device, its parasitic capacitance is less, institute when providing voltage to little load, can reduce power consumption.
Brief description of the drawings
Fig. 1 is prior art Dickson charge pump schematic diagram;
Fig. 2 is the schematic diagram of prior art for the charge pump circuit of memory;
Fig. 3 is the schematic diagram of charge pump circuit one execution mode of the present invention;
Fig. 4 is the schematic diagram of memory one embodiment of the present invention;
Fig. 5 is the schematic diagram of the another embodiment of memory of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, implemented but the present invention can also adopt other to be different from alternate manner described here, therefore the present invention is not subject to the restriction of following public specific embodiment.
Just as described in the background section, prior art is for the charge pump circuit of memory, providing in program voltage and erasing voltage process, use same clock driver, in order to fit memory-aided programming process and erase process simultaneously, the strong clock driver of available technology adopting driving force is to meet the situation of heavy load, in fact, when the output of charge pump circuit is little load, do not need the clock driver of larger driving force.The strong clock driver of described driving force, owing to having larger parasitic capacitance, can cause larger power consumption.
For the problems referred to above, the invention provides a kind of charge pump circuit, with reference to figure 3, show the schematic diagram of charge pump circuit one execution mode of the present invention.
Described charge pump circuit comprises clock driver 203 and charge pump unit 101, wherein,
Clock driver 203 comprises the first clock driver 201 and second clock driver 202, and described the first clock driver 201 is all connected with charge pump unit 101 with described second clock driver 202, is applicable to respectively provide the situation of different voltages.Wherein, the driving force of described the first clock driver 201 is greater than the driving force of described second clock driver 202.
Using heavy load as first kind load, using little load as Second Type load, so, strong the first clock driver 201 of driving force is for driving charge pump unit 101 that the process of voltage is provided to first kind load, and the weak second clock driver 202 of driving force is for driving charge pump unit 101 that the process of voltage is provided to Second Type load.
In prior art, in the time that charge pump circuit provides voltage to little load, still adopt the clock driver that driving force is strong to compare, charge pump circuit provided by the invention, adopting the clock driver a little less than driving force in the time that little load provides voltage, and the weak clock driver of driving force is owing to adopting small size device, and its parasitic capacitance is less, so in the time providing voltage to little load, the existing technical scheme of required power dissipation ratio is much smaller.
Because charge pump circuit is widely used in memory, below in conjunction with the specific embodiment of memory, charge pump circuit of the present invention is elaborated.With reference to figure 4, show the schematic diagram of memory one embodiment.As shown in Figure 4, in the present embodiment, charge pump circuit provides program voltage and erasing voltage to memory, described memory comprises: controller 500, clock driver 203, charge pump unit 101, selector 301 and memory array cell 401, described clock driver 203 comprises Mbus driver 201 and wipes clock driver 202, wherein:
Controller 500, for providing programming instruction or erasing instruction to clock driver 203, selector 301, triggering respectively charge pump circuit provides the process of program voltage or erasing voltage to memory cell array 401.
Clock driver 203, based on the instruction of controller 500, provides driving signal to charge pump unit 101, and wherein, Mbus driver 201, for driving charge pump unit 101 so that program voltage to be provided; Wipe clock driver 202, for driving charge pump unit 101 so that erasing voltage to be provided.Wherein, when program voltage is provided, the output of described charge pump unit 101 is connected with the programming incoming end of memory cell array 401; When erasing voltage is provided, the output of described charge pump unit 101 is connected with the incoming end of wiping of memory cell array 401.In the present embodiment, the load of the programming incoming end of memory cell array 401 is greater than the load of wiping incoming end, using the load of the programming incoming end of memory cell array 401 as first kind load, using the load of wiping incoming end of memory cell array 401 as first kind load.Correspondingly, the driving force of described Mbus driver 201 is greater than the driving force of wiping clock driver 202.
Charge pump unit 101, for the driving signal boost voltage providing according to clock driver 203, reaches after target voltage (program voltage or erasing voltage) export target voltage at the output voltage of charge pump unit 101.
Selector 301, is connected in controller 500, and the programming instruction providing based on controller 500 or erasing instruction are communicated with respectively the output of charge pump unit 101 and the programming incoming end of memory cell array 401 or wipe incoming end.
The course of work of the present embodiment memory is: the memory information of carrying out is write fashionable, controller 500 sends programming instruction to Mbus driver 201 and the selector 301 of clock driver 203, Mbus driver 201 is under the triggering of described programming instruction, send and drive signal to charge pump unit 101, charge pump unit 101 is under the driving of Mbus driver 201, through the multistage process of boosting, reach program voltage (for example 8V), the output output program voltage of charge pump unit 101, selector 301 is under the triggering of described programming instruction, be communicated with the output of charge pump unit 101 and the programming incoming end of memory cell array 401, the output of charge pump unit 101 is to the programming incoming end output program voltage of memory cell array 401, thereby complete the process that memory data writes.
Similarly, in erase process, controller 500 to clock driver 203 wipe clock driver 202 and selector 301 sends erasing instruction, wipe clock driver 202 under the triggering of described programming instruction, send and drive signal to charge pump unit 101, charge pump unit 101 is being wiped under the driving of clock driver 202, through the multistage process of boosting, reach erasing voltage (for example 10V), the output output erasing voltage of charge pump unit 101, selector 301 is under the triggering of described erasing instruction, be communicated with the incoming end of wiping of the output of charge pump unit 101 and memory cell array 401, the output of charge pump unit 101 is exported erasing voltage to memory cell array 401, thereby complete the process of memory erase data message.
In prior art, provide in the erase process of program voltage at the programming incoming end to little load, adopt the strong clock driver of driving force, due to the loss of parasitic capacitance, the efficiency of charge pump circuit when programming (ratio of power output and input power) is lower, is 10%.And in the technical program, clock driver comprise Mbus driver, driving force that driving force is large little wipe clock driver, the load of programming process is less, adopt the Mbus driver that driving force is less, owing to having reduced the loss of parasitic capacitance, when programming, the efficiency of charge pump improves greatly, is 30%～40%.Charge pump circuit of the present invention can also have other embodiment, with reference to figure 5, shows the schematic diagram of the memory that comprises the another embodiment of charge pump circuit.The memory of the present embodiment comprises: controller 501, clock driver 203, charge pump unit 101, memory cell array 401.
The present embodiment part same as the previously described embodiments repeats no more, and the difference of the present embodiment and above-described embodiment is:
Controller 501, only for providing programming instruction or erasing instruction to clock driver 203, triggering respectively charge pump circuit provides the process of program voltage or erasing voltage to memory cell array 401.
Charge pump unit 101 comprises programmed charges pump 103 and wipes charge pump 102.Wherein:
Described programmed charges pump 103 is connected with Mbus driver 201, and meanwhile, the output of described programmed charges pump 103 is directly connected with the programming incoming end of memory cell array 401.
Describedly wipe charge pump 102 and wipe clock driver 202 and be connected, meanwhile, described in wipe the output of charge pump 102 and the incoming end of wiping of memory cell array 401 is directly connected.
In programming process, under the driving of Mbus driver 201, programmed charges pump 103 reaches program voltage through the process of boosting, and to programming incoming end output program voltage; In erase process, wiping under the driving of clock driver 202, wiping charge pump 102 and reach erasing voltage through the process of boosting, and to wiping incoming end output erasing voltage.
In the present embodiment, the load of programmed charges pump 103 outputs is greater than the load of wiping charge pump 102 outputs, and correspondingly, the driving force of described Mbus driver 201 is greater than the driving force of wiping clock driver 202.Owing to wiping, the driving force of clock driver 202 is relatively little, and the size of wiping clock driver 202 is less, thereby it is less to wipe the parasitic capacitance of clock driver 202, and then has reduced the power consumption in erase process.
In the present embodiment, programmed charges pump 103 with wipe charge pump 102 respectively with the programming input of memory cell array 400 with wipe input and be directly connected, shown in picture Fig. 4, be communicated with charge pump and memory cell array by selector, thereby simplify the structure.
It should be noted that, in above-described embodiment, the load that is greater than charge pump in erase process taking the load of charge pump in programming process is example, but, the present invention is not limited thereto, due to " programming " of memory cell array, " wipe " mechanism difference, in programming process, the load of charge pump may be less than the charge pump load in erase process, in this case, using the load of wiping incoming end as first kind load, with using programming incoming end load as Second Type load, correspondingly, the driving force of wiping clock driver is greater than the driving force of Mbus driver, those skilled in the art can be according to the description of above-described embodiment, modify, distortion and replacement.
It should be noted that, in charge pump circuit provided by the invention, adopt the strong clock driver of driving force to be used for driving heavy load, adopt the weak clock driver of driving force to be used for driving little load.In the time selecting clock driver, can, first according to the efficiency of loading condition and clock driver, select to be applicable to the clock driver of described loading condition.
To sum up, charge pump circuit provided by the invention comprises Mbus driver and wipes clock driver, when providing voltage to little load, adopt the weak clock driver of driving force, and the weak clock driver of driving force is owing to adopting small size device, its parasitic capacitance is less, and institute is when providing voltage to little load, and required power consumption is smaller.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and amendment to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (8)
1. a charge pump circuit, is characterized in that, comprising: clock driver and charge pump unit, and wherein, described charge pump unit for providing voltage to the first kind and Second Type load under the driving of clock driver; Described first kind load is greater than described Second Type load;
Described clock driver comprises the first clock driver and second clock driver, and the driving force of described the first clock driver is greater than the driving force of second clock driver, described the first clock driver is used for driving charge pump unit to provide voltage to first kind load, and described second clock driver is used for driving charge pump unit to provide voltage to Second Type load.
2. charge pump circuit as claimed in claim 1, is characterized in that, described charge pump unit is the first charge pump being all connected with second clock driver with the first clock driver.
3. charge pump circuit as claimed in claim 1, it is characterized in that, charge pump unit comprises: the first charge pump being connected with the first clock driver and the second charge pump being connected with second clock driver, described the first charge pump provides voltage to first kind load under the first clock driver drives, and described the second charge pump provides voltage to Second Type load under second clock driver drives.
4. a memory that comprises charge pump circuit described in claim 1 or 2, described memory also comprises memory cell array, described clock driver is used for driving charge pump unit to provide program voltage and erasing voltage to memory cell array respectively.
5. memory as claimed in claim 4, it is characterized in that, the first clock driver drives charge pump unit to provide program voltage to the programming incoming end of memory cell array, and second clock driver drives charge pump unit provides erasing voltage to the incoming end of wiping of memory cell array.
6. memory as claimed in claim 4, it is characterized in that, the first clock driver drives charge pump unit to provide erasing voltage to the incoming end of wiping of memory cell array, and second clock driver drives charge pump unit provides program voltage to the programming incoming end of memory cell array.
7. the memory of charge pump circuit as claimed in claim 4, it is characterized in that, described memory also comprises controller and selector, described controller is for providing respectively programming instruction or erasing instruction to the first clock driver and second clock driver, first, second clock driver triggers respectively charge pump unit and provides program voltage or erasing voltage to memory cell array, described controller also provides programming instruction or erasing instruction to selector, described selector is connected with charge pump unit and memory cell array, under the triggering of described programming instruction or erasing instruction, the programming incoming end of the output of corresponding connection charge pump unit and memory cell array or wipe incoming end.
8. one kind comprises the memory of charge pump circuit described in claim 3, described memory also comprises controller, described controller, for providing programming instruction to the first clock driver and the first charge pump, provides erasing instruction to second clock driver and the second charge pump; Or described controller, for providing erasing instruction to the first clock driver and the first charge pump, provides programming instruction to second clock driver and the second charge pump.
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| CN201010168837.9A CN102237788B (en) | 2010-04-29 | 2010-04-29 | Charge pump circuit and memory |
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| CN201010168837.9A CN102237788B (en) | 2010-04-29 | 2010-04-29 | Charge pump circuit and memory |
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| CN102237788B true CN102237788B (en) | 2014-12-10 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105551523A (en) * | 2015-12-10 | 2016-05-04 | 北京兆易创新科技股份有限公司 | NAND memory and device thereof for balancing WL voltage establishment time |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137181B (en) * | 2013-02-25 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | Memory, the programmed method of storage array and voltage provide system |
| CN103812332B (en) * | 2014-03-05 | 2016-04-13 | 上海华虹宏力半导体制造有限公司 | A kind of charge pump circuit and memory |
| CN104967307B (en) * | 2015-06-23 | 2017-12-19 | 北京兆易创新科技股份有限公司 | The clock driving method and system of a kind of charge pump |
| CN109842290A (en) * | 2017-11-24 | 2019-06-04 | 北京兆易创新科技股份有限公司 | A kind of high pressure bleeder circuit, charge pump circuit and NOR FLASH |
| CN112636587B (en) * | 2020-12-30 | 2022-03-08 | 芯天下技术股份有限公司 | Charge pump circuit and nonvolatile memory |
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| CN1477773A (en) * | 2003-07-11 | 2004-02-25 | 清华大学 | Electric charge pump circuit based on coupling capacitance share |
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| US6937517B2 (en) * | 2002-07-18 | 2005-08-30 | Micron Technology, Inc. | Clock regulation scheme for varying loads |
| EP1677308A1 (en) * | 2005-01-03 | 2006-07-05 | STMicroelectronics S.r.l. | Low-ripple boosted voltage generator |
| JP2008146772A (en) * | 2006-12-12 | 2008-06-26 | Toshiba Corp | Semiconductor memory |
| US7683700B2 (en) * | 2008-06-25 | 2010-03-23 | Sandisk Corporation | Techniques of ripple reduction for charge pumps |
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| CN1477773A (en) * | 2003-07-11 | 2004-02-25 | 清华大学 | Electric charge pump circuit based on coupling capacitance share |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105551523A (en) * | 2015-12-10 | 2016-05-04 | 北京兆易创新科技股份有限公司 | NAND memory and device thereof for balancing WL voltage establishment time |
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