CN104967307B - The clock driving method and system of a kind of charge pump - Google Patents
The clock driving method and system of a kind of charge pump Download PDFInfo
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- CN104967307B CN104967307B CN201510350919.8A CN201510350919A CN104967307B CN 104967307 B CN104967307 B CN 104967307B CN 201510350919 A CN201510350919 A CN 201510350919A CN 104967307 B CN104967307 B CN 104967307B
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Abstract
The embodiments of the invention provide the clock driving method and system of a kind of charge pump, method therein specifically includes：Output according to enable signal and external clock control trigger；Wherein, the output end of the trigger is connected with the drive device of the charge pump, and the clock signal that the trigger exports is delivered into the drive device；Wherein, the step of output of the foundation enable signal and external clock control trigger includes：When the enable signal is low level, keep the output of the trigger constant.The embodiment of the present invention can make charge pump be stopped in time, improve the performance of charge pump.
Description
Technical field
The present invention relates to electronic technology field, clock driving method and a kind of charge pump more particularly to a kind of charge pump
Clock drive system.
Background technology
With the rapid development of electronic technology, charge pump, as a kind of important electronic component, being widely used in needs
In the system for wanting battery, for example it can apply in cellular phone, Bluetooth system and portable electric appts.
Charge pump needs continuous pulse signal to promote electric charge to be operated.Pulse signal is overturn, then charge pump,
Voltage is produced in output end and outwards conveys electric current；Pulse signal stops upset, then charge pump is stopped, that is, stops outwards defeated
Power transmission stream.Clock is used in engineering as above-mentioned pulse signal.
Reference picture 1, a kind of structural representation of the clock drive system of existing charge pump is shown, can specifically be included：
With gate circuit 1, not circuit 2, drive device 3 and drive device 4；Wherein, CLK is clock caused by external oscillator；EN is
Enable signal, it is the indication signal of the working condition of charge pump, when EN is high level, then it represents that charge pump needs to start；Work as EN
For low level, then it represents that the output voltage of charge pump has reached preset voltage value, it is necessary to stop the upset of clock, and charge pump needs
It is stopped；CLK1 and CLK2 is a pair of reverse clocks for directly driving charge pump；CLK and EN respectively from gate circuit
1 two inputs input, the output signal with gate circuit 1 is as drive device 3 and the input signal of not circuit 2, NOT gate
The output signal CLK1 of input signal of the output signal of circuit 2 as drive device 4, drive device 3 and drive device 4 and
CLK2 is respectively as just anticlockwise needed for charge pump.
However, EN and CLK is delivered to CLK1 and CLK2 process from gate circuit and needs the time in Fig. 1, this causes EN
When being changed into low level, CLK1 and CLK2 can not stop overturning in time, so as to which charge pump can not be stopped in time.
Reference picture 2, the timing diagram of traditional charge pump clock drive system shown in Fig. 1 is shown, wherein, EN is in T4
Low level is converted to control charge pump to be stopped by high level, however, EN and CLK with gate circuit 1, not circuit 2, drive
Propagation delay time in dynamic device 3 and drive device 4 causes CLK1 and CLK2 to stop overturning not at T4, but stops at T5
Only overturn, also, CLK1 and CLK2 have carried out once inside out again between T4 and T5, therefore charge pump is also working after T4,
That is, the accurate control of charge pump can not be realized.
The content of the invention
Technical problem to be solved of the embodiment of the present invention is to provide a kind of clock driving method of charge pump, makes charge pump
It is stopped in time, improves the performance of charge pump.
Accordingly, the embodiment of the present invention additionally provides a kind of clock drive system of charge pump, to ensure the above method
Realization and application.
In order to solve the above problems, the invention discloses a kind of clock driving method of charge pump, including：
Output according to enable signal and external clock control trigger；Wherein, the output end of the trigger with it is described
The drive device of charge pump is connected, and the clock signal that the trigger exports is delivered into the drive device；
Wherein, the step of output of the foundation enable signal and external clock control trigger includes：Described enabled
When signal is low level, keep the output of the trigger constant.
Preferably, the step of output of the foundation enable signal and external clock control trigger also includes：Described
When enable signal is high level, the output of the trigger is controlled to follow the external clock.
Preferably, it is described when the enable signal is low level, keep the constant step of the output of the trigger, bag
Include：
The output of the first gate circuit and the second gate circuit is controlled according to the enable signal and the external clock, described
When enable signal is low level, the output of first gate circuit and second gate circuit is low level；Wherein, described
The input of one gate circuit terminates the enable signal and external clock, and the input of second gate circuit terminates the external clock
With reverse, the output end and the input phase of the trigger of first gate circuit and the second gate circuit of the enable signal
Even；
According to the output of trigger described in the output control of first gate circuit and the second gate circuit, at described first
When the output of circuit and second gate circuit is low level, keep the output of the trigger constant.
Preferably, it is described when the enable signal is high level, control the output of the trigger to follow the outside
The step of clock, including：
The output of the 3rd gate circuit and the 4th gate circuit is controlled according to the enable signal and the external clock, described
When enable signal is high level, the output of at least one of the 3rd gate circuit and described 4th gate circuit is high level；Its
In, the input of the 3rd gate circuit terminates the enable signal and external clock, the input termination institute of the 4th gate circuit
State reverse, the output end of the 3rd gate circuit and output end and the institute of the 4th gate circuit of external clock and the enable signal
The input for stating trigger is connected；
According to the output of trigger described in the output control of the 3rd gate circuit and the 4th gate circuit, described
When the output of at least one of three gate circuits and the 4th gate circuit is high level, the output of the trigger is controlled to follow institute
State external clock.
Preferably, it is described when the enable signal is low level, keep the constant step of the output of the trigger also
Including：
The output of the 5th gate circuit and the 6th gate circuit is controlled according to the enable signal and the external clock, described
When enable signal is low level, the output of the 5th gate circuit and the 6th gate circuit is high level；Wherein, described 5th
The input of circuit terminates the enable signal and external clock, and the input of the 6th gate circuit terminates the external clock and institute
The reverse of enable signal is stated, the output end of the 5th gate circuit and the 6th gate circuit is connected with the input of the trigger；
According to the output of trigger described in the output control of the 5th gate circuit and the 6th gate circuit, at described 5th
When the output of circuit and the 6th gate circuit is high level, keep the output of the trigger constant.
Preferably, it is described when the enable signal is high level, control the output of the trigger to follow the outside
The step of clock, including：
The output of the 7th gate circuit and the 8th gate circuit is controlled according to the enable signal and the external clock, described
When enable signal is high level, the output of at least one of the 7th gate circuit and described 8th gate circuit is low level；Its
In, the input of the 7th gate circuit terminates the enable signal and external clock, the input termination institute of the 8th gate circuit
State reverse, the output end of the 7th gate circuit and output end and the institute of the 8th gate circuit of external clock and the enable signal
The input for stating trigger is connected；
According to the output of trigger described in the output control of the 7th gate circuit and the 8th gate circuit, the described 7th
When the output of at least one of gate circuit and the 8th gate circuit is low level, control the trigger output follow it is described
External clock.
On the other hand, the invention also discloses a kind of clock drive system of charge pump, including：Controller and trigger；
Wherein, the controller is used for the output according to enable signal and external clock control trigger；Wherein, it is described to touch
The output end of hair device is connected with the drive device of the charge pump, the clock signal that the trigger exports is delivered to described
Drive device；
Wherein, the controller includes：First control module, for when the enable signal is low level, keeping institute
The output for stating trigger is constant.
Preferably, the controller also includes：
Second control module, for when the enable signal is high level, controlling the output of the trigger to follow institute
State external clock.
Preferably, first control module, including：First gate circuit and the second gate circuit；First gate circuit
Input terminates the enable signal and external clock, and the input of second gate circuit terminates the external clock and described enabled
Signal it is reverse, the output end of first gate circuit and the second gate circuit is connected with the input of the trigger；
Wherein, when the output of first gate circuit and second gate circuit is low level, the trigger is protected
It is constant to hold output.
Preferably, second control module, including：3rd gate circuit and the 4th gate circuit；3rd gate circuit
Input terminates the enable signal and external clock, and the input of the 4th gate circuit terminates the external clock and described enabled
Signal it is reverse, the output end of the 3rd gate circuit and the 4th gate circuit is connected with the input of the trigger；
Wherein, it is described when the output of at least one of the 3rd gate circuit and the 4th gate circuit is high level
The output of trigger follows the external clock.
Preferably, first control module, including：5th gate circuit and the 6th gate circuit；5th gate circuit
Input terminates the enable signal and the external clock, and the input of the 6th gate circuit terminates the external clock and described
Enable signal it is reverse, the output end of the 5th gate circuit and the 6th gate circuit is connected with the input of the trigger；
Wherein, when the output of the 5th gate circuit and the 6th gate circuit is high level, the trigger keeps defeated
Go out constant.
Preferably, second control module, including：7th gate circuit and the 8th gate circuit；7th gate circuit
Input terminates the enable signal and external clock, and the input of the 8th gate circuit terminates the external clock and described enabled
Reverse, the output end of the 7th gate circuit and the output end and the input phase of the trigger of the 8th gate circuit of signal
Even；
Wherein, it is described when the output of at least one of the 7th gate circuit and the 8th gate circuit is low level
The output of trigger follows the external clock.
Compared with prior art, the embodiment of the present invention includes advantages below：
For the embodiment of the present invention after enable signal is changed into low level, the clock signal of trigger output is maintained at low level
Or high level is constant, i.e. the clock signal of trigger output no longer carries out the upset between high level and low level, therefore energy
The clock signal after low enable signal is sent enough is avoided still to overturn and so that the phenomenon that charge pump works on so that electric charge
Pump is stopped in time, so as to realize being precisely controlled for charge pump.Further, the feelings being stopped in time in charge pump
Under condition, the voltage of charge pump output is not above preset voltage value, overshoot during charge pump is reduced, so as to reduce line
Ripple, the performance of charge pump is set to be improved.
Brief description of the drawings
Fig. 1 is a kind of structural representation of the clock drive system of existing charge pump；
Fig. 2 is the timing diagram of charge pump clock drive system shown in Fig. 1；
Fig. 3 is provided in an embodiment of the present invention a kind of when enable signal is low level, keeps the output of trigger constant
Method step flow chart；
Fig. 4 is provided in an embodiment of the present invention a kind of when enable signal is low level, keeps the output of trigger constant
Method step flow chart；
A kind of step flow chart of the clock-driven method of Fig. 5 charge pumps provided in an embodiment of the present invention；
Fig. 6 is provided in an embodiment of the present invention a kind of when enable signal is high level, and the output of control trigger follows
The step flow chart of the method for external clock；
Fig. 7 is provided in an embodiment of the present invention a kind of when enable signal is high level, and the output of control trigger follows
The step flow chart of the method for external clock；
Fig. 8 is a kind of timing diagram of the clock driving method of charge pump provided in an embodiment of the present invention；
Fig. 9 is a kind of structure chart of the clock drive system of charge pump provided in an embodiment of the present invention；
Figure 10 is a kind of structural representation of the clock drive system of charge pump provided in an embodiment of the present invention；
Figure 11 is a kind of structural representation of the clock drive system of charge pump provided in an embodiment of the present invention；And
Figure 12 is a kind of structure chart of the clock drive system of charge pump provided in an embodiment of the present invention.
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, it is below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is further detailed explanation.
Embodiment one
The clock-driven method for a kind of charge pump that the embodiment of the present invention one provides, according to enable signal and external clock
The output of control trigger, when enable signal is low level, keep the output of trigger constant；Wherein, the output of trigger
End is connected with the drive device of charge pump, and the clock signal that trigger is exported is delivered to drive device.
The embodiment of the present invention keeps the output of trigger constant when enable signal is low level, i.e., turns in enable signal
Be changed to after low level, before output and the enable signal of trigger are converted to low level the output of trigger be consistent, example
Such as, if the output that enable signal is converted to trigger before low level is high level, after enable signal is converted to low level,
The output of trigger is still high level；And for example, if the output of trigger is low level before enable signal is converted to low level,
After enable signal is converted to low level, the output of trigger is still low level.
To sum up, the clock driving method of a kind of charge pump provided in an embodiment of the present invention, due to being changed into enable signal
After low level, the clock signal of trigger output is maintained at low level or high level is constant, i.e. the clock letter of trigger output
The upset between high level and low level number is no longer carried out, therefore clock signal can be avoided after low enable signal is sent still
The phenomenon for so overturning and causing charge pump to work on so that charge pump is stopped in time, so as to realize charge pump
It is precisely controlled.Further, in the case where charge pump is stopped in time, the voltage of charge pump output is not above default electricity
Pressure value, overshoot during charge pump is reduced, so as to reduce ripple, the performance of charge pump is improved.
The present invention can provide when enable signal is low level, keeps the constant technical side of the output of trigger as follows
Case：
Option A 1
Reference picture 3, one kind provided in an embodiment of the present invention is given when enable signal is low level, keeps trigger
The step flow chart of constant method is exported, specifically may include steps of：
Step 301, the output according to enable signal and external clock the first gate circuit of control and the second gate circuit, enabled
When signal is low level, the output of the first gate circuit and the second gate circuit is low level；Wherein, the input of the first gate circuit
Connect enable signal and external clock, the input termination external clock of the second gate circuit and reverse, the first gate circuit of enable signal
It is connected with the output end of the second gate circuit with the input of trigger；
It should be noted that enable signal is the indication signal of the working condition of charge pump, enable signal is high level, table
Show that charge pump needs to start, clock needs to be overturn；Enable signal is low level, represents that the output voltage of charge pump has reached
To preset voltage value, it is necessary to stop the upset of clock, charge pump needs to be stopped.
In one kind application example of the present invention, the first gate circuit can be and gate circuit, the second gate circuit can be or
Not circuit.Specifically, the input of the first gate circuit can connect enable signal and external clock, the input of the second gate circuit
Connect reverse, the output end of the first gate circuit and the second gate circuit and the input phase of trigger of external clock and enable signal
Even.
It is appreciated that it with gate circuit, the second gate circuit can be that OR-NOT circuit is that above-mentioned first gate circuit, which can be,
As a kind of example of the first gate circuit and the second gate circuit, and the application limitation of the embodiment of the present invention is not understood to, in fact,
When it is low level to have an input signal, output signal be low level any first gate circuit and the second gate circuit be can
Capable, all gate circuits that above-mentioned function can be achieved are within the protection domain of the embodiment of the present invention.
Step 302, the output according to the first gate circuit and the output control trigger of the second gate circuit, in the first gate circuit
When output with the second gate circuit is low level, keep the output of trigger constant.
In actual applications, trigger can be rest-set flip-flop.Wherein the R ends of rest-set flip-flop are first input end, and S ends are
Second input, Q ends are the first output end, and Qb ends are the second output end.The output end of first gate circuit and the of rest-set flip-flop
One input is connected, and the output end of the second gate circuit is connected with the second input of rest-set flip-flop.
Reference table 1, show a kind of example of the truth table of rest-set flip-flop of the present invention.
Table 1
| First input end | Second input | First output end | Second output end |
| 0 | 0 | Keep | Keep |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | Forbid | Forbid |
As can be seen that when the first input end of rest-set flip-flop and the input signal of the second input are low level, i.e.,
When the output of one gate circuit and the second gate circuit is low level, the first output end and second output end of rest-set flip-flop are kept
Export constant.
Keep the output of the first output end and the second output end of rest-set flip-flop constant, if specifically, enable signal is changed
Output for the first output end and the second output end of rest-set flip-flop before low level is high level, then enable signal is converted to
After low level, the output of the first output end and the second output end of rest-set flip-flop is equal high level；If enable signal is converted to
The output of the first output end and the second output end of rest-set flip-flop is low level before low level, then enable signal is converted to low
After level, the output of the first output end and the second output end of rest-set flip-flop is low level.Therefore, enable signal is changed into
After low level, the clock signal of the output end of rest-set flip-flop first and the output of the second output end is held in high level or low electricity
It is flat constant.
It should be noted that the first output end of rest-set flip-flop is connected with first driving means, the second of rest-set flip-flop is defeated
Go out end with the second drive device to be connected, the first clock signal that the output end of rest-set flip-flop first exports is passed into the first driving
Device, the second clock signal that the second output end of rest-set flip-flop exports is passed into the second drive device.And the first driving dress
Processing can be amplified to the first clock signal and second clock signal respectively with the second drive device by putting, and by after amplification
First clock signal and second clock signal are supplied to charge pump.
The first clock signal and second clock signal come due to trigger transmission are held in high level or low level
Constant, therefore the first clock signal and second clock signal, receive first without the upset between high level and low level
Clock signal and the charge pump of second clock signal do not continue to work, can be stood after enable signal is converted to low level
It is stopped.
Option A 2
Reference picture 4, show that one kind provided in an embodiment of the present invention when enable signal is low level, keeps trigger
The step flow chart of constant method is exported, specifically may include steps of：
Step 401, the output according to enable signal and external clock the 5th gate circuit of control and the 6th gate circuit, enabled
When signal is low level, the output of the 5th gate circuit and the 6th gate circuit is high level；Wherein, the input of the 5th gate circuit
Connect enable signal and external clock, the input termination external clock of the 6th gate circuit and reverse, the 5th gate circuit of enable signal
It is connected with the output end of the 6th gate circuit with the input of trigger；
In one kind application example of the present invention, the 5th gate circuit can be NAND gate circuit, and the 6th gate circuit can be
OR circuit.Specifically, the input termination enable signal and external clock of the 5th gate circuit, the input termination of the 6th gate circuit is outer
Portion's clock and enable signal it is reverse, the output end of the 5th gate circuit and the 6th gate circuit is connected with the input of trigger.
It is appreciated that it with gate circuit, the 6th gate circuit can be that OR-NOT circuit is that above-mentioned 5th gate circuit, which can be,
As a kind of example of the 5th gate circuit and the 6th gate circuit, and the application limitation of the embodiment of the present invention is not understood to, in fact,
When it is low level to have an input signal, output signal be low level any 5th gate circuit and the 6th gate circuit be can
Capable, all gate circuits that above-mentioned function can be achieved are within the protection domain of the embodiment of the present invention.
Step 402, the output according to the 5th gate circuit and the output control trigger of the 6th gate circuit, in the 5th gate circuit
When output with the 6th gate circuit is high level, keep the output of trigger constant.
In actual applications, trigger can be rest-set flip-flop.Wherein the R ends of rest-set flip-flop are the 5th input, and S ends are
6th input, Q ends are the 5th output end, and Qb ends are the 6th output end.The output end of 5th gate circuit and the of rest-set flip-flop
Five inputs are connected, and the output end of the 6th gate circuit is connected with the 6th input of rest-set flip-flop.
Reference table 2, show a kind of example of the truth table of rest-set flip-flop of the present invention.
Table 2
| 5th input | 6th input | 5th output end | 6th output end |
| 1 | 1 | Keep | Keep |
| 1 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 |
| 0 | 0 | Forbid | Forbid |
As can be seen that when the 5th input of rest-set flip-flop and the input signal of the 6th input are high level, i.e.,
When the output of five gate circuits and the 6th gate circuit is high level, the 5th output end and the 6th output end of rest-set flip-flop are kept
Export constant.
Keep the output of the 5th output end and the 6th output end of rest-set flip-flop constant, if specifically, enable signal is changed
Output for the 5th output end and the 6th output end of rest-set flip-flop before low level is high level, then enable signal is converted to
After low level, the output of the 5th output end and the 6th output end of rest-set flip-flop is equal high level；If enable signal is converted to
The output of the 5th output end and the 6th output end of rest-set flip-flop is low level before low level, then enable signal is converted to low
After level, the output of the 5th output end and the 6th output end of rest-set flip-flop is low level.Therefore, enable signal is changed into
After low level, the clock signal of the output end of rest-set flip-flop the 5th and the output of the 6th output end is held in high level or low electricity
It is flat constant.
It should be noted that the 5th output end of rest-set flip-flop is connected with the 5th drive device, the 6th of rest-set flip-flop is defeated
Go out end with the 6th drive device to be connected, the 5th clock signal that the output end of rest-set flip-flop the 5th exports is passed into the 5th driving
Device, the 6th clock signal that the 6th output end of rest-set flip-flop exports is passed into the 6th drive device.And the 5th driving
Device and the 6th drive device can be amplified processing to the 5th clock signal and the 6th clock signal respectively, and by after amplification
The 5th clock signal and the 6th clock signal be supplied to charge pump.
The 5th clock signal and the 6th clock signal is held in high level or low level is constant that trigger transmission comes,
Therefore 5th clock signal and the 6th clock signal, receive the 5th clock without the upset between high level and low level
The charge pump of signal and the 6th clock signal does not continue to work, can stop immediately after enable signal is converted to low level
Only work.
It is provided above when enable signal is low level, the two schemes for keeping the output of trigger constant have been carried out in detail
It is thin to introduce, it will be understood that those skilled in the art can be according to being actually needed using any or more in above two scheme
Kind, the present invention is not any limitation as to specific selection.Or those skilled in the art can also use others in enable signal
For low level when, keep the constant scheme of output of trigger.
To sum up, the clock driving method of a kind of charge pump provided in an embodiment of the present invention, can be changed into enable signal
After low level, the clock signal of trigger output is maintained at low level or high level is constant, i.e. the clock of trigger output
Signal no longer carries out the upset between high level and low level, therefore can avoid the clock signal after low enable signal is sent
Still the phenomenon for overturning and causing charge pump to work on so that charge pump is stopped in time, so as to realize charge pump
Be precisely controlled.Further, in the case where charge pump is stopped in time, the voltage of charge pump output is not above presetting
Magnitude of voltage, overshoot during charge pump is reduced, so as to reduce ripple, the performance of charge pump is improved.
Embodiment two
Reference picture 5, give a kind of step flow of the clock-driven method of charge pump provided in an embodiment of the present invention
Figure, methods described can specifically include：Output according to enable signal and external clock control trigger；
Wherein, the step of output of the foundation enable signal and external clock control trigger, can specifically include：
Step 501, when enable signal is low level, keep the output of trigger constant.
Step 502, when enable signal is high level, the output of control trigger follows external clock.
It should be noted that when enable signal is high level, the output of control trigger follows external clock, i.e., outside
Clock carries out the upset between high level and low level, and the clock signal of trigger output followed by external clock and carries out height simultaneously
Upset between level and low level, if for example, before enable signal is converted to high level the output of trigger be high level,
After enable signal is converted to high level, the output of trigger is low level by high level upset with the upset of external clock；
And for example, if the output of trigger is low level before enable signal is converted to high level, enable signal be converted to high level it
Afterwards, the output of trigger is high level by low level upset with the upset of external clock.Due to the clock letter of trigger output
Number follow external clock to carry out the upset between high level and low level, therefore receive the electric charge pump startup work of the clock signal
Make.
To sum up, the time driving method of a kind of charge pump provided in an embodiment of the present invention, it is changed into high electricity in enable signal
After flat, clock signal is overturn, and cause charge pump to start work in time, so as to realize being precisely controlled for charge pump,
The performance of charge pump is set to be improved.
The present invention can be provided as follows when enable signal is high level, and the output of control trigger follows external clock
Technical scheme.
Option b 1,
Reference picture 6, one kind provided in an embodiment of the present invention is given when enable signal is high level, control trigger
Output follows the step flow chart of the method for external clock, specifically may include steps of：
Step 601, the output according to enable signal and external clock the 3rd gate circuit of control and the 4th gate circuit, enabled
When signal is high level, the output of at least one of the 3rd gate circuit and the 4th gate circuit is high level；Wherein, the 3rd gate circuit
Input termination enable signal and external clock, the input termination external clock of the 4th gate circuit and enable signal it is reverse, the
The output end of three gate circuits and the output end of the 4th gate circuit are connected with the input of trigger；
When enable signal is high level, the output of at least one of the 3rd gate circuit and the 4th gate circuit is high level,
I.e. the output of the 3rd gate circuit is high level, and the output of the 4th gate circuit is low level；Or the 3rd gate circuit output to be low
Level, the output of the 4th gate circuit is high level.In one kind application example of the present invention, the 3rd gate circuit can be and door electricity
Road, the 4th gate circuit can be OR-NOT circuit.Specifically, the input termination enable signal and external clock of the 3rd gate circuit,
4th gate circuit input termination external clock and enable signal it is reverse, the output end of the 3rd gate circuit and the 4th gate circuit with
The input of trigger is connected.
It is appreciated that it with gate circuit, the 4th gate circuit is that OR-NOT circuit is intended only as the 3rd that above-mentioned 3rd gate circuit, which is,
A kind of example of gate circuit and the 4th gate circuit, and the application limitation of the embodiment of the present invention is not understood to, in fact, there is one
When input signal is low level, output signal is low level any 3rd gate circuit and the 4th gate circuit is feasible, institute
There is the gate circuit of achievable above-mentioned function within the protection domain of the embodiment of the present invention.
Step 602, when the output of at least one of the 3rd gate circuit and the 4th gate circuit is high level, control trigger
Output follow external clock.
In actual applications, trigger can be rest-set flip-flop.Wherein the R ends of rest-set flip-flop are the 3rd input, and S ends are
4th input, Q ends are the 3rd output end, and Qb ends are the 4th output end.The output end of 3rd gate circuit and the of rest-set flip-flop
Three inputs are connected, and the output end of the 4th gate circuit is connected with the 4th input of rest-set flip-flop.
Reference table 3, show a kind of example of the true value of rest-set flip-flop of the present invention.
Table 3
| 3rd input | 4th input | 3rd output end | 4th output end |
| 0 | 0 | Keep | Keep |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | Forbid | Forbid |
As can be seen that when in the input signal of two inputs of rest-set flip-flop at least one input signal be high electricity
It is flat, i.e. when the output of at least one of output of the 3rd gate circuit and the 4th gate circuit is high level, control the of rest-set flip-flop
The output of three output ends and the 4th output end follows external clock.
The output of the 3rd output end and the 4th output end of rest-set flip-flop is controlled to follow external clock, if specifically, enabled
The 3rd output end of rest-set flip-flop is high level before signal is converted to high level, and the output of the 4th output end is low level, then
After enable signal is converted to high level, the 3rd output end of rest-set flip-flop follows the upset of external clock, is overturn by high level
For low level；4th output end of rest-set flip-flop follows the upset of external clock, is high level by low level upset.If enabled letter
The 3rd output end of rest-set flip-flop is low level before number being converted to high level, and the output of the 4th output end of rest-set flip-flop is height
Level, then after enable signal is converted to high level, the 3rd output end of rest-set flip-flop follows the upset of external clock, by low electricity
Flat upset is high level；4th output end of rest-set flip-flop follows the upset of external clock, is low level by high level upset.Cause
This, enable signal is changed into after high level, and the clock signal of the output end of rest-set flip-flop the 3rd and the output of the 4th output end follows
External clock is overturn accordingly.
It should be noted that the 3rd output end of rest-set flip-flop is connected with the 3rd drive device, the 4th of rest-set flip-flop is defeated
Go out end with four-drive device to be connected, the 3rd clock signal that the output end of rest-set flip-flop the 3rd exports is passed into the 3rd driving
Device, the 4th clock signal that four output ends of rest-set flip-flop export is passed into four-drive device.And the 3rd drive device
Processing can be amplified to the 3rd clock signal and the 4th clock signal respectively with four-drive device, and by after amplification
Three clock signals and the 4th clock signal are supplied to charge pump.
The 3rd clock signal and the 4th clock signal that trigger transmission comes follow the upset of external clock, therefore, receive
The charge pump of 3rd clock signal and the 4th clock signal can work, trigger after enable signal is converted to high level,
Start work immediately.
Option b 2
Reference picture 7, one kind provided in an embodiment of the present invention is given when enable signal is high level, control trigger
Output follows the step flow chart of the method for external clock, specifically may include steps of：
Step 701, the output according to enable signal and external clock the 7th gate circuit of control and the 8th gate circuit, enabled
When signal is high level, the output of at least one of the 7th gate circuit and the 8th gate circuit is low level；Wherein, the 7th gate circuit
Input termination enable signal and external clock, the input termination external clock of the 8th gate circuit and enable signal it is reverse, the
The output end of seven gate circuits and the output end of the 8th gate circuit are connected with the input of trigger；
When enable signal is high level, the output of at least one of the 7th gate circuit and the 8th gate circuit is high level,
I.e. the output of the 7th gate circuit is high level, and the output of the 8th gate circuit is low level；Or the 7th gate circuit output to be low
Level, the output of the 8th gate circuit is high level.
In one kind application example of the present invention, the 7th gate circuit can be NAND gate circuit, and the 8th gate circuit can be
OR circuit.Specifically, the input termination enable signal and external clock of the 7th gate circuit, the input termination of the 8th gate circuit is outer
Portion's clock and enable signal it is reverse, the output end of the 7th gate circuit and the 8th gate circuit is connected with the input of trigger.
It is appreciated that above-mentioned 7th gate circuit is NAND gate circuit, the 8th gate circuit is that OR circuit is intended only as the 7th
A kind of example of gate circuit and the 8th gate circuit, and the application limitation of the embodiment of the present invention is not understood to, in fact, there is one
When input signal is low level, output signal is low level any 7th gate circuit and the 8th gate circuit is feasible, institute
There is the gate circuit of achievable above-mentioned function within the protection domain of the embodiment of the present invention.
Step 702, according to the 7th gate circuit and the 8th gate circuit output control trigger output, the 7th gate circuit with
When the output of at least one of 8th gate circuit is low level, the output of control trigger follows the external clock.
In actual applications, trigger can be rest-set flip-flop.Wherein the R ends of rest-set flip-flop are the 7th input, and S ends are
8th input, Q ends are the 7th output end, and Qb ends are the 8th output end.The output end of 7th gate circuit and the of rest-set flip-flop
Seven inputs are connected, and the output end of the 8th gate circuit is connected with the 8th input of rest-set flip-flop.
Reference table 4, show a kind of example of the truth table of rest-set flip-flop of the present invention.
Table 4
| 7th input | 8th input | 7th output end | 8th output end |
| 1 | 1 | Keep | Keep |
| 1 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 |
| 0 | 0 | Forbid | Forbid |
As can be seen that when in the input signal of two inputs of rest-set flip-flop at least one input signal be low electricity
It is flat, i.e. when the output of at least one of output of the 7th gate circuit and the 8th gate circuit is low level, control the of rest-set flip-flop
The output of seven output ends and the 8th output end follows external clock.
The output of the 7th output end and the 8th output end of rest-set flip-flop is controlled to follow external clock, if specifically, enabled
The 7th output end of rest-set flip-flop is high level before signal is converted to high level, and the output of the 8th output end is low level, then
After enable signal is converted to high level, the 7th output end of rest-set flip-flop is by high level upset with the upset of external clock
Low level；8th output end of rest-set flip-flop is high level by low level upset with the upset of external clock.If enable signal turns
The 7th output end of rest-set flip-flop is low level before being changed to high level, and the output of the 8th output end of rest-set flip-flop is high electricity
Flat, then after enable signal is converted to high level, the 7th output end of rest-set flip-flop is turned over the upset of external clock by low level
Switch to high level；8th output end of rest-set flip-flop is low level by high level upset with the upset of external clock.Therefore, make
Energy signal is changed into after high level, when the clock signal of the output end of rest-set flip-flop the 7th and the output of the 8th output end follows outside
Clock is overturn accordingly.
It should be noted that the 7th output end of rest-set flip-flop is connected with the 7th drive device, the 8th of rest-set flip-flop is defeated
Go out end with the 8th drive device to be connected, the 7th clock signal that the output end of rest-set flip-flop the 7th exports is passed into the 7th driving
Device, the 8th clock signal that the eight or four output end of rest-set flip-flop exports is passed into the 8th drive device.And the 7th driving
Device and the 8th drive device can be amplified processing to the 7th clock signal and the 8th clock signal respectively, and by after amplification
The 7th clock signal and the 8th clock signal be supplied to charge pump.
The 7th clock signal and the 8th clock signal that trigger transmission comes follow the upset two of external clock to carry out accordingly
Upset, therefore, receiving the charge pump of the 7th clock signal and the 8th clock signal can be worked, and height is converted in enable signal
After level, trigger starts work immediately.
It is provided above when enable signal is low level, the two schemes for keeping the output of trigger constant have been carried out in detail
It is thin to introduce, it will be understood that those skilled in the art can be according to being actually needed using any or more in above two scheme
Kind, the present invention is not any limitation as to specific selection.Or those skilled in the art can also use others in enable signal
For low level when, keep the constant scheme of output of trigger.
In summary, the clock driving method of a kind of charge pump provided in an embodiment of the present invention, can turn in enable signal
It is changed into after high level, makes clock signal follow external clock to be overturn, and causes charge pump timely to drive work, so as to
Being precisely controlled for charge pump is realized, the performance of charge pump is improved.
Reference picture 8, the timing diagram of the clock driving method of the charge pump of the embodiment of the present invention is shown, wherein, EN is to make
Energy signal, CLK is external clock.EN in T1 by low transition be high level with control electric charge pump startup work, CLK is in T2
Place's upset, CLK1 and CLK2 are overturn at T2 with CLK upset, therefore, the work of electric charge pump startup；EN is in T3 by high electricity
Flat turn is changed to low level to control charge pump to be stopped, and CLK1 and CLK2 start no longer to be overturn at T3, therefore, electric charge
Pump can be stopped at T3.
It should be noted that for embodiment of the method, in order to be briefly described, therefore it is all expressed as to a series of action group
Close, but those skilled in the art should know, the embodiment of the present invention is not limited by described sequence of movement, because according to
According to the embodiment of the present invention, some steps can use other orders or carry out simultaneously.Secondly, those skilled in the art also should
Know, embodiment described in this description belongs to preferred embodiment, and the involved action not necessarily present invention is implemented
Necessary to example.
Device embodiment one
Reference picture 9, a kind of structure chart of the clock drive system of charge pump provided in an embodiment of the present invention is shown, specifically
It can include：Controller 901 and trigger 902.
Controller 901 is used for the output according to enable signal and external clock control trigger 902；Trigger 902 it is defeated
Go out end with the drive device of charge pump to be connected, the clock signal that trigger 902 exports is delivered to drive device；
Wherein, controller 901 can specifically include：First control module 911, for when enable signal is low level,
Keep the output of trigger 902 constant.
To sum up, the clock drive system of a kind of charge pump provided in an embodiment of the present invention, due to being changed into enable signal
After low level, the clock signal that trigger 902 exports is maintained at low level or high level is constant, i.e., trigger 902 exports
Clock signal no longer carries out the upset between high level and low level, therefore can avoid after enable signal is converted to low level
Clock signal still overturns and so that the phenomenon that charge pump works on so that charge pump is stopped in time, so as to reality
Existing charge pump is precisely controlled.Further, in the case where charge pump is stopped in time, the voltage of charge pump output will not
Higher than preset voltage value, overshoot during charge pump is reduced, so as to reduce ripple, is put forward the performance of charge pump
Rise.
In one preferred embodiment of the invention, first control module 911 can specifically include：
First gate circuit and the second gate circuit；The input termination enable signal and external clock of first gate circuit, second
Circuit input termination external clock and the enable signal it is reverse, the output end of the first gate circuit and the second gate circuit with touch
The input of hair device 902 is connected；
Wherein, when the output of the first gate circuit and the second gate circuit is low level, trigger 902 keeps output not
Become.
Reference picture 10, show a kind of structural representation of the clock drive system of charge pump provided by the invention；
In embodiments of the present invention, it with gate circuit 1001, the second gate circuit is OR-NOT circuit 1002 that the first gate circuit, which is,
Trigger is rest-set flip-flop 1003；Wherein, the input with gate circuit 1001 terminates enable signal and external clock, nor gate 1002
Input termination external clock and the enable signal it is reverse；With the output end and the R of rest-set flip-flop 1003 of gate circuit 1001
End is connected, and the output end of OR-NOT circuit 1002 is connected with the S ends of rest-set flip-flop 1003；The Q ends and first of rest-set flip-flop 1003
Drive device 1004 is connected, and the Qb ends of rest-set flip-flop 1003 are connected with the second drive device 1005.
In another preferred embodiment of the invention, first control module 911 can specifically include：
5th gate circuit and the 6th gate circuit；The input termination enable signal and external clock of 5th gate circuit, the 6th
Circuit input termination external clock and the enable signal it is reverse, the output end of the 5th gate circuit and the 6th gate circuit with touch
The input of hair device 902 is connected；
Wherein, when the output of the 5th gate circuit and the 6th gate circuit is low level, trigger 902 keeps output not
Become.
Reference picture 11, show a kind of structural representation of the clock drive system of charge pump provided by the invention；
In embodiments of the present invention, it with door inverter circuit 1101, the 6th gate circuit is OR circuit 1102 that the 5th gate circuit, which is,
Trigger is rest-set flip-flop 1103；Wherein, the input termination enable signal and external clock of NAND gate circuit 1101, OR gate 1102
Input termination external clock and the enable signal it is reverse；The output end of NAND gate circuit 1101 and rest-set flip-flop 1103
R ends are connected, and the output end of OR circuit 1102 is connected with the S ends of rest-set flip-flop 1103；Driven with the 5th at the Q ends of rest-set flip-flop 1103
Dynamic device 1104 is connected, and the Qb ends of rest-set flip-flop 1103 are connected with the 6th drive device 1105.
To sum up, the clock drive system of a kind of charge pump provided in an embodiment of the present invention, it is changed into low electricity in enable signal
After flat, make clock signal keep high level or low level constant, and charge pump is timely stopped, so as to realize
Charge pump is precisely controlled.Further, charge pump is stopped in time so that the output voltage of charge pump is not above presetting
Magnitude of voltage, therefore overshoot when reducing charge pump, so as to reduce ripple, make the performance of charge pump be improved.
Device embodiment two
Reference picture 12, a kind of structure chart of the clock drive system of charge pump provided in an embodiment of the present invention is shown, had
Body can include：Controller 1201 and trigger 1202.
Controller 1201 is used for the output according to enable signal and external clock control trigger 1202；Trigger 1202
Output end is connected with the drive device of charge pump, and the clock signal that trigger 1202 exports is delivered into drive device；
Wherein, controller 1201 can specifically include：First control module 1211, the second control module 1212.Wherein,
Two control modules 1212, for when enable signal is high level, the output of control trigger 1202 to follow external clock.
In one preferred embodiment of the invention, second control module 1212 can specifically include：
3rd gate circuit and the 4th gate circuit；The input termination enable signal and external clock of 3rd gate circuit, the 4th
The input termination external clock of circuit and reverse, the output end and trigger of the 3rd gate circuit and the 4th gate circuit of enable signal
1202 input is connected；
Wherein, when the output of at least one of the 3rd gate circuit and the 4th gate circuit is high level, trigger 1202
Output follows the external clock.
Reference picture 10, show a kind of structural representation of the clock drive system of charge pump provided by the invention；
In embodiments of the present invention, the 3rd gate circuit can be the same as the first gate circuit in device embodiment one, the 4th electricity
Road can will not be repeated here with the second gate circuit in device embodiment one, the embodiment of the present invention.
In another preferred embodiment of the invention, second control module 1212 can specifically include：
7th gate circuit and the 8th gate circuit；The input termination enable signal and external clock of 7th gate circuit, the 8th
The input termination external clock of circuit and reverse, the output end and trigger of the 7th gate circuit and the 8th gate circuit of enable signal
1202 input is connected；
Wherein, when the output of at least one of the 7th gate circuit and the 8th gate circuit is low level, trigger 1202
Output follows external clock.
Reference picture 11, show a kind of structural representation of the clock drive system of charge pump provided by the invention；
In embodiments of the present invention, the 7th gate circuit can be the same as the 5th gate circuit in device embodiment one, the 8th electricity
Road can will not be repeated here with the 6th gate circuit in device embodiment one, the embodiment of the present invention.
In summary, the clock drive system of a kind of charge pump provided in an embodiment of the present invention, is changed into enable signal
After high level, clock signal can be made to follow external clock to be overturn, and cause charge pump timely to drive work, so as to
Being precisely controlled for charge pump is realized, the performance of charge pump is improved.
For system embodiment, because it is substantially similar to embodiment of the method, so description is fairly simple, it is related
Part illustrates referring to the part of embodiment of the method.
Each embodiment in this specification is described by the way of progressive, what each embodiment stressed be with
The difference of other embodiment, between each embodiment identical similar part mutually referring to.
It should be understood by those skilled in the art that, the embodiment of the embodiment of the present invention can be provided as method, apparatus or calculate
Machine program product.Therefore, the embodiment of the present invention can use complete hardware embodiment, complete software embodiment or combine software and
The form of the embodiment of hardware aspect.Moreover, the embodiment of the present invention can use one or more wherein include computer can
With in the computer-usable storage medium (including but is not limited to magnetic disk storage, CD-ROM, optical memory etc.) of program code
The form of the computer program product of implementation.
The embodiment of the present invention is with reference to method according to embodiments of the present invention, terminal device (system) and computer program
The flow chart and/or block diagram of product describes.It should be understood that can be by computer program instructions implementation process figure and/or block diagram
In each flow and/or square frame and the flow in flow chart and/or block diagram and/or the combination of square frame.These can be provided
Computer program instructions are set to all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing terminals
Standby processor is to produce a machine so that is held by the processor of computer or other programmable data processing terminal equipments
Capable instruction is produced for realizing in one flow of flow chart or multiple flows and/or one square frame of block diagram or multiple square frames
The device for the function of specifying.
These computer program instructions, which may be alternatively stored in, can guide computer or other programmable data processing terminal equipments
In the computer-readable memory to work in a specific way so that the instruction being stored in the computer-readable memory produces bag
The manufacture of command device is included, the command device is realized in one flow of flow chart or multiple flows and/or one side of block diagram
The function of being specified in frame or multiple square frames.
These computer program instructions can be also loaded into computer or other programmable data processing terminal equipments so that
Series of operation steps is performed on computer or other programmable terminal equipments to produce computer implemented processing, so that
The instruction performed on computer or other programmable terminal equipments is provided for realizing in one flow of flow chart or multiple flows
And/or specified in one square frame of block diagram or multiple square frames function the step of.
Although having been described for the preferred embodiment of the embodiment of the present invention, those skilled in the art once know base
This creative concept, then other change and modification can be made to these embodiments.So appended claims are intended to be construed to
Including preferred embodiment and fall into having altered and changing for range of embodiment of the invention.
Finally, it is to be noted that, herein, such as first and second or the like relational terms be used merely to by
One entity or operation make a distinction with another entity or operation, and not necessarily require or imply these entities or operation
Between any this actual relation or order be present.Moreover, term " comprising ", "comprising" or its any other variant meaning
Covering including for nonexcludability, so that process, method, article or terminal device including a series of elements are not only wrapped
Those key elements, but also the other element including being not expressly set out are included, or is also included for this process, method, article
Or the key element that terminal device is intrinsic.In the absence of more restrictions, wanted by what sentence "including a ..." limited
Element, it is not excluded that other identical element in the process including the key element, method, article or terminal device also be present.
The clock drivetrain of clock driving method to a kind of charge pump provided by the present invention and a kind of charge pump above
System is described in detail, and specific case used herein is set forth to the principle and embodiment of the present invention, the above
The explanation of embodiment is only intended to help the method and its core concept for understanding the present invention；Meanwhile for the general skill of this area
Art personnel, according to the thought of the present invention, there will be changes in specific embodiments and applications, in summary, this
Description should not be construed as limiting the invention.
Claims (10)
1. the clock driving method of a kind of charge pump, it is characterised in that methods described includes：According to enable signal and external clock
The output of control trigger；Wherein, the output end of the trigger is connected with the drive device of the charge pump, is touched described
The clock signal of hair device output is delivered to the drive device；
Wherein, the step of output of the foundation enable signal and external clock control trigger includes：In the enable signal
For low level when, keep the output of the trigger constant；It is described when the enable signal is low level, keep the triggering
The constant step of output of device, including：
The output of the first gate circuit and the second gate circuit is controlled according to the enable signal and the external clock, described enabled
When signal is low level, the output of first gate circuit and second gate circuit is low level；Wherein, described first
The input of circuit terminates the enable signal and external clock, and the input of second gate circuit terminates the external clock and institute
The reverse of enable signal is stated, the output end of first gate circuit and the second gate circuit is connected with the input of the trigger；
According to the output of trigger described in the output control of first gate circuit and the second gate circuit, in first gate circuit
When output with second gate circuit is low level, keep the output of the trigger constant.
2. according to the method for claim 1, it is characterised in that described according to enable signal and external clock control trigger
Output the step of also include：When the enable signal is high level, the output of the trigger is controlled to follow the outside
Clock.
3. according to the method for claim 2, it is characterised in that it is described when the enable signal is high level, control institute
The step of output of trigger follows the external clock is stated, including：
The output of the 3rd gate circuit and the 4th gate circuit is controlled according to the enable signal and the external clock, described enabled
When signal is high level, the output of at least one of the 3rd gate circuit and described 4th gate circuit is high level；Wherein, institute
The input for stating the 3rd gate circuit terminates the enable signal and external clock, and the input of the 4th gate circuit terminates the outside
Reverse, the output end of the 3rd gate circuit and the output end of the 4th gate circuit and the triggering of clock and the enable signal
The input of device is connected；
According to the output of trigger described in the output control of the 3rd gate circuit and the 4th gate circuit, at described 3rd
When the output of at least one of circuit and the 4th gate circuit is high level, control the trigger output follow it is described outer
Portion's clock.
4. according to the method for claim 1, it is characterised in that it is described when the enable signal is low level, keep institute
Stating the constant step that exports of trigger also includes：
The output of the 5th gate circuit and the 6th gate circuit is controlled according to the enable signal and the external clock, described enabled
When signal is low level, the output of the 5th gate circuit and the 6th gate circuit is high level；Wherein, the 5th gate circuit
Input terminate the enable signal and external clock, the input of the 6th gate circuit terminates the external clock and described made
Can signal it is reverse, the output end of the 5th gate circuit and the 6th gate circuit is connected with the input of the trigger；
According to the output of trigger described in the output control of the 5th gate circuit and the 6th gate circuit, in the 5th gate circuit
When output with the 6th gate circuit is high level, keep the output of the trigger constant.
5. according to the method for claim 2, it is characterised in that it is described when the enable signal is high level, control institute
The step of output of trigger follows the external clock is stated, including：
The output of the 7th gate circuit and the 8th gate circuit is controlled according to the enable signal and the external clock, described enabled
When signal is high level, the output of at least one of the 7th gate circuit and described 8th gate circuit is low level；Wherein, institute
The input for stating the 7th gate circuit terminates the enable signal and external clock, and the input of the 8th gate circuit terminates the outside
Reverse, the output end of the 7th gate circuit and the output end of the 8th gate circuit and the triggering of clock and the enable signal
The input of device is connected；
According to the output of trigger described in the output control of the 7th gate circuit and the 8th gate circuit, the 7th electricity
When the output of at least one of road and the 8th gate circuit is low level, the output of the trigger is controlled to follow the outside
Clock.
A kind of 6. clock drive system of charge pump, it is characterised in that including：Controller and trigger；
Wherein, the controller is used for the output according to enable signal and external clock control trigger；Wherein, the trigger
Output end be connected with the drive device of the charge pump, the clock signal that the trigger exports is delivered to the driving
Device；
Wherein, the controller includes：First control module, touched for when the enable signal is low level, keeping described
The output for sending out device is constant；First control module, including：First gate circuit and the second gate circuit；First gate circuit
Input terminates the enable signal and external clock, and the input of second gate circuit terminates the external clock and described enabled
Signal it is reverse, the output end of first gate circuit and the second gate circuit is connected with the input of the trigger；
Wherein, when the output of first gate circuit and second gate circuit is low level, the trigger keeps defeated
Go out constant.
7. system according to claim 6, it is characterised in that the controller also includes：
Second control module, the output for when the enable signal is high level, controlling the trigger follow described outer
Portion's clock.
8. system according to claim 7, it is characterised in that second control module, including：3rd gate circuit and
Four gate circuits；The input of 3rd gate circuit terminates the enable signal and external clock, the input of the 4th gate circuit
Terminate the reverse of the external clock and the enable signal, the output end of the 3rd gate circuit and the 4th gate circuit with it is described
The input of trigger is connected；
Wherein, when the output of at least one of the 3rd gate circuit and the 4th gate circuit is high level, the triggering
The output of device follows the external clock.
9. system according to claim 6, it is characterised in that first control module, including：5th gate circuit and
Six gate circuits；The input of 5th gate circuit terminates the enable signal and the external clock, the 6th gate circuit
Input terminates the reverse of the external clock and the enable signal, the output end of the 5th gate circuit and the 6th gate circuit with
The input of the trigger is connected；
Wherein, when the output of the 5th gate circuit and the 6th gate circuit is high level, the trigger keeps output not
Become.
10. system according to claim 7, it is characterised in that second control module, including：7th gate circuit and
8th gate circuit；The input of 7th gate circuit terminates the enable signal and external clock, the 8th gate circuit it is defeated
Enter to terminate the reverse of the external clock and the enable signal, the output end of the 7th gate circuit and the 8th gate circuit it is defeated
Go out end with the input of the trigger to be connected；
Wherein, when the output of at least one of the 7th gate circuit and the 8th gate circuit is low level, the triggering
The output of device follows the external clock.
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| CN104967307A (en) | 2015-10-07 |
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