CN104967307A - charge pump clock driving method and system - Google Patents
charge pump clock driving method and system Download PDFInfo
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- CN104967307A CN104967307A CN201510350919.8A CN201510350919A CN104967307A CN 104967307 A CN104967307 A CN 104967307A CN 201510350919 A CN201510350919 A CN 201510350919A CN 104967307 A CN104967307 A CN 104967307A
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Abstract
The embodiment of the invention provides a charge pump clock driving method and a system. The method particularly comprises a steps in which output of a trigger is controlled according to enabling signals and an outer clock. The step comprises a substep in which when the enabling signal is low level, output of the trigger is kept unchanged. The output end of the trigger is connected with a driving device of the charge pump so as to transmit clock signals outputted by the trigger to the driving device. According to the embodiment of the invention, the charge pump can stop working timely, and performance of the charge pump is improved.
Description
Technical field
The present invention relates to electronic technology field, particularly relate to a kind of clock driving method of charge pump and a kind of clock drive system of charge pump.
Background technology
Along with the develop rapidly of electronic technology, charge pump, as a kind of important electronic devices and components, is widely used in and needs in the system of battery, such as can be applied in cellular phone, Bluetooth system and portable electric appts.
Charge pump needs continuous print pulse signal to carry out work to promote electric charge.Pulse signal overturns, then charge pump, produces voltage and outwards carry electric current at output; Pulse signal stops upset, then charge pump quits work, and namely stops outwards carrying electric current.Use clock as above-mentioned pulse signal in engineering.
With reference to Fig. 1, show the structural representation of the clock drive system of existing a kind of charge pump, specifically can comprise: AND circuit 1, not circuit 2, drive unit 3 and drive unit 4; Wherein, CLK is the clock that external oscillator produces; EN is enable signal, is the index signal of the operating state of charge pump, when EN is high level, then represents that charge pump needs to start; When EN is low level, then represent that the output voltage of charge pump reaches preset voltage value, need the upset stopping clock, charge pump needs to quit work; CLK1 and CLK2 is a pair reverse clock of Direct driver charge pump; CLK and EN is respectively from two input inputs of AND circuit 1, the output signal of AND circuit 1 is as the input signal of drive unit 3 and not circuit 2, the output signal of not circuit 2 as the input signal of drive unit 4, just anticlockwise respectively as needed for charge pump of the output signal CLK1 of drive unit 3 and drive unit 4 and CLK2.
But the process that in Fig. 1, EN and CLK is delivered to CLK1 and CLK2 from gate circuit needs the time, this causes EN when changing into low level, CLK1 and CLK2 can not stop upset in time, thus charge pump can not quit work in time.
With reference to Fig. 2, show the sequential chart of the traditional charge pump clock drive system shown in Fig. 1, wherein, EN is converted to low level when T4 by high level and quits work to control charge pump, but, the propagation delay time of EN and CLK in AND circuit 1, not circuit 2, drive unit 3 and drive unit 4 causes CLK1 and CLK2 not stop upset at T4 place, but stop upset at T5 place, and, CLK1 and CLK2 has carried out once inside out again between T4 and T5, therefore charge pump is also in work after T4, also, can not realize the accurate control of charge pump.
Summary of the invention
Embodiment of the present invention technical problem to be solved is to provide a kind of clock driving method of charge pump, and charge pump is quit work in time, improves electric charge pump performance.
Accordingly, the embodiment of the present invention additionally provides a kind of clock drive system of charge pump, in order to ensure the implementation and application of said method.
In order to solve the problem, the invention discloses a kind of clock driving method of charge pump, comprising:
The output of foundation enable signal and external clock control trigger; Wherein, the output of described trigger is connected with the drive unit of described charge pump, is delivered to described drive unit with the clock signal exported by described trigger;
Wherein, the step of the output of described foundation enable signal and external clock control trigger comprises: when described enable signal is low level, keep the output of described trigger constant.
Preferably, the step of the output of described foundation enable signal and external clock control trigger also comprises: when described enable signal is high level, described external clock is followed in the output controlling described trigger.
Preferably, described when described enable signal is low level, keep the step that the output of described trigger is constant, comprising:
Control the output of the first gate circuit and the second gate circuit according to described enable signal and described external clock, when described enable signal is low level, the output of described first gate circuit and described second gate circuit is low level; Wherein, enable signal and external clock described in the input termination of described first gate circuit, external clock described in the input termination of described second gate circuit and described enable signal reverse, described first gate circuit is connected with the input of described trigger with the output of the second gate circuit;
Output according to described first gate circuit and the second gate circuit controls the output of described trigger, when the output of described first gate circuit and described second gate circuit is low level, keeps the output of described trigger constant.
Preferably, described when described enable signal is high level, the step of described external clock is followed in the output controlling described trigger, comprising:
Control the output of the 3rd gate circuit and the 4th gate circuit according to described enable signal and described external clock, when described enable signal is high level, in described 3rd gate circuit and described 4th gate circuit, the output of at least one is high level; Wherein, enable signal and external clock described in the input termination of described 3rd gate circuit, external clock described in the input termination of described 4th gate circuit and described enable signal reverse, the output of described 3rd gate circuit is connected with the input of described trigger with the output of the 4th gate circuit;
Output according to described 3rd gate circuit and described 4th gate circuit controls the output of described trigger, and when in described 3rd gate circuit and described 4th gate circuit, the output of at least one is high level, described external clock is followed in the output controlling described trigger.
Preferably, described when described enable signal is low level, keep the constant step of the output of described trigger also to comprise:
Control the output of the 5th gate circuit and the 6th gate circuit according to described enable signal and described external clock, when described enable signal is low level, the output of described 5th gate circuit and the 6th gate circuit is high level; Wherein, enable signal and external clock described in the input termination of described 5th gate circuit, external clock described in the input termination of described 6th gate circuit and described enable signal reverse, described 5th gate circuit is connected with the input of described trigger with the output of the 6th gate circuit;
Output according to described 5th gate circuit and the 6th gate circuit controls the output of described trigger, when the output of described 5th gate circuit and the 6th gate circuit is high level, keeps the output of described trigger constant.
Preferably, described when described enable signal is high level, the step of described external clock is followed in the output controlling described trigger, comprising:
Control the output of the 7th gate circuit and the 8th gate circuit according to described enable signal and described external clock, when described enable signal is high level, in described 7th gate circuit and described 8th gate circuit, the output of at least one is low level; Wherein, enable signal and external clock described in the input termination of described 7th gate circuit, external clock described in the input termination of described 8th gate circuit and described enable signal reverse, the output of described 7th gate circuit is connected with the input of described trigger with the output of the 8th gate circuit;
Output according to described 7th gate circuit and described 8th gate circuit controls the output of described trigger, and when in described 7th gate circuit and described 8th gate circuit, the output of at least one is low level, described external clock is followed in the output controlling described trigger.
On the other hand, the invention also discloses a kind of clock drive system of charge pump, comprising: controller and trigger;
Wherein, described controller is used for the output according to enable signal and external clock control trigger; Wherein, the output of described trigger is connected with the drive unit of described charge pump, is delivered to described drive unit with the clock signal exported by described trigger;
Wherein, described controller comprises: the first control module, for when described enable signal is low level, keeps the output of described trigger constant.
Preferably, described controller also comprises:
Second control module, for when described enable signal is high level, described external clock is followed in the output controlling described trigger.
Preferably, described first control module, comprising: the first gate circuit and the second gate circuit; Enable signal and external clock described in the input termination of described first gate circuit, external clock described in the input termination of described second gate circuit and described enable signal reverse, described first gate circuit is connected with the input of described trigger with the output of the second gate circuit;
Wherein, when the output of described first gate circuit and described second gate circuit is low level, described trigger keeps exporting constant.
Preferably, described second control module, comprising: the 3rd gate circuit and the 4th gate circuit; Enable signal and external clock described in the input termination of described 3rd gate circuit, external clock described in the input termination of described 4th gate circuit and described enable signal reverse, described 3rd gate circuit is connected with the input of described trigger with the output of the 4th gate circuit;
Wherein, when in described 3rd gate circuit and described 4th gate circuit, the output of at least one is high level, described external clock is followed in the output of described trigger.
Preferably, described first control module, comprising: the 5th gate circuit and the 6th gate circuit; Enable signal and described external clock described in the input termination of described 5th gate circuit, external clock described in the input termination of described 6th gate circuit and described enable signal reverse, described 5th gate circuit is connected with the input of described trigger with the output of the 6th gate circuit;
Wherein, when the output of described 5th gate circuit and the 6th gate circuit is high level, described trigger keeps exporting constant.
Preferably, described second control module, comprising: the 7th gate circuit and the 8th gate circuit; Enable signal and external clock described in the input termination of described 7th gate circuit, external clock described in the input termination of described 8th gate circuit and described enable signal reverse, the output of described 7th gate circuit is connected with the input of described trigger with the output of the 8th gate circuit;
Wherein, when in described 7th gate circuit and described 8th gate circuit, the output of at least one is low level, described external clock is followed in the output of described trigger.
Compared with prior art, the embodiment of the present invention comprises following advantage:
The embodiment of the present invention is after enable signal changes low level into, the clock signal that trigger exports remains on low level or high level is constant, namely the clock signal that trigger exports no longer carries out the upset between high level and low level, therefore, it is possible to avoid clock signal after sending low enable signal still to overturn and the phenomenon making charge pump work on, charge pump is quit work in time, thus the accurate control of charge pump can be realized.Further, in the timely out-of-work situation of charge pump, the voltage that charge pump exports higher than preset voltage value, can not reduce overshoot during charge pump, thus reduces ripple, and electric charge pump performance is improved.
Accompanying drawing explanation
Fig. 1 is the structural representation of the clock drive system of existing a kind of charge pump;
Fig. 2 is the sequential chart of the drive system of charge pump clock shown in Fig. 1;
Fig. 3 be the one that provides of the embodiment of the present invention when enable signal is low level, the flow chart of steps of the method keeping the output of trigger constant;
Fig. 4 be the one that provides of the embodiment of the present invention when enable signal is low level, the flow chart of steps of the method keeping the output of trigger constant;
The flow chart of steps of the clock-driven method of a kind of charge pump that Fig. 5 embodiment of the present invention provides;
Fig. 6 be the one that provides of the embodiment of the present invention when enable signal is high level, the flow chart of steps of the method for external clock is followed in the output of control trigger;
Fig. 7 be the one that provides of the embodiment of the present invention when enable signal is high level, the flow chart of steps of the method for external clock is followed in the output of control trigger;
Fig. 8 is the sequential chart of the clock driving method of a kind of charge pump that the embodiment of the present invention provides;
Fig. 9 is the structure chart of the clock drive system of a kind of charge pump that the embodiment of the present invention provides;
Figure 10 is the structural representation of the clock drive system of a kind of charge pump that the embodiment of the present invention provides;
Figure 11 is the structural representation of the clock drive system of a kind of charge pump that the embodiment of the present invention provides; And
Figure 12 is the structure chart of the clock drive system of a kind of charge pump that the embodiment of the present invention provides.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Embodiment one
The clock-driven method of a kind of charge pump that the embodiment of the present invention one provides, the output of foundation enable signal and external clock control trigger, when enable signal is low level, keeps the output of trigger constant; Wherein, the output of trigger is connected with the drive unit of charge pump, is delivered to drive unit with the clock signal exported by trigger.
The embodiment of the present invention is when enable signal is low level, keep the output of trigger constant, namely after enable signal is converted to low level, the output of trigger and enable signal be converted to low level before the output of trigger be consistent, such as, if enable signal be converted to low level before the output of trigger be high level, then after enable signal is converted to low level, the output of trigger is still high level; And for example, if enable signal be converted to low level before the output of trigger be low level, then after enable signal is converted to low level, the output of trigger is still low level.
To sum up, the clock driving method of a kind of charge pump that the embodiment of the present invention provides, due to after enable signal changes low level into, the clock signal that trigger exports remains on low level or high level is constant, namely the clock signal that trigger exports no longer carries out the upset between high level and low level, therefore, it is possible to avoid clock signal after sending low enable signal still to overturn and the phenomenon making charge pump work on, charge pump is quit work in time, thus the accurate control of charge pump can be realized.Further, in the timely out-of-work situation of charge pump, the voltage that charge pump exports higher than preset voltage value, can not reduce overshoot during charge pump, thus reduces ripple, and electric charge pump performance is improved.
The present invention can provide following when enable signal is low level, keeps the technical scheme that the output of trigger is constant:
Option A 1
With reference to Fig. 3, give one that the embodiment of the present invention provides when enable signal is low level, the flow chart of steps of the method keeping the output of trigger constant, specifically can comprise the steps:
Step 301, foundation enable signal and external clock control the output of the first gate circuit and the second gate circuit, and when enable signal is low level, the output of the first gate circuit and the second gate circuit is low level; Wherein, the input termination enable signal of the first gate circuit and external clock, the input termination external clock of the second gate circuit and the reverse of enable signal, the first gate circuit is connected with the input of trigger with the output of the second gate circuit;
It should be noted that, enable signal is the index signal of the operating state of charge pump, and enable signal is high level, and represent that charge pump needs to start, clock needs to overturn; Enable signal is low level, represents that the output voltage of charge pump reaches preset voltage value, needs the upset stopping clock, and charge pump needs to quit work.
In a kind of application example of the present invention, the first gate circuit can be AND circuit, and the second gate circuit can be OR-NOT circuit.Concrete, the input of the first gate circuit can connect enable signal and external clock, and the input termination external clock of the second gate circuit and the reverse of enable signal, the first gate circuit is connected with the input of trigger with the output of the second gate circuit.
Be appreciated that; above-mentioned first gate circuit can be AND circuit, the second gate circuit can for OR-NOT circuit be just as a kind of example of the first gate circuit and the second gate circuit; and be not understood to the application restriction of the embodiment of the present invention; in fact; when there being an input signal to be low level; output signal for low level any first gate circuit and the second gate circuit be all feasible, all gate circuits realizing above-mentioned functions are all within the protection range of the embodiment of the present invention.
Step 302, output according to the output control trigger of the first gate circuit and the second gate circuit, when the output of the first gate circuit and the second gate circuit is low level, keep the output of trigger constant.
In actual applications, trigger can be rest-set flip-flop.Wherein the R end of rest-set flip-flop is first input end, and S end is the second input, and Q end is the first output, and Qb end is the second output.The output of the first gate circuit is connected with the first input end of rest-set flip-flop, and the output of the second gate circuit is connected with the second input of rest-set flip-flop.
With reference to table 1, show the example of the truth table of a kind of rest-set flip-flop of the present invention.
Table 1
| First input end | Second input | First output | Second output |
| 0 | 0 | Keep | Keep |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | Forbid | Forbid |
Can find out, when the first input end of rest-set flip-flop and the input signal of the second input are low level, when namely the output of the first gate circuit and the second gate circuit is low level, keep the output of the first output of rest-set flip-flop and the second output constant.
Keep the output of the first output of rest-set flip-flop and the second output constant, be specially, if enable signal be converted to low level before the first output of rest-set flip-flop and the output of the second output be high level, after then enable signal is converted to low level, the first output of rest-set flip-flop and the output of the second output are equal high level; If enable signal be converted to low level before the first output of rest-set flip-flop and the output of the second output be low level, then after enable signal is converted to low level, the first output of rest-set flip-flop and the output of the second output are low level.Therefore, after enable signal changes low level into, the clock signal that rest-set flip-flop first output and the second output export all remains on high level or low level is constant.
It should be noted that, first output of rest-set flip-flop is connected with the first drive unit, second output of rest-set flip-flop is connected with the second drive unit, pass to the first drive unit with the first clock signal exported by rest-set flip-flop first output, the second clock signal transmission exported by the second output of rest-set flip-flop is to the second drive unit.And the first drive unit and the second drive unit can carry out amplification process to the first clock signal and second clock signal respectively, and the first clock signal after amplification and second clock signal are supplied to charge pump.
Due to trigger transmission come the first clock signal and second clock signal all remains on high level or low level is constant, first clock signal and second clock signal all do not carry out the upset between high level and low level, therefore, the charge pump receiving the first clock signal and second clock signal no longer works on, after enable signal is converted to low level, can quit work immediately.
Option A 2
With reference to Fig. 4, show one that the embodiment of the present invention provides when enable signal is low level, the flow chart of steps of the method keeping the output of trigger constant, specifically can comprise the steps:
Step 401, foundation enable signal and external clock control the output of the 5th gate circuit and the 6th gate circuit, and when enable signal is low level, the output of the 5th gate circuit and the 6th gate circuit is high level; Wherein, the input termination enable signal of the 5th gate circuit and external clock, the input termination external clock of the 6th gate circuit and the reverse of enable signal, the 5th gate circuit is connected with the input of trigger with the output of the 6th gate circuit;
In a kind of application example of the present invention, the 5th gate circuit can be NAND gate circuit, and the 6th gate circuit can be OR circuit.Concrete, the input termination enable signal of the 5th gate circuit and external clock, the input termination external clock of the 6th gate circuit and the reverse of enable signal, the 5th gate circuit is connected with the input of trigger with the output of the 6th gate circuit.
Be appreciated that; above-mentioned 5th gate circuit can be AND circuit, the 6th gate circuit can for OR-NOT circuit be just as a kind of example of the 5th gate circuit and the 6th gate circuit; and be not understood to the application restriction of the embodiment of the present invention; in fact; when there being an input signal to be low level; output signal for low level any 5th gate circuit and the 6th gate circuit be all feasible, all gate circuits realizing above-mentioned functions are all within the protection range of the embodiment of the present invention.
Step 402, output according to the output control trigger of the 5th gate circuit and the 6th gate circuit, when the output of the 5th gate circuit and the 6th gate circuit is high level, keep the output of trigger constant.
In actual applications, trigger can be rest-set flip-flop.Wherein the R end of rest-set flip-flop is the 5th input, and S end is the 6th input, and Q end is the 5th output, and Qb end is the 6th output.The output of the 5th gate circuit is connected with the 5th input of rest-set flip-flop, and the output of the 6th gate circuit is connected with the 6th input of rest-set flip-flop.
With reference to table 2, show the example of the truth table of a kind of rest-set flip-flop of the present invention.
Table 2
| 5th input | 6th input | 5th output | 6th output |
| 1 | 1 | Keep | Keep |
| 1 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 |
| 0 | 0 | Forbid | Forbid |
Can find out, when the 5th input of rest-set flip-flop and the input signal of the 6th input are high level, when namely the output of the 5th gate circuit and the 6th gate circuit is high level, keep the output of the 5th output of rest-set flip-flop and the 6th output constant.
Keep the output of the 5th output of rest-set flip-flop and the 6th output constant, be specially, if enable signal be converted to low level before the 5th output of rest-set flip-flop and the output of the 6th output be high level, after then enable signal is converted to low level, the 5th output of rest-set flip-flop and the output of the 6th output are equal high level; If enable signal be converted to low level before the 5th output of rest-set flip-flop and the output of the 6th output be low level, then after enable signal is converted to low level, the 5th output of rest-set flip-flop and the output of the 6th output are low level.Therefore, after enable signal changes low level into, the clock signal that rest-set flip-flop the 5th output and the 6th output export all remains on high level or low level is constant.
It should be noted that, 5th output of rest-set flip-flop is connected with the 5th drive unit, 6th output of rest-set flip-flop is connected with the 6th drive unit, pass to the 5th drive unit with the 5th clock signal exported by rest-set flip-flop the 5th output, the 6th clock signal that the 6th output of rest-set flip-flop exports is passed to the 6th drive unit.And the 5th drive unit and the 6th drive unit can carry out amplification process to the 5th clock signal and the 6th clock signal respectively, and the 5th clock signal after amplification and the 6th clock signal are supplied to charge pump.
Trigger transmission come the 5th clock signal and the 6th clock signal all remains on high level or low level is constant, 5th clock signal and the 6th clock signal all do not carry out the upset between high level and low level, therefore, the charge pump receiving the 5th clock signal and the 6th clock signal no longer works on, after enable signal is converted to low level, can quit work immediately.
There is provided above when enable signal is low level, the constant two schemes of the output of trigger is kept to be described in detail, be appreciated that those skilled in the art can adopt in above-mentioned two schemes according to actual needs arbitrary or multiple, the present invention is not limited concrete selection.Or, those skilled in the art can also adopt other when enable signal is low level, keep the scheme that the output of trigger is constant.
To sum up, the clock driving method of a kind of charge pump that the embodiment of the present invention provides, can after enable signal changes low level into, the clock signal that trigger exports remains on low level or high level is constant, namely the clock signal that trigger exports no longer carries out the upset between high level and low level, therefore, it is possible to avoid clock signal after sending low enable signal still to overturn and the phenomenon making charge pump work on, charge pump is quit work in time, thus the accurate control of charge pump can be realized.Further, in the timely out-of-work situation of charge pump, the voltage that charge pump exports higher than preset voltage value, can not reduce overshoot during charge pump, thus reduces ripple, and electric charge pump performance is improved.
Embodiment two
With reference to Fig. 5, give the flow chart of steps of the clock-driven method of a kind of charge pump that the embodiment of the present invention provides, described method specifically can comprise: the output of foundation enable signal and external clock control trigger;
Wherein, the step of the output of described foundation enable signal and external clock control trigger, specifically can comprise:
Step 501, when enable signal is low level, keep the output of trigger constant.
Step 502, when enable signal is high level, external clock is followed in the output of control trigger.
It should be noted that, when enable signal is high level, external clock is followed in the output of control trigger, namely external clock carries out the upset between high level and low level, the clock signal that trigger exports followed by the upset that external clock carries out between high level and low level simultaneously, such as, if enable signal be converted to high level before the output of trigger be high level, after then enable signal is converted to high level, the output of trigger is along with the upset of external clock, and being overturn by high level is low level; And for example, if enable signal be converted to high level before the output of trigger be low level, then after enable signal is converted to high level, the output of trigger is along with the upset of external clock, and being overturn by low level is high level.The clock signal exported due to trigger follows the upset that external clock carries out between high level and low level, therefore receives the charge pump startup work of this clock signal.
To sum up, the time driving method of a kind of charge pump that the embodiment of the present invention provides, after enable signal changes high level into, clock signal is overturn, and make charge pump start work in time, thus realize the accurate control of charge pump, electric charge pump performance is improved.
The present invention can provide following when enable signal is high level, and the technical scheme of external clock is followed in the output of control trigger.
Option b 1,
With reference to Fig. 6, give one that the embodiment of the present invention provides when enable signal is high level, the flow chart of steps of the method for external clock is followed in the output of control trigger, specifically can comprise the steps:
Step 601, control the output of the 3rd gate circuit and the 4th gate circuit according to enable signal and external clock, when enable signal is high level, in the 3rd gate circuit and the 4th gate circuit, the output of at least one is high level; Wherein, the input termination enable signal of the 3rd gate circuit and external clock, the input termination external clock of the 4th gate circuit and the reverse of enable signal, the output of the 3rd gate circuit is connected with the input of trigger with the output of the 4th gate circuit;
When enable signal is high level, in the 3rd gate circuit and the 4th gate circuit, the output of at least one is high level, and namely the output of the 3rd gate circuit is high level, and the output of the 4th gate circuit is low level; Or the output of the 3rd gate circuit is low level, the output of the 4th gate circuit is high level.In a kind of application example of the present invention, the 3rd gate circuit can be AND circuit, and the 4th gate circuit can be OR-NOT circuit.Concrete, the input termination enable signal of the 3rd gate circuit and external clock, the input termination external clock of the 4th gate circuit and the reverse of enable signal, the 3rd gate circuit is connected with the input of trigger with the output of the 4th gate circuit.
Be appreciated that; above-mentioned 3rd gate circuit is AND circuit, the 4th gate circuit is that OR-NOT circuit is just as a kind of example of the 3rd gate circuit and the 4th gate circuit; and be not understood to the application restriction of the embodiment of the present invention; in fact; when there being an input signal to be low level; output signal for low level any 3rd gate circuit and the 4th gate circuit be all feasible, all gate circuits realizing above-mentioned functions are all within the protection range of the embodiment of the present invention.
Step 602, when in the 3rd gate circuit and the 4th gate circuit, the output of at least one is high level, external clock is followed in the output of control trigger.
In actual applications, trigger can be rest-set flip-flop.Wherein the R end of rest-set flip-flop is the 3rd input, and S end is four-input terminal, and Q end is the 3rd output, and Qb end is the 4th output.The output of the 3rd gate circuit is connected with the 3rd input of rest-set flip-flop, and the output of the 4th gate circuit is connected with the four-input terminal of rest-set flip-flop.
With reference to table 3, show the example of the true value of a kind of rest-set flip-flop of the present invention.
Table 3
| 3rd input | Four-input terminal | 3rd output | 4th output |
| 0 | 0 | Keep | Keep |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | Forbid | Forbid |
Can find out, in the input signal of two inputs of rest-set flip-flop, have at least an input signal to be high level, when the output of at least one is high level in the output of i.e. the 3rd gate circuit and the 4th gate circuit, control the 3rd output of rest-set flip-flop and external clock is followed in the output of the 4th output.
External clock is followed in control the 3rd output of rest-set flip-flop and the output of the 4th output, be specially, if enable signal be converted to high level before the 3rd output of rest-set flip-flop be high level, the output of the 4th output is low level, after then enable signal is converted to high level, 3rd output of rest-set flip-flop follows the upset of external clock, and being overturn by high level is low level; 4th output of rest-set flip-flop follows the upset of external clock, and being overturn by low level is high level.If enable signal be converted to high level before the 3rd output of rest-set flip-flop be low level, the output of the 4th output of rest-set flip-flop is high level, after then enable signal is converted to high level, the 3rd output of rest-set flip-flop follows the upset of external clock, and being overturn by low level is high level; 4th output of rest-set flip-flop follows the upset of external clock, and being overturn by high level is low level.Therefore, after enable signal changes high level into, the clock signal that rest-set flip-flop the 3rd output and the 4th output export is followed external clock and is overturn accordingly.
It should be noted that, 3rd output of rest-set flip-flop is connected with the 3rd drive unit, 4th output of rest-set flip-flop is connected with four-drive device, pass to the 3rd drive unit with the 3rd clock signal exported by rest-set flip-flop the 3rd output, the 4th clock signal that four outputs of rest-set flip-flop export is passed to four-drive device.And the 3rd drive unit and four-drive device can carry out amplification process to the 3rd clock signal and the 4th clock signal respectively, and the 3rd clock signal after amplification and the 4th clock signal are supplied to charge pump.
The 3rd clock signal that trigger transmission comes and the 4th clock signal follow the upset of external clock, and therefore, the charge pump receiving the 3rd clock signal and the 4th clock signal can work, and trigger, after enable signal is converted to high level, starts work immediately.
Option b 2
With reference to Fig. 7, give one that the embodiment of the present invention provides when enable signal is high level, the flow chart of steps of the method for external clock is followed in the output of control trigger, specifically can comprise the steps:
Step 701, control the output of the 7th gate circuit and the 8th gate circuit according to enable signal and external clock, when enable signal is high level, in the 7th gate circuit and the 8th gate circuit, the output of at least one is low level; Wherein, the input termination enable signal of the 7th gate circuit and external clock, the input termination external clock of the 8th gate circuit and the reverse of enable signal, the output of the 7th gate circuit is connected with the input of trigger with the output of the 8th gate circuit;
When enable signal is high level, in the 7th gate circuit and the 8th gate circuit, the output of at least one is high level, and namely the output of the 7th gate circuit is high level, and the output of the 8th gate circuit is low level; Or the output of the 7th gate circuit is low level, the output of the 8th gate circuit is high level.
In a kind of application example of the present invention, the 7th gate circuit can be NAND gate circuit, and the 8th gate circuit can be OR circuit.Concrete, the input termination enable signal of the 7th gate circuit and external clock, the input termination external clock of the 8th gate circuit and the reverse of enable signal, the 7th gate circuit is connected with the input of trigger with the output of the 8th gate circuit.
Be appreciated that; above-mentioned 7th gate circuit is NAND gate circuit, the 8th gate circuit is that OR circuit is just as a kind of example of the 7th gate circuit and the 8th gate circuit; and be not understood to the application restriction of the embodiment of the present invention; in fact; when there being an input signal to be low level; output signal for low level any 7th gate circuit and the 8th gate circuit be all feasible, all gate circuits realizing above-mentioned functions are all within the protection range of the embodiment of the present invention.
Step 702, output according to the output control trigger of the 7th gate circuit and the 8th gate circuit, when in the 7th gate circuit and the 8th gate circuit, the output of at least one is low level, described external clock is followed in the output of control trigger.
In actual applications, trigger can be rest-set flip-flop.Wherein the R end of rest-set flip-flop is the 7th input, and S end is the 8th input, and Q end is the 7th output, and Qb end is the 8th output.The output of the 7th gate circuit is connected with the 7th input of rest-set flip-flop, and the output of the 8th gate circuit is connected with the 8th input of rest-set flip-flop.
With reference to table 4, show the example of the truth table of a kind of rest-set flip-flop of the present invention.
Table 4
| 7th input | 8th input | 7th output | 8th output |
| 1 | 1 | Keep | Keep |
| 1 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 |
| 0 | 0 | Forbid | Forbid |
Can find out, in the input signal of two inputs of rest-set flip-flop, have at least an input signal to be low level, when the output of at least one is low level in the output of i.e. the 7th gate circuit and the 8th gate circuit, control the 7th output of rest-set flip-flop and external clock is followed in the output of the 8th output.
External clock is followed in control the 7th output of rest-set flip-flop and the output of the 8th output, be specially, if enable signal be converted to high level before the 7th output of rest-set flip-flop be high level, the output of the 8th output is low level, after then enable signal is converted to high level, 7th output of rest-set flip-flop is with the upset of external clock, and being overturn by high level is low level; 8th output of rest-set flip-flop is with the upset of external clock, and being overturn by low level is high level.If enable signal be converted to high level before the 7th output of rest-set flip-flop be low level, the output of the 8th output of rest-set flip-flop is high level, after then enable signal is converted to high level, the 7th output of rest-set flip-flop is with the upset of external clock, and being overturn by low level is high level; 8th output of rest-set flip-flop is with the upset of external clock, and being overturn by high level is low level.Therefore, after enable signal changes high level into, the clock signal that rest-set flip-flop the 7th output and the 8th output export is followed external clock and is overturn accordingly.
It should be noted that, 7th output of rest-set flip-flop is connected with the 7th drive unit, 8th output of rest-set flip-flop is connected with the 8th drive unit, pass to the 7th drive unit with the 7th clock signal exported by rest-set flip-flop the 7th output, the 8th clock signal that the eight or four output of rest-set flip-flop exports is passed to the 8th drive unit.And the 7th drive unit and the 8th drive unit can carry out amplification process to the 7th clock signal and the 8th clock signal respectively, and the 7th clock signal after amplification and the 8th clock signal are supplied to charge pump.
The upset two that the 7th clock signal that trigger transmission comes and the 8th clock signal follow external clock overturns accordingly, therefore, the charge pump receiving the 7th clock signal and the 8th clock signal can work, and after enable signal is converted to high level, trigger starts work immediately.
There is provided above when enable signal is low level, the constant two schemes of the output of trigger is kept to be described in detail, be appreciated that those skilled in the art can adopt in above-mentioned two schemes according to actual needs arbitrary or multiple, the present invention is not limited concrete selection.Or, those skilled in the art can also adopt other when enable signal is low level, keep the scheme that the output of trigger is constant.
In sum, the clock driving method of a kind of charge pump that the embodiment of the present invention provides, can after enable signal changes high level into, make clock signal follow external clock to overturn, and make charge pump drive work timely, thus realize the accurate control of charge pump, electric charge pump performance is improved.
With reference to Fig. 8, show the sequential chart of the clock driving method of the charge pump of the embodiment of the present invention, wherein, EN is enable signal, and CLK is external clock.EN when T1 by low transition be high level to control charge pump startup work, CLK T2 place upset, CLK1 and CLK2 overturns along with the upset of CLK at T2 place, therefore, charge pump startup work; EN is converted to low level when T3 by high level and quits work to control charge pump, CLK1 and CLK2 starts at T3 place no longer to overturn, and therefore, charge pump can quit work at T3 place.
It should be noted that, for embodiment of the method, in order to simple description, therefore it is all expressed as a series of combination of actions, but those skilled in the art should know, the embodiment of the present invention is not by the restriction of described sequence of movement, because according to the embodiment of the present invention, some step can adopt other orders or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in specification all belongs to preferred embodiment, and involved action might not be that the embodiment of the present invention is necessary.
Device embodiment one
With reference to Fig. 9, show the structure chart of the clock drive system of a kind of charge pump that the embodiment of the present invention provides, specifically can comprise: controller 901 and trigger 902.
Controller 901 is for the output according to enable signal and external clock control trigger 902; The output of trigger 902 is connected with the drive unit of charge pump, is delivered to drive unit with the clock signal exported by trigger 902;
Wherein, controller 901 specifically can comprise: the first control module 911, for when enable signal is low level, keeps the output of trigger 902 constant.
To sum up, the clock drive system of a kind of charge pump that the embodiment of the present invention provides, due to after enable signal changes low level into, the clock signal that trigger 902 exports remains on low level or high level is constant, namely the clock signal that trigger 902 exports no longer carries out the upset between high level and low level, therefore, it is possible to avoid clock signal after enable signal is converted to low level still to overturn and the phenomenon making charge pump work on, charge pump is quit work in time, thus the accurate control of charge pump can be realized.Further, in the timely out-of-work situation of charge pump, the voltage that charge pump exports higher than preset voltage value, can not reduce overshoot during charge pump, thus reduces ripple, and electric charge pump performance is improved.
In one preferred embodiment of the invention, described first control module 911 specifically can comprise:
First gate circuit and the second gate circuit; The input termination enable signal of the first gate circuit and external clock, the input termination external clock of the second gate circuit and the reverse of described enable signal, the first gate circuit is connected with the input of trigger 902 with the output of the second gate circuit;
Wherein, when the output of the first gate circuit and the second gate circuit is low level, trigger 902 keeps exporting constant.
With reference to Figure 10, show the structural representation of the clock drive system of a kind of charge pump provided by the invention;
In embodiments of the present invention, the first gate circuit is AND circuit 1001, and the second gate circuit is OR-NOT circuit 1002, and trigger is rest-set flip-flop 1003; Wherein, the input termination enable signal of AND circuit 1001 and external clock, the input termination external clock of NOR gate 1002 and the reverse of described enable signal; The output of AND circuit 1001 is held with the R of rest-set flip-flop 1003 and is connected, and the output of OR-NOT circuit 1002 is held with the S of rest-set flip-flop 1003 and is connected; The Q end of rest-set flip-flop 1003 is connected with the first drive unit 1004, and the Qb end of rest-set flip-flop 1003 is connected with the second drive unit 1005.
In another preferred embodiment of the invention, described first control module 911 specifically can comprise:
5th gate circuit and the 6th gate circuit; The input termination enable signal of the 5th gate circuit and external clock, the input termination external clock of the 6th gate circuit and the reverse of described enable signal, the 5th gate circuit is connected with the input of trigger 902 with the output of the 6th gate circuit;
Wherein, when the output of the 5th gate circuit and the 6th gate circuit is low level, trigger 902 keeps exporting constant.
With reference to Figure 11, show the structural representation of the clock drive system of a kind of charge pump provided by the invention;
In embodiments of the present invention, the 5th gate circuit is be OR circuit 1102 with door inverter circuit the 1101, six gate circuit, and trigger is rest-set flip-flop 1103; Wherein, the input termination enable signal of NAND gate circuit 1101 and external clock, or the input termination external clock of door 1102 and the reverse of described enable signal; The output of NAND gate circuit 1101 is held with the R of rest-set flip-flop 1103 and is connected, and the output of OR circuit 1102 is held with the S of rest-set flip-flop 1103 and is connected; The Q end of rest-set flip-flop 1103 is connected with the 5th drive unit 1104, and the Qb end of rest-set flip-flop 1103 is connected with the 6th drive unit 1105.
To sum up, the clock drive system of a kind of charge pump that the embodiment of the present invention provides, after enable signal changes low level into, make clock signal keep high level or low level constant, and charge pump is quit work timely, thus realize the accurate control of charge pump.Further, charge pump quits work in time, makes the output voltage of charge pump higher than preset voltage value, because this reducing overshoot during charge pump, thus can not reduce ripple, electric charge pump performance is improved.
Device embodiment two
With reference to Figure 12, show the structure chart of the clock drive system of a kind of charge pump that the embodiment of the present invention provides, specifically can comprise: controller 1201 and trigger 1202.
Controller 1201 is for the output according to enable signal and external clock control trigger 1202; The output of trigger 1202 is connected with the drive unit of charge pump, is delivered to drive unit with the clock signal exported by trigger 1202;
Wherein, controller 1201 specifically can comprise: the first control module 1211, second control module 1212.Wherein, the second control module 1212, for when enable signal is high level, external clock is followed in the output of control trigger 1202.
In one preferred embodiment of the invention, described second control module 1212 specifically can comprise:
3rd gate circuit and the 4th gate circuit; The input termination enable signal of the 3rd gate circuit and external clock, the input termination external clock of the 4th gate circuit and the reverse of enable signal, the 3rd gate circuit is connected with the input of trigger 1202 with the output of the 4th gate circuit;
Wherein, when in the 3rd gate circuit and the 4th gate circuit, the output of at least one is high level, described external clock is followed in the output of trigger 1202.
With reference to Figure 10, show the structural representation of the clock drive system of a kind of charge pump provided by the invention;
In embodiments of the present invention, the 3rd gate circuit can with the first gate circuit in device embodiment one, and the 4th gate circuit can with the second gate circuit in device embodiment one, and the embodiment of the present invention does not repeat them here.
In another preferred embodiment of the invention, described second control module 1212 specifically can comprise:
7th gate circuit and the 8th gate circuit; The input termination enable signal of the 7th gate circuit and external clock, the input termination external clock of the 8th gate circuit and the reverse of enable signal, the 7th gate circuit is connected with the input of trigger 1202 with the output of the 8th gate circuit;
Wherein, when in the 7th gate circuit and the 8th gate circuit, the output of at least one is low level, external clock is followed in the output of trigger 1202.
With reference to Figure 11, show the structural representation of the clock drive system of a kind of charge pump provided by the invention;
In embodiments of the present invention, the 7th gate circuit can with the 5th gate circuit in device embodiment one, and the 8th gate circuit can with the 6th gate circuit in device embodiment one, and the embodiment of the present invention does not repeat them here.
In sum, the clock drive system of a kind of charge pump that the embodiment of the present invention provides, after enable signal changes high level into, clock signal can be made to follow external clock overturn, and make charge pump drive work timely, thus realize the accurate control of charge pump, electric charge pump performance is improved.
For system embodiment, due to itself and embodiment of the method basic simlarity, so description is fairly simple, relevant part illustrates see the part of embodiment of the method.
Each embodiment in this specification all adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar part mutually see.
Those skilled in the art should understand, the embodiment of the embodiment of the present invention can be provided as method, device or computer program.Therefore, the embodiment of the present invention can adopt the form of complete hardware embodiment, completely software implementation or the embodiment in conjunction with software and hardware aspect.And the embodiment of the present invention can adopt in one or more form wherein including the upper computer program implemented of computer-usable storage medium (including but not limited to magnetic disc store, CD-ROM, optical memory etc.) of computer usable program code.
The embodiment of the present invention describes with reference to according to the flow chart of the method for the embodiment of the present invention, terminal equipment (system) and computer program and/or block diagram.Should understand can by the combination of the flow process in each flow process in computer program instructions realization flow figure and/or block diagram and/or square frame and flow chart and/or block diagram and/or square frame.These computer program instructions can being provided to the processor of all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing terminal equipment to produce a machine, making the instruction performed by the processor of computer or other programmable data processing terminal equipment produce device for realizing the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
These computer program instructions also can be stored in can in the computer-readable memory that works in a specific way of vectoring computer or other programmable data processing terminal equipment, the instruction making to be stored in this computer-readable memory produces the manufacture comprising command device, and this command device realizes the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
These computer program instructions also can be loaded on computer or other programmable data processing terminal equipment, make to perform sequence of operations step to produce computer implemented process on computer or other programmable terminal equipment, thus the instruction performed on computer or other programmable terminal equipment is provided for the step realizing the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
Although described the preferred embodiment of the embodiment of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of embodiment of the present invention scope.
Finally, also it should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or terminal equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or terminal equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the terminal equipment comprising described key element and also there is other identical element.
Above the clock driving method of a kind of charge pump provided by the present invention and a kind of clock drive system of charge pump are described in detail, apply specific case herein to set forth principle of the present invention and execution mode, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (12)
1. a clock driving method for charge pump, is characterized in that, described method comprises: the output of foundation enable signal and external clock control trigger; Wherein, the output of described trigger is connected with the drive unit of described charge pump, is delivered to described drive unit with the clock signal exported by described trigger;
Wherein, the step of the output of described foundation enable signal and external clock control trigger comprises: when described enable signal is low level, keep the output of described trigger constant.
2. method according to claim 1, is characterized in that, the step of the output of described foundation enable signal and external clock control trigger also comprises: when described enable signal is high level, described external clock is followed in the output controlling described trigger.
3. method according to claim 1, is characterized in that, described when described enable signal is low level, keeps the step that the output of described trigger is constant, comprising:
Control the output of the first gate circuit and the second gate circuit according to described enable signal and described external clock, when described enable signal is low level, the output of described first gate circuit and described second gate circuit is low level; Wherein, enable signal and external clock described in the input termination of described first gate circuit, external clock described in the input termination of described second gate circuit and described enable signal reverse, described first gate circuit is connected with the input of described trigger with the output of the second gate circuit;
Output according to described first gate circuit and the second gate circuit controls the output of described trigger, when the output of described first gate circuit and described second gate circuit is low level, keeps the output of described trigger constant.
4. method according to claim 2, is characterized in that, described when described enable signal is high level, and the step of described external clock is followed in the output controlling described trigger, comprising:
Control the output of the 3rd gate circuit and the 4th gate circuit according to described enable signal and described external clock, when described enable signal is high level, in described 3rd gate circuit and described 4th gate circuit, the output of at least one is high level; Wherein, enable signal and external clock described in the input termination of described 3rd gate circuit, external clock described in the input termination of described 4th gate circuit and described enable signal reverse, the output of described 3rd gate circuit is connected with the input of described trigger with the output of the 4th gate circuit;
Output according to described 3rd gate circuit and described 4th gate circuit controls the output of described trigger, and when in described 3rd gate circuit and described 4th gate circuit, the output of at least one is high level, described external clock is followed in the output controlling described trigger.
5. method according to claim 1, is characterized in that, described when described enable signal is low level, keeps the constant step of the output of described trigger also to comprise:
Control the output of the 5th gate circuit and the 6th gate circuit according to described enable signal and described external clock, when described enable signal is low level, the output of described 5th gate circuit and the 6th gate circuit is high level; Wherein, enable signal and external clock described in the input termination of described 5th gate circuit, external clock described in the input termination of described 6th gate circuit and described enable signal reverse, described 5th gate circuit is connected with the input of described trigger with the output of the 6th gate circuit;
Output according to described 5th gate circuit and the 6th gate circuit controls the output of described trigger, when the output of described 5th gate circuit and the 6th gate circuit is high level, keeps the output of described trigger constant.
6. method according to claim 2, is characterized in that, described when described enable signal is high level, and the step of described external clock is followed in the output controlling described trigger, comprising:
Control the output of the 7th gate circuit and the 8th gate circuit according to described enable signal and described external clock, when described enable signal is high level, in described 7th gate circuit and described 8th gate circuit, the output of at least one is low level; Wherein, enable signal and external clock described in the input termination of described 7th gate circuit, external clock described in the input termination of described 8th gate circuit and described enable signal reverse, the output of described 7th gate circuit is connected with the input of described trigger with the output of the 8th gate circuit;
Output according to described 7th gate circuit and described 8th gate circuit controls the output of described trigger, and when in described 7th gate circuit and described 8th gate circuit, the output of at least one is low level, described external clock is followed in the output controlling described trigger.
7. a clock drive system for charge pump, is characterized in that, comprising: controller and trigger;
Wherein, described controller is used for the output according to enable signal and external clock control trigger; Wherein, the output of described trigger is connected with the drive unit of described charge pump, is delivered to described drive unit with the clock signal exported by described trigger;
Wherein, described controller comprises: the first control module, for when described enable signal is low level, keeps the output of described trigger constant.
8. system according to claim 7, is characterized in that, described controller also comprises:
Second control module, for when described enable signal is high level, described external clock is followed in the output controlling described trigger.
9. system according to claim 7, is characterized in that, described first control module, comprising: the first gate circuit and the second gate circuit; Enable signal and external clock described in the input termination of described first gate circuit, external clock described in the input termination of described second gate circuit and described enable signal reverse, described first gate circuit is connected with the input of described trigger with the output of the second gate circuit;
Wherein, when the output of described first gate circuit and described second gate circuit is low level, described trigger keeps exporting constant.
10. system according to claim 8, is characterized in that, described second control module, comprising: the 3rd gate circuit and the 4th gate circuit; Enable signal and external clock described in the input termination of described 3rd gate circuit, external clock described in the input termination of described 4th gate circuit and described enable signal reverse, described 3rd gate circuit is connected with the input of described trigger with the output of the 4th gate circuit;
Wherein, when in described 3rd gate circuit and described 4th gate circuit, the output of at least one is high level, described external clock is followed in the output of described trigger.
11. systems according to claim 7, is characterized in that, described first control module, comprising: the 5th gate circuit and the 6th gate circuit; Enable signal and described external clock described in the input termination of described 5th gate circuit, external clock described in the input termination of described 6th gate circuit and described enable signal reverse, described 5th gate circuit is connected with the input of described trigger with the output of the 6th gate circuit;
Wherein, when the output of described 5th gate circuit and the 6th gate circuit is high level, described trigger keeps exporting constant.
12. systems according to claim 8, is characterized in that, described second control module, comprising: the 7th gate circuit and the 8th gate circuit; Enable signal and external clock described in the input termination of described 7th gate circuit, external clock described in the input termination of described 8th gate circuit and described enable signal reverse, the output of described 7th gate circuit is connected with the input of described trigger with the output of the 8th gate circuit;
Wherein, when in described 7th gate circuit and described 8th gate circuit, the output of at least one is low level, described external clock is followed in the output of described trigger.
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Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |