CN105205012A - Method and device for reading data - Google Patents
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- CN105205012A CN105205012A CN201410298551.0A CN201410298551A CN105205012A CN 105205012 A CN105205012 A CN 105205012A CN 201410298551 A CN201410298551 A CN 201410298551A CN 105205012 A CN105205012 A CN 105205012A
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Abstract
The invention discloses a method and device for reading data. The method and device aim at solving the problem of low data reading efficiency. The method includes the steps that S1, a controller carries out control to read data of an appointed page from a storing device to a first cache, and meanwhile controls data stored in a second cache to be output to a serial interface; S2, the controller carries out control to read data of an appointed page from the storing device to the second cache, and meanwhile controls data stored in the first cache to be output to the serial interface; wherein if S1 or S2 is carried out in one-time data reading operation, S2 or S1 is carried out in next-time data reading operation, and data reading operation is sequentially and alternately carried out. The data of one cache are output while the data are written into one cache from a storage area, data reading time is effectively shortened accordingly, and data reading efficiency is improved.
Description
Technical field
The present invention relates to communication technical field, particularly relate to a kind of method for reading data and a kind of data fetch device.
Background technology
Flash often represents the meaning of FlashMemory in electronics and semiconductor applications, and namely at ordinary times said " flash memory ", be entirely named as FlashEEPROMMemory, it is the one of storage chip, can be revised the data of the inside by specific program.
Flash storage combines the strong point of ROM and RAM, not only possesses Electrical Erasable programmable read only memory (ElectricallyErasableProgrammableRead-OnlyMemory, EEPROM) performance, data (advantage as nonvolatile random access memory NVRAM) can also be read fast, data can not be lost because of power-off.
NANDFLASH internal memory is the one of Flash internal memory, the non-linear macroelement pattern of its inner employing, and the realization for solid-state large-capacity internal memory provides cheap effective solution.The advantages such as it is comparatively large that NANDFLASH storer has capacity, and speed of rewriting is fast, are applicable to the storage of mass data, have thus arrived and applied more and more widely, as embedded product comprises the USB flash disk etc. of digital camera, MP3 walkman memory card, compact.
In usual chip, NANDFLASH storer is that the mode taking page to read reads data, is namely once read in a large capacity cache of built-in chip type by a page data (such as 4KB), more outwards export data by address from buffer memory.As shown in Figure 1, t1 is the time that the inner page of NANDFLASH reads, and t2 is the time that the data of one page outwards export in order.
Because NANDFLASH is after a page data of inside reads buffer memory completely, then from buffer memory, read data externally export.Therefore, after a page data exports, just can restart the reading of next page data, in chip, the output time of data is t1+t2.
Because common page capacity is comparatively large, data read buffer memory from NANDFLASH, then export all consuming time comparatively large from buffer memory, affect data output efficiency.
Summary of the invention
Embodiment of the present invention technical matters to be solved is to provide a kind of method for reading data, to solve the lower problem of data reading performance using redundancy.
Accordingly, the embodiment of the present invention additionally provides a kind of data fetch device, in order to ensure the implementation and application of said method.
In order to solve the problem, the invention discloses a kind of method for reading data, comprising: S1, controller control reads the data of specific page in the first buffer memory from storer, controls the data stored in the second buffer memory to output to serial line interface simultaneously; S2, described controller control reads the data of specific page in described second buffer memory from described storer, controls the data stored in described first buffer memory to output to described serial line interface simultaneously; Wherein, if perform S1 or S2 in a data read operation, then perform S2 or S1 in data read operation next time, alternately perform data read operation successively.
Optionally, described controller control reads the data of specific page in the first buffer memory from storer, control the data stored in the second buffer memory to output to serial line interface simultaneously, comprising: described controller sends reading command to described storer, send output order to described second buffer memory simultaneously; Described storer reads the data of specific page according to described reading command and is deposited in described first buffer memory; Meanwhile, the data of storage are outputted to serial line interface according to described output order by described second buffer memory.
Optionally, described controller control reads the data of specific page in described second buffer memory from described storer, control the data stored in described first buffer memory to output to described serial line interface simultaneously, comprise: described controller sends reading command to described storer, send output order to described first buffer memory simultaneously; Described storer reads the data of specific page according to described reading command and is deposited in described second buffer memory; Meanwhile, the data of storage are outputted to serial line interface according to described output order by described first buffer memory.
Optionally, described storer reads the data of specific page according to described reading command, comprising: described storer obtains the page address of specific page from described reading command; Data are read from the page address of described specific page.
Optionally, according to described output order, the data of storage are outputted to serial line interface, comprising: from described output order, obtain OPADD, the data of storage are outputted to described Input Address by described serial line interface.
Accordingly, the invention also discloses a kind of data fetch device, comprising: the first read module, from storer, read the data of specific page in the first buffer memory for controller control, control the data stored in the second buffer memory to output to serial line interface simultaneously; Second read module, reads the data of specific page in described second buffer memory for controller control, controls the data stored in described first buffer memory to output to described serial line interface simultaneously from described storer; Wherein, triggering first read module and the second read module is replaced.
Optionally, described first read module, comprising: first sends submodule, sends reading command to described storer for described controller, sends output order to described second buffer memory simultaneously, to trigger the first reading submodule and the first input submodule simultaneously; First reading submodule, reads the data of specific page for described storer according to described reading command and is deposited in described first buffer memory; The data of storage are outputted to serial line interface for described second buffer memory according to described output order by the first input submodule.
Optionally, described second read module, comprising: second sends submodule, sends reading command to described storer for described controller, sends output order to described first buffer memory simultaneously, to trigger the second reading submodule and the second input submodule simultaneously; Second reading submodule, reads the data of specific page for described storer according to described reading command and is deposited in described second buffer memory; The data of storage are outputted to serial line interface for described first buffer memory according to described output order by the second input submodule.
Optionally, described first reading submodule, obtains the page address of specific page from described reading command for described storer; From the page address of described specific page, read data and be deposited in described first buffer memory; Described second reading submodule, obtains the page address of specific page from described reading command for described storer; From the page address of described specific page, read data and be deposited in described second buffer memory.
Optionally, described first input submodule, obtains OPADD for described second buffer memory, the data of storage is outputted to described Input Address by described serial line interface from described output order; Described second input submodule, obtains OPADD for described first buffer memory, the data of storage is outputted to described Input Address by described serial line interface from described output order.
Compared with prior art, the embodiment of the present invention comprises following advantage:
If perform S1 or S2 in a data read operation, then perform S2 or S1 in data read operation next time, alternately perform data read operation successively, wherein S1 is that sky controller controls to read the data of specific page from storer in the first buffer memory, controls the data stored in the second buffer memory to output to serial line interface simultaneously; And S2 is that described controller controls to read the data of specific page from described storer in described second buffer memory, control the data stored in described first buffer memory to output to described serial line interface simultaneously, namely while data are write a buffer memory from memory block, export the data of another buffer memory, thus effectively decrease the time of digital independent, improve data reading performance using redundancy.
Accompanying drawing explanation
Fig. 1 is the digital independent timing waveform schematic diagram provided in background technology;
Fig. 2 is the flow chart of steps of a kind of method for reading data embodiment of the present invention;
Fig. 3 is the structural representation of a kind of chip in the embodiment of the present invention two;
Fig. 4 A and Fig. 4 B is the timing waveform schematic diagram of data read operation;
Fig. 5 is the structured flowchart of a kind of data fetch device embodiment of the present invention;
Fig. 6 is the structured flowchart of a kind of data fetch device embodiment of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
One of core idea of the embodiment of the present invention is, the embodiment of the present invention provides a kind of method for reading data, to solve the lower problem of data reading performance using redundancy.If perform S1 or S2 in a data read operation, then perform S2 or S1 in data read operation next time, alternately perform data read operation successively, wherein S1 is that sky controller controls to read the data of specific page from storer in the first buffer memory, controls the data stored in the second buffer memory to output to serial line interface simultaneously; And S2 is that described controller controls to read the data of specific page from described storer in described second buffer memory, control the data stored in described first buffer memory to output to described serial line interface simultaneously, namely while data are write a buffer memory from memory block, export the data of another buffer memory, thus effectively decrease the time of digital independent, improve data reading performance using redundancy.
Embodiment one
With reference to Fig. 2, show the flow chart of steps of a kind of method for reading data embodiment of the present invention, specifically can comprise the steps:
S1, controller control reads the data of specific page in the first buffer memory from storer, controls the data stored in the second buffer memory to output to serial line interface simultaneously.
S2, described controller control reads the data of specific page in described second buffer memory from described storer, controls the data stored in described first buffer memory to output to described serial line interface simultaneously.
Wherein, if perform S1 or S2 in a data read operation, then perform S2 or S1 in data read operation next time, alternately perform data read operation successively.
In order to improve the reading efficiency of data in chip, the embodiment of the present invention arranges two buffer memorys in the chips, to replace the data in buffer memory, thus when a buffer memory stores the data in storer, the data that another buffer memory is stored output to serial line interface.
In the embodiment of the present invention, storer is NANDFLASH storer, reads and writes data in units of page, and wherein, page is a kind of storage cell, and if capacity is 4K, namely a page data is all read in each read operation, as read the 4K data that one page stores.
Two buffer memorys are provided with in chip, be respectively the first buffer memory and the second buffer memory, both can adopt identical buffer memory, also different buffer memory can be adopted, the embodiment of the present invention is not construed as limiting this, if the first buffer memory is buffer register (buffer), the second buffer memory is cache memory (cache); Output interface adopts serial line interface, as Serial Peripheral Interface (SPI) (SerialPeripheralInterface, SPI).
Due to before reading data first from NANDFLASH, first buffer memory and the second buffer memory are all without the data in NANDFLASH, therefore, chip when reading data first from NANDFLASH, can read the data of specific page to the first buffer memory or the second buffer memory by controller from NANDFLASH, the buffer memory not receiving the data of specific page in NANDFLASH wouldn't export data to serial line interface.
Suppose, read the data of specific page to the first buffer memory from NANDFLASH during read operation first; Then perform above-mentioned steps S2 during second time read operation, the data namely reading specific page from described storer, in described second buffer memory, control the data stored in described first buffer memory to output to described serial line interface simultaneously; Then at third time read operation execution above-mentioned steps S1; Alternately perform data read operation according to this, namely perform step S1 when the odd-times read operation except first, perform step S2 when even-times read operation.
In contrast, if first read operation time by the digital independent of NANDFLASH specific page to the second buffer memory, then after this odd-times read operation time perform step S2, when even-times read operation perform step S1.
To sum up, if perform S1 or S2 in a data read operation, then perform S2 or S1 in data read operation next time, alternately perform data read operation successively, wherein S1 is that sky controller controls to read the data of specific page from storer in the first buffer memory, controls the data stored in the second buffer memory to output to serial line interface simultaneously; And S2 is that described controller controls to read the data of specific page from described storer in described second buffer memory, control the data stored in described first buffer memory to output to described serial line interface simultaneously, namely while data are write a buffer memory from memory block, export the data of another buffer memory, thus effectively decrease the time of digital independent, improve data reading performance using redundancy.
Embodiment two
On the basis of above-described embodiment, the present embodiment discusses the method for the digital independent that to be hocketed by two buffer memorys further.
Then the control of above-mentioned steps S1 controller reads the data of specific page in the first buffer memory from storer, control the data stored in the second buffer memory to output to serial line interface simultaneously, comprise: described controller sends reading command to described storer, send output order to described second buffer memory simultaneously; Described storer reads the data of specific page according to described reading command and is deposited in described first buffer memory; Meanwhile, the data of storage are outputted to serial line interface according to described output order by described second buffer memory.
The control of above-mentioned steps S2 controller reads the data of specific page in described second buffer memory from described storer, control the data stored in described first buffer memory to output to described serial line interface simultaneously, comprise: described controller sends reading command to described storer, send output order to described first buffer memory simultaneously; Described storer reads the data of specific page according to described reading command and is deposited in described second buffer memory; Meanwhile, the data of storage are outputted to serial line interface according to described output order by described first buffer memory.
Wherein, storer reads the data of specific page according to described reading command, comprising: described storer obtains the page address of specific page from described reading command; Data are read from the page address of described specific page.
According to described output order, the data of storage are outputted to serial line interface, comprising: from described output order, obtain OPADD, the data of storage are outputted to described Input Address by described serial line interface.
With reference to Fig. 3, show the structural representation of a kind of chip in the embodiment of the present invention two.
Suppose, storer is NANDFLASH, and the first buffer memory is buffer register (buffer), and the second buffer memory is cache memory (cache), and serial line interface adopts SPI interface, discusses method for reading data as example.
When reading data in chip first from NANDFLASH, controller can be adopted to send reading command to NANDFLASH, NANDFLASH obtains the page address of specific page as Page0 from this reading command, and then NANDFLASH reads the data of specific page in buffer or cache.
If first by the digital independent of specific page in buffer, when even-times then from second time reads data, controller sends reading command to NANDFLASH, send output order to buffer simultaneously, to make NANDFLASH read in cache by specific page data, the data that buffer once reads in before being stored simultaneously output in SPI interface; When odd-times from third time reads data, controller sends reading command to NANDFLASH, send output order to cache, to make NANDFLASH read in buffer by specific page data, the data that cache once reads in before being stored simultaneously output in SPI interface simultaneously.
In contrast, if first by the digital independent of specific page in cache, when even-times then from second time reads data, controller sends reading command to NANDFLASH, send output order to cache simultaneously, to make NANDFLASH read in buffer by specific page data, the data that cache once reads in before being stored simultaneously output in SPI interface; When odd-times from third time reads data, controller sends reading command to NANDFLASH, send output order to buffer, to make NANDFLASH read in cache by specific page data, the data that buffer once reads in before being stored simultaneously output in SPI interface simultaneously.
Wherein, frontly once refer to the once front of current read data number of times, read data as current for second time, then before once headed by time, and for example currently reading data for third time, then be once for the second time before.
When NANDFLASH receives reading command, the page address of specific page is obtained from reading command, as Pagen, Pagen+1 etc., the cashing indication of buffer memory can also be obtained from reading command, as buffer memory name, buffer memory numbering etc. uniquely can represent the cashing indication of a buffer memory, carry out buffer memory to determine the data of specific page to be input in buffer or cache, then from the page address of described specific page, read data, and according to cashing indication by data buffer storage in buffer or cache.
Buffer, after receiving output order, can obtain OPADD from output order, then the data of storage is outputted to described Input Address by described SPI interface.
Cache, after receiving output order, can obtain OPADD from output order, then the data of storage is outputted to described Input Address by described SPI interface.
Suppose, the data reading specific page from storer NANDFLASH are t1 to the time of buffer memory (buffer or cache), can regard Data within the chip as and read the time; The page data exporting storage from buffer or cache is t2 to the time of SPI interface, can regard chip as and outwards export data time, then the time of carrying out a data read operation in the chips just depends on that internal data reads time t1 and outwards exports that time value larger in data time t2.
Wherein, when internal data reading time t1 is greater than outside output data time t2, the timing waveform of a data read operation is carried out as shown in Figure 4 A in chip, wherein by the data of NANDFLASH alternately input buffer and cache buffer memory, and cache or buffer to SPI interface export data reach t2 time, data export complete, after waiting until the time period of (t1-t2), carry out data output by another buffer memory.Namely chip internal is that NANDFLASH reads continuously, and the data after reading, in turn stored in buffer and cache, realize inner seamless continuous reading.
When internal data reading time t1 is less than outside output data time t2, the timing waveform of a data read operation is carried out as shown in Figure 4 B in chip, wherein, in buffer and cache, the data of buffer memory alternately output to SPI interface successively, and the digital independent of specific page is t1 to the time in buffer or cache by NANDFLASH, by the time (t2-t1) time period, NANDFLASH again reads page data and outputs in another buffer memory (cache or buffer).Namely chip internal is that two buffer memorys alternately export data continuously, realizes inner seamless continuous output.
To sum up, can alternately keep in the data read out in NANDFLASH by two buffer memorys, thus realize the continuous reading of NANDFLASH inside.Therefore be finished successively without the need to waiting for digital independent and exporting, but continuous unremitting reading and output data, substantially increase the data reading speed of NANDFLASH.
It should be noted that, for embodiment of the method, in order to simple description, therefore it is all expressed as a series of combination of actions, but those skilled in the art should know, the embodiment of the present invention is not by the restriction of described sequence of movement, because according to the embodiment of the present invention, some step can adopt other orders or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in instructions all belongs to preferred embodiment, and involved action might not be that the embodiment of the present invention is necessary.
With reference to Fig. 5, show the structured flowchart of a kind of data fetch device embodiment of the present invention, specifically can comprise as lower module:
First read module 502, reads the data of specific page in the first buffer memory for controller control, controls the data stored in the second buffer memory to output to serial line interface simultaneously from storer.
Second read module 504, reads the data of specific page in described second buffer memory for controller control, controls the data stored in described first buffer memory to output to described serial line interface simultaneously from described storer.
Wherein, the data of the second buffer memory or the first buffer memory, so that data in storer are replaced input first buffer memory and the second buffer memory, are alternately exported by alternately triggering first read module 502 and the second read module 504 simultaneously.
In sum, the data of the second buffer memory or the first buffer memory, so that data in storer are replaced input first buffer memory and the second buffer memory, are alternately exported by alternately triggering first read module 502 and the second read module 504 simultaneously.Namely while data are write a buffer memory from memory block, export the data of another buffer memory, thus effectively decrease the time of digital independent, improve data reading performance using redundancy.
With reference to Fig. 6, show the structured flowchart of a kind of data fetch device embodiment of the present invention, specifically can comprise as lower module:
Described first read module 502, comprising: first sends submodule 5022, sends reading command to described storer for described controller, sends output order to described second buffer memory simultaneously, to trigger the first reading submodule and the first input submodule simultaneously; First reading submodule 5024, reads the data of specific page for described storer according to described reading command and is deposited in described first buffer memory; The data of storage are outputted to serial line interface for described second buffer memory according to described output order by the first input submodule 5026.
Described second read module 504, comprising: second sends submodule 5042, sends reading command to described storer for described controller, sends output order to described first buffer memory simultaneously, to trigger the second reading submodule and the second input submodule simultaneously; Second reading submodule 5044, reads the data of specific page for described storer according to described reading command and is deposited in described second buffer memory; The data of storage are outputted to serial line interface for described first buffer memory according to described output order by the second input submodule 5046.
Optionally, described first reading submodule 5024, obtains the page address of specific page from described reading command for described storer; From the page address of described specific page, read data and be deposited in described first buffer memory; Described second reading submodule 5044, obtains the page address of specific page from described reading command for described storer; From the page address of described specific page, read data and be deposited in described second buffer memory.
Optionally, described first input submodule 5026, obtains OPADD for described second buffer memory, the data of storage is outputted to described Input Address by described serial line interface from described output order; Described second input submodule 5046, obtains OPADD for described first buffer memory, the data of storage is outputted to described Input Address by described serial line interface from described output order.
To sum up, can alternately keep in the data read out in NANDFLASH by two buffer memorys, thus realize the continuous reading of NANDFLASH inside.Therefore be finished successively without the need to waiting for digital independent and exporting, but continuous unremitting reading and output data, substantially increase the data reading speed of NANDFLASH.
For device embodiment, due to itself and embodiment of the method basic simlarity, so description is fairly simple, relevant part illustrates see the part of embodiment of the method.
Each embodiment in this instructions all adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar part mutually see.
Those skilled in the art should understand, the embodiment of the embodiment of the present invention can be provided as method, device or computer program.Therefore, the embodiment of the present invention can adopt the form of complete hardware embodiment, completely software implementation or the embodiment in conjunction with software and hardware aspect.And the embodiment of the present invention can adopt in one or more form wherein including the upper computer program implemented of computer-usable storage medium (including but not limited to magnetic disk memory, CD-ROM, optical memory etc.) of computer usable program code.
The embodiment of the present invention describes with reference to according to the process flow diagram of the method for the embodiment of the present invention, terminal device (system) and computer program and/or block scheme.Should understand can by the combination of the flow process in each flow process in computer program instructions realization flow figure and/or block scheme and/or square frame and process flow diagram and/or block scheme and/or square frame.These computer program instructions can being provided to the processor of multi-purpose computer, special purpose computer, Embedded Processor or other programmable data processing terminal equipment to produce a machine, making the instruction performed by the processor of computing machine or other programmable data processing terminal equipment produce device for realizing the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.
These computer program instructions also can be stored in can in the computer-readable memory that works in a specific way of vectoring computer or other programmable data processing terminal equipment, the instruction making to be stored in this computer-readable memory produces the manufacture comprising command device, and this command device realizes the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.
These computer program instructions also can be loaded on computing machine or other programmable data processing terminal equipment, make to perform sequence of operations step to produce computer implemented process on computing machine or other programmable terminal equipment, thus the instruction performed on computing machine or other programmable terminal equipment is provided for the step realizing the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.
Although described the preferred embodiment of the embodiment of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of embodiment of the present invention scope.
Finally, also it should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operational zone, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or terminal device and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or terminal device.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the terminal device comprising described key element and also there is other identical element.
Above to a kind of method for reading data provided by the present invention and a kind of data fetch device, be described in detail, apply specific case herein to set forth principle of the present invention and embodiment, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1. a method for reading data, is characterized in that, comprising:
S1, controller control reads the data of specific page in the first buffer memory from storer, controls the data stored in the second buffer memory to output to serial line interface simultaneously;
S2, described controller control reads the data of specific page in described second buffer memory from described storer, controls the data stored in described first buffer memory to output to described serial line interface simultaneously;
Wherein, if perform S1 or S2 in a data read operation, then perform S2 or S1 in data read operation next time, alternately perform data read operation successively.
2. method according to claim 1, is characterized in that, described controller control reads the data of specific page in the first buffer memory from storer, controls the data stored in the second buffer memory to output to serial line interface simultaneously, comprising:
Described controller sends reading command to described storer, sends output order to described second buffer memory simultaneously;
Described storer reads the data of specific page according to described reading command and is deposited in described first buffer memory;
Meanwhile, the data of storage are outputted to serial line interface according to described output order by described second buffer memory.
3. method according to claim 1, is characterized in that, described controller control reads the data of specific page in described second buffer memory from described storer, controls the data stored in described first buffer memory to output to described serial line interface simultaneously, comprising:
Described controller sends reading command to described storer, sends output order to described first buffer memory simultaneously;
Described storer reads the data of specific page according to described reading command and is deposited in described second buffer memory;
Meanwhile, the data of storage are outputted to serial line interface according to described output order by described first buffer memory.
4. according to the method in claim 2 or 3, it is characterized in that, described storer reads the data of specific page according to described reading command, comprising:
Described storer obtains the page address of specific page from described reading command;
Data are read from the page address of described specific page.
5. according to the method in claim 2 or 3, it is characterized in that, according to described output order, the data of storage outputted to serial line interface, comprising:
From described output order, obtain OPADD, the data of storage are outputted to described Input Address by described serial line interface.
6. a data fetch device, is characterized in that, comprising:
First read module, reads the data of specific page in the first buffer memory for controller control, controls the data stored in the second buffer memory to output to serial line interface simultaneously from storer;
Second read module, reads the data of specific page in described second buffer memory for controller control, controls the data stored in described first buffer memory to output to described serial line interface simultaneously from described storer;
Wherein, triggering first read module and the second read module is replaced.
7. device according to claim 6, is characterized in that, described first read module, comprising:
First sends submodule, sends reading command to described storer for described controller, sends output order to described second buffer memory simultaneously, to trigger the first reading submodule and the first input submodule simultaneously;
First reading submodule, reads the data of specific page for described storer according to described reading command and is deposited in described first buffer memory;
The data of storage are outputted to serial line interface for described second buffer memory according to described output order by the first input submodule.
8. device according to claim 6, is characterized in that, described second read module, comprising:
Second sends submodule, sends reading command to described storer for described controller, sends output order to described first buffer memory simultaneously, to trigger the second reading submodule and the second input submodule simultaneously;
Second reading submodule, reads the data of specific page for described storer according to described reading command and is deposited in described second buffer memory;
The data of storage are outputted to serial line interface for described first buffer memory according to described output order by the second input submodule.
9. the device according to claim 7 or 8, is characterized in that:
Described first reading submodule, obtains the page address of specific page from described reading command for described storer; From the page address of described specific page, read data and be deposited in described first buffer memory;
Described second reading submodule, obtains the page address of specific page from described reading command for described storer; From the page address of described specific page, read data and be deposited in described second buffer memory.
10. the device according to claim 7 or 8, is characterized in that:
Described first input submodule, obtains OPADD for described second buffer memory, the data of storage is outputted to described Input Address by described serial line interface from described output order;
Described second input submodule, obtains OPADD for described first buffer memory, the data of storage is outputted to described Input Address by described serial line interface from described output order.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2017210868A1 (en) * | 2016-06-07 | 2017-12-14 | 深圳市大疆创新科技有限公司 | Data processing method, device and system |
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