CN102610265A - Flash memory - Google Patents
Flash memory Download PDFInfo
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- CN102610265A CN102610265A CN2012100822613A CN201210082261A CN102610265A CN 102610265 A CN102610265 A CN 102610265A CN 2012100822613 A CN2012100822613 A CN 2012100822613A CN 201210082261 A CN201210082261 A CN 201210082261A CN 102610265 A CN102610265 A CN 102610265A
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Abstract
The invention relates to a flash memory which comprises a storage array, a sensitive amplifier and a buffer which are connected in sequence, wherein the buffer is connected with an external interface of the flash memory, the storage array is used for storing data, the sensitive amplifier is used for reading the data sent from the storage array and transmitting the data to the buffer according to read instructions and data addresses sent by the buffer, the buffer is used for receiving the read instructions and the data addresses from the external interface and transmitting the read instructions and the data addresses to the sensitive amplifier, and the buffer is also used for buffering the data sent by the sensitive amplifier and outputting the data by the external interface. The flash memory can improve working efficiency and responding speed.
Description
Technical Field
The invention relates to the technical field of memory design, in particular to a flash memory.
Background
Flash memory (Flash) is a memory with a fast response speed. As shown in fig. 1, a conventional Flash (labeled as 11) includes two parts, namely a memory array 101 and a sense amplifier 102, connected together, where the memory array 101 is used for storing data, and the sense amplifier 102 is connected to an external interface 12 of the Flash, and is used for reading out corresponding data stored in the memory array 101 according to a read instruction and a data address sent by the external interface 12, and outputting the corresponding data through the external interface 12.
Therefore, the operation of reading data by using the existing Flash at least comprises the following two steps: the first step is that the sense amplifier 102 reads out corresponding data from the storage array 101, and the second step is that the sense amplifier 102 sends the data to the external interface 12, whereas in the prior art, the speed of the second step is much faster than that of the first step, so that in the working process of the existing Flash, the external interface 12 needs to consume a lot of time to wait for the sense amplifier 102 to read the data from the storage array 101, and is also in an idle state for a long time, which not only reduces the working efficiency of the Flash, but also makes the response speed of the Flash lower.
Disclosure of Invention
The invention aims to provide a flash memory, which can improve the working efficiency and the response speed.
The technical scheme for solving the technical problems is as follows: a Flash memory Flash comprises a memory array, a sensitive amplifier and a buffer which are connected in sequence; the buffer is connected with an external interface of the Flash; wherein,
the storage array is used for storing data;
the sensitive amplifier is used for reading data from the memory array according to the reading instruction and the data address sent by the buffer and sending the data to the buffer;
the buffer is used for receiving the read instruction and the data address from the external interface and sending the read instruction and the data address to the sensitive amplifier; and buffering the data sent by the sensitive amplifier and outputting the data through the external interface.
The invention has the beneficial effects that: the Flash adds a buffer between the sensitive amplifier and the external interface, the sensitive amplifier is only used for reading data from the memory array, and the buffer bears the work of buffering the data read by the sensitive amplifier and outputting the data to the external interface, thus, the two parts of work of reading the data by the sensitive amplifier and outputting the data by the buffer can be simultaneously carried out, after the buffer outputs all the buffered data to the external interface, the sensitive amplifier can immediately send the next batch of read data to the buffer, therefore, the external interface does not need to be in an idle state or only has little time, the working efficiency of the Flash is greatly improved, and the response speed of the Flash to external instructions is also improved.
On the basis of the technical scheme, the invention can be further improved as follows:
further, the data address is an address of one word line;
and the sensitive amplifier is used for reading out the data stored by the word line from the memory array according to the read instruction sent by the buffer and the address of the word line and sending the data to the buffer in parallel.
Further, the data address is an address of a page;
the sensitive amplifier is used for reading out the data stored in the page from the memory array according to the read instruction sent by the buffer and the address of the page and sending the data to the buffer in parallel.
Furthermore, the buffer is also used for buffering the data sent by the external interface and sending the data to the sensitive amplifier;
the sensitive amplifier is also used for sending the data sent by the buffer to the storage array for storage.
Drawings
FIG. 1 is a diagram showing a conventional Flash structure;
FIG. 2 is a diagram of a structure of Flash according to the present invention.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
Fig. 2 is a structural diagram of a Flash memory (Flash) according to the present invention. As shown in fig. 2, the Flash (reference numeral 21) includes a storage array 201, a sense amplifier 202 and a buffer 203, which are connected in sequence; the buffer 203 is connected with the external interface 22 of the Flash; wherein,
the storage array 201 is used for storing data;
the sense amplifier 202 is used for reading data from the memory array 201 and supplying the data to the buffer 203 according to a read command and a data address supplied from the buffer 203. The data address refers to a storage address of the data to be read by the read command in the memory array 201, and the sense amplifier 202 can only read the corresponding data from the memory array 201 according to the read command and the data address.
The buffer 203 is used for receiving a read command and a data address from the external interface 22 and sending the read command and the data address to the sense amplifier 202; data from sense amplifiers 202 are buffered and output through external interface 22.
Therefore, the Flash in the invention adds the buffer between the sensitive amplifier and the external interface, the sensitive amplifier is only used for reading data from the memory array, and the buffer bears the work of buffering the data read by the sensitive amplifier and outputting the data to the external interface, so that the two parts of work of reading the data by the sensitive amplifier and outputting the data by the buffer can be simultaneously carried out, and the sensitive amplifier can immediately send the next batch of read data to the buffer after the buffer outputs all the buffered data to the external interface, therefore, the external interface does not need to be in an idle state or only has little time, thereby greatly improving the working efficiency of the Flash and simultaneously improving the response speed of the Flash to external instructions.
In the present invention, the data address sent to the buffer 203 by the external interface 22 may be an address of a word line, so that the read command means that all data (e.g. 1kbyte, 2kbyte or more data) stored on the word line in the memory array 201 is read out completely, in this case, the sense amplifier 202 is configured to read out the data stored by the word line from the memory array 201 and send the data to the buffer 203 in parallel according to the read command sent by the buffer 203 and the address of the word line, and the buffer 203 further outputs the data to the external interface 22 in parallel or in serial.
In addition, the data address sent to the buffer 203 by the external interface 22 may be an address of a page, that is, addresses of a plurality of word lines, so that the above-mentioned read command means that all the data (for example, 4kbyte or more data) stored on the page in the memory array 201 is read out, in this case, the sense amplifier 202 is configured to read out the data stored on the page from the memory array 201 and send the data to the buffer 203 in parallel according to the read command sent from the buffer 203 and the address of the page, and then output the data to the external interface 22 in parallel or in serial by the buffer 203.
Of course, there are other forms of data addresses described above, and accordingly, the amount of data read by sense amplifiers 202 may vary, and such cases are within the scope of the present invention.
In the case where the amount of data read out at a time by the sense amplifier 202 is the same, the capacity of the buffer 203 in the present invention may be set to the amount of data read out at a time by the sense amplifier 202, or larger. Of course, if the amount of data read out at a time by sense amplifier 202 is different, the capacity of buffer 203 may be set to the maximum amount of data read out at a time by sense amplifier 202, or larger.
The invention can read data from Flash, write data into Flash, and because of the setting of buffer 203, the invention can realize that the sensitive amplifier 202 writes data into the memory array 201 and the buffer 203 outputs data to the external interface 22. At this time, the buffer 203 is also used for buffering the data sent from the external interface 22 and sending the data to the sense amplifier 202; the sense amplifier 202 is also used to send the data from the buffer 203 to the memory array 201 for storage.
It can be seen that after the sense amplifier 202 outputs the read data to the buffer 203, the data sent from the buffer 203 can be written into the memory array 201 immediately, and at the same time, the buffer 203 sends the data sent from the sense amplifier 202 to the external interface 22 in a parallel or serial manner, which also improves the working efficiency and response speed of Flash.
It can be seen that the present invention has the following advantages:
(1) the Flash adds a buffer between the sensitive amplifier and the external interface, the sensitive amplifier is only used for reading data from the memory array, and the buffer bears the work of buffering the data read by the sensitive amplifier and outputting the data to the external interface, thus, the two parts of work of reading the data by the sensitive amplifier and outputting the data by the buffer can be simultaneously carried out, after the buffer outputs all the buffered data to the external interface, the sensitive amplifier can immediately send the next batch of read data to the buffer, therefore, the external interface does not need to be in an idle state or only has little time, the working efficiency of the Flash is greatly improved, and the response speed of the Flash to external instructions is also improved.
(2) In the invention, after the read data is output to the buffer by the sensitive amplifier, the data sent by the buffer can be immediately written into the memory array, and meanwhile, the data sent by the sensitive amplifier is sent to the external interface by the buffer in a parallel or serial mode, which is also beneficial to improving the working efficiency and the response speed of Flash.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (4)
1. A Flash memory Flash is characterized by comprising a storage array, a sensitive amplifier and a buffer which are sequentially connected; the buffer is connected with an external interface of the Flash; wherein,
the storage array is used for storing data;
the sensitive amplifier is used for reading data from the memory array according to the reading instruction and the data address sent by the buffer and sending the data to the buffer;
the buffer is used for receiving the read instruction and the data address from the external interface and sending the read instruction and the data address to the sensitive amplifier; and buffering the data sent by the sensitive amplifier and outputting the data through the external interface.
2. Flash according to claim 1, characterised in that the data address is the address of a word line;
and the sensitive amplifier is used for reading out the data stored by the word line from the memory array according to the read instruction sent by the buffer and the address of the word line and sending the data to the buffer in parallel.
3. The Flash according to claim 1, wherein the data address is an address of a page;
the sensitive amplifier is used for reading out the data stored in the page from the memory array according to the read instruction sent by the buffer and the address of the page and sending the data to the buffer in parallel.
4. Flash according to claim 1, characterized in that,
the buffer is also used for buffering the data sent by the external interface and sending the data to the sensitive amplifier;
the sensitive amplifier is also used for sending the data sent by the buffer to the storage array for storage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100822613A CN102610265A (en) | 2012-03-26 | 2012-03-26 | Flash memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100822613A CN102610265A (en) | 2012-03-26 | 2012-03-26 | Flash memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102610265A true CN102610265A (en) | 2012-07-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012100822613A Pending CN102610265A (en) | 2012-03-26 | 2012-03-26 | Flash memory |
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| CN (1) | CN102610265A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105205012A (en) * | 2014-06-26 | 2015-12-30 | 北京兆易创新科技股份有限公司 | Method and device for reading data |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1890753A (en) * | 2003-12-30 | 2007-01-03 | 英特尔公司 | Method and apparatus for multiple row caches per bank |
| US20070300012A1 (en) * | 2006-06-26 | 2007-12-27 | Micron Technology, Inc. | Method for substantially uninterrupted cache readout |
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2012
- 2012-03-26 CN CN2012100822613A patent/CN102610265A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1890753A (en) * | 2003-12-30 | 2007-01-03 | 英特尔公司 | Method and apparatus for multiple row caches per bank |
| US20070300012A1 (en) * | 2006-06-26 | 2007-12-27 | Micron Technology, Inc. | Method for substantially uninterrupted cache readout |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105205012A (en) * | 2014-06-26 | 2015-12-30 | 北京兆易创新科技股份有限公司 | Method and device for reading data |
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Address after: 100084 Beijing City, Haidian District Xueyuan Road No. 30, large industrial building A block 12 layer Applicant after: GigaDevice Semiconductor (Beijing) Inc. Address before: 100084 Room 301, B building, Tsinghua Science and Technology Park, Haidian District, Beijing Applicant before: GigaDevice Semiconductor Inc. |
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Free format text: CORRECT: APPLICANT; FROM: BEIJING GIGADEVICE SEMICONDUCTOR INC. TO: BEIJING GIGADEVICE SEMICONDUCTOR CO., LTD. |
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Application publication date: 20120725 |