CN103684425A - Dual-mode frequency divider circuit - Google Patents
Dual-mode frequency divider circuit Download PDFInfo
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- CN103684425A CN103684425A CN201210336536.1A CN201210336536A CN103684425A CN 103684425 A CN103684425 A CN 103684425A CN 201210336536 A CN201210336536 A CN 201210336536A CN 103684425 A CN103684425 A CN 103684425A
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Abstract
The invention provides a dual-mode frequency divider circuit. The dual-mode frequency divider circuit includes a divide-by-N and divide-by-N+1 dual-mode frequency division module, a first flip-flop, a control mode terminal and a logic gate, wherein the divide-by-N and divide-by-N+1 dual-mode frequency division module is used for carrying out N or N+1 frequency division on an input signal so as to generate a first frequency division signal; the first flip-flop is used for carrying out frequency division on the first frequency division signal so as to generate a second frequency division signal; the control mode terminal is used for inputting a first mode signal and a second mode signal; the logic gate is connected with the first flip-flop, the divide-by-N and divide-by-N+1 dual-mode frequency division module and the control mode terminal; when the control mode terminal inputs the first mode signal, the divide-by-N and divide-by-N+1 dual-mode frequency division module is controlled by the logic gate to work in a first frequency division mode; when the control mode terminal inputs the second mode signal, the divide-by-N and divide-by-N+1 dual-mode frequency division module is controlled by the logic gate to be switched between the first frequency division mode and a second frequency division mode according to the second frequency division signal. The dual-mode frequency divider circuit facilitates the construction of a dual-mode frequency divider structure according to an actually required frequency division value, and achieves convenience in memory.
Description
Technical field
The present invention relates to digital circuit technique field, particularly a kind of dual-mode frequency divider circuit.
Background technology
Existingly remove 2 and except the normal circuit form adopting as shown in Figure 1 of 3 bimodulus frequency dividing circuit.Should except 2 and except the operation principle of 3 bimodulus frequency dividing circuit as follows: when mode control signal is ' 0 ', the output of the NAND gate d ' being connected with it is exactly ' 1 ', in this time, this bimodulus frequency dividing circuit has been exactly frequency-halving circuit in fact, so the two divided-frequency result that output OUT is input CK; When mode control signal is ' 1 ', this bimodulus frequency dividing circuit has been exactly three frequency division circuit in fact, so the three frequency division result that output out is input CK.Therefore, this bimodulus frequency dividing circuit can complete except 2 with except 3 bimodulus division function.But, based on this bimodulus frequency dividing circuit structure, can't be generalized to the bimodulus frequency dividing circuit of other bimodulus frequency division value.
In addition, existing remove 4 and except the circuit of 5 dual-mode frequency dividers as shown in Figure 2 A, by Fig. 2 A except 4 and adopt modular structure except the circuit of 5 dual-mode frequency dividers, to simplify integrated circuit, be convenient to set forth, the circuit after modularization as shown in Figure 2 B.
In Fig. 2 A, when mode is ' 0 ', should and be 4 frequency dividing circuits except the circuit of 5 dual-mode frequency dividers is actual except 4, when mode be ' 1 ', should except 4 and to remove the circuit of 5 dual-mode frequency dividers actual be 5 frequency dividing circuits.On this basis, except 8 and except the circuit of 9 dual-mode frequency dividers as shown in Figure 3, wherein, when mode is ' 0 ', should and be 9 frequency dividing circuits except the circuit of 9 dual-mode frequency dividers is actual except 8, when mode be ' 1 ', should except 8 and to remove the circuit of 9 dual-mode frequency dividers actual be 8 frequency dividing circuits.Further, except 64 and except the circuit of 65 dual-mode frequency dividers as shown in Figure 4, wherein, when mode is ' 0 ', should and be 65 frequency dividing circuits except the circuit of 65 dual-mode frequency dividers is actual except 64, when mode be ' 1 ', should except 64 and to remove the circuit of 65 dual-mode frequency dividers actual be 64 frequency dividing circuits.
Although in prior art, can be according to based on except 4 with expand to except 8 with except 9 circuit except 5, and based on except 4 with expand to except 64 with except 65 circuit except 5, but clearly do not propose based on expanding to except 2N with except the universal circuit rule of 2N+1 except N with except N+1, more do not mention based on expanding to except 2N+1 with except the circuit methods of 2N+2 except N with except N+1.
Therefore, prior art is not told about the dual-mode frequency divider that how to expand to other bimodulus frequency division values, is inconvenient to design and remember.And prior art does not propose the dual-mode frequency divider structure that some frequency division values are prime number yet, has seriously hindered the design of some special occasions, very flexible.
Summary of the invention
Object of the present invention is intended to solve at least to a certain extent one of above-mentioned technological deficiency.
For this reason, the object of the invention is to propose a kind of dual-mode frequency divider circuit, be convenient to build actual required dual-mode frequency divider structure, convenient memory.
For achieving the above object, the dual-mode frequency divider circuit that embodiments of the invention propose, comprise: except N with except N+1 bimodulus frequency division module, describedly except N with except N+1 bimodulus frequency division module, comprise input, control end and output, under the control signal of described control end is controlled, described except N with except N+1 bimodulus frequency division module is for carrying out the input signal by described input Fractional-N frequency or N+1 frequency division to generate the first fractional frequency signal, wherein, N is more than or equal to 2 integer, the first trigger, the clock end of described the first trigger is connected with the output except N+1 bimodulus frequency division module with the described N that removes, for described the first fractional frequency signal is carried out to frequency division to generate the second fractional frequency signal, control model end, for inputting first mode signal and the second mode signal, and gate, the first input end of described gate is connected with the first output of described the first trigger, the output of described gate is connected with the control end except N+1 bimodulus frequency division module with the described N that removes, the second input of described gate is connected with described control model end, wherein, described in when described control model end input first mode signal, gate is controlled the described N of removing and is removed N+1 bimodulus frequency division module and is operated in the first frequency division pattern, described in when described control model end is inputted the second mode signal, gate is controlled the described N of removing and is removed N+1 bimodulus frequency division module according to described the second fractional frequency signal and switches between described the first frequency division pattern and divide-by-two mode.
According to the dual-mode frequency divider circuit of the embodiment of the present invention, can will carry out 2N and 2N+1 frequency division and 2N+1 and 2N+2 frequency division except N with except the input signal of the input of N+1 bimodulus frequency division module, be convenient to construct structure, the especially special frequency divider of some frequency division values of actual required dual-mode frequency divider.And convenient memory, flexibility is good.
The aspect that the present invention is additional and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Accompanying drawing explanation
Above-mentioned and/or the additional aspect of the present invention and advantage will become from the following description of the accompanying drawings of embodiments and obviously and easily understand, wherein:
Fig. 1 existingly removes 2 and except 3 bimodulus frequency dividing circuit schematic diagrames;
Fig. 2 A existingly removes 4 and except the circuit diagram of 5 dual-mode frequency dividers;
Fig. 2 B existingly removes 4 and except the illustraton of model of 5 dual-mode frequency dividers;
Fig. 3 a kind ofly removes 8 and except the circuit diagram of 9 dual-mode frequency dividers;
Fig. 4 a kind ofly removes 64 and except the circuit diagram of 65 dual-mode frequency dividers;
Fig. 5 is according to the schematic diagram of the dual-mode frequency divider circuit of the embodiment of the present invention;
Fig. 6 is the schematic diagram that removes according to an embodiment of the invention 2N and remove 2N+1 dual-mode frequency divider circuit;
Fig. 7 is the schematic diagram that removes in accordance with another embodiment of the present invention 2N+1 and remove 2N+2 dual-mode frequency divider circuit;
Fig. 8 be according to the present invention an example except 4 with except the schematic diagram of 5 dual-mode frequency divider circuit;
Fig. 9 A be according to the present invention another example except 8 with except the schematic diagram of 9 dual-mode frequency divider circuit;
Fig. 9 B be according to the present invention another example except 8 with except the model schematic diagram of 9 dual-mode frequency divider circuit;
Figure 10 be according to the present invention another example except 9 with except the schematic diagram of 10 dual-mode frequency divider circuit;
Figure 11 A is the schematic diagram that removes according to an embodiment of the invention 4N and remove 4N+1 dual-mode frequency divider circuit;
Figure 11 B is according to an embodiment of the invention except 4N with except the schematic diagram of 4N+1 dual-mode frequency divider circuit when N=4;
Figure 12 A is the schematic diagram that removes in accordance with another embodiment of the present invention 4N+1 and remove 4N+2 dual-mode frequency divider circuit;
Figure 12 B is in accordance with another embodiment of the present invention except 4N+1 with except the schematic diagram of 4N+2 dual-mode frequency divider circuit when N=4;
Figure 13 A be according to the present invention another embodiment except 4N+2 with except the schematic diagram of 4N+3 dual-mode frequency divider circuit;
Figure 13 B be according to the present invention another embodiment except 4N+2 with except the schematic diagram of 4N+3 dual-mode frequency divider circuit when N=4;
Figure 14 A be according to the present invention another embodiment except 4N+3 with except the schematic diagram of 4N+4 dual-mode frequency divider circuit; And
Figure 14 B be according to the present invention another embodiment except 4N+3 with except the schematic diagram of 4N+4 dual-mode frequency divider circuit when N=4.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Below by the embodiment being described with reference to the drawings, be exemplary, only for explaining the present invention, and can not be interpreted as limitation of the present invention.
Disclosing below provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts of specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and object clearly, itself do not indicate the relation between discussed various embodiment and/or setting.In addition, the various specific technique the invention provides and the example of material, but those of ordinary skills can recognize the property of can be applicable to of other techniques and/or the use of other materials.In addition, First Characteristic described below Second Characteristic it " on " structure can comprise that the first and second Characteristics creations are for the direct embodiment of contact, also can comprise the embodiment of other Characteristics creation between the first and second features, such the first and second features may not be direct contacts.
In description of the invention, it should be noted that, unless otherwise prescribed and limit, term " installation ", " being connected ", " connection " should be interpreted broadly, for example, can be mechanical connection or electrical connection, also can be the connection of two element internals, can be to be directly connected, and also can indirectly be connected by intermediary, for the ordinary skill in the art, can understand as the case may be the concrete meaning of above-mentioned term.
With reference to description and accompanying drawing below, these and other aspects of embodiments of the invention will be known.These describe and accompanying drawing in, specifically disclose some specific implementations in embodiments of the invention, represent to implement some modes of the principle of embodiments of the invention, still should be appreciated that the scope of embodiments of the invention is not limited.On the contrary, embodiments of the invention comprise spirit and all changes within the scope of intension, modification and the equivalent that falls into additional claims.
The dual-mode frequency divider circuit proposing according to the embodiment of the present invention is described with reference to the accompanying drawings.
As shown in Figure 5, the dual-mode frequency divider circuit that the embodiment of the present invention proposes comprises except N with except N+1 bimodulus frequency division module 501, the first trigger 502, control model end Mode and gate 503.
Wherein, remove N and remove N+1 bimodulus frequency division module 501 and comprise input in, control end m and output out, under the control signal of control end m is controlled, remove N and remove N+1 bimodulus frequency division module 501 for the signal CK inputting by input in being carried out to Fractional-N frequency or N+1 frequency division to generate the first fractional frequency signal, wherein, N is more than or equal to 2 integer.
As shown in Figure 5, the clock end ck of the first trigger 502 with except N with except the output out of N+1 bimodulus frequency division module 501, be connected, for above-mentioned the first fractional frequency signal is carried out to frequency division to generate the second fractional frequency signal.In a preferred exemplary of the present invention, as shown in Figure 6 and Figure 7, the first trigger 502 can be T trigger.Certainly, the first trigger 502 can be also d type flip flop, will be described in other embodiments of the invention, is understandable that, the first trigger 502 can be also other triggers.
Control model end Mode is for input pattern signal mode, and mode signal mode comprises first mode signal and the second mode signal.The first input end 1 of gate 503 is connected with the first output Q of the first trigger 502, the first output Q of the first trigger 502 is also the output OUT of this dual-mode frequency divider circuit, export the second fractional frequency signal, the output 3 of gate 503 with except N with except the control end m of N+1 bimodulus frequency division module 501, be connected, the second input 2 of gate 503 is connected with control model end Mode, wherein, when control model end Mode input first mode signal, gate 503 is controlled except N and is removed N+1 bimodulus frequency division module 501 and is operated in the first frequency division pattern, when control model end Mode inputs the second mode signal, gate 503 is controlled except N and is removed N+1 bimodulus frequency division module 501 according to the second fractional frequency signal and switches between the first frequency division pattern and divide-by-two mode.
In one embodiment of the invention, as shown in Figure 6, gate 503 be first with door 601 o'clock, the first frequency division pattern is Fractional-N frequency, divide-by-two mode is N+1 frequency division, so when control model end Mode input first mode signal is for example ' 0 ' time, the second fractional frequency signal is 2N frequency division, when control model end Mode inputs the second mode signal for example ' 1 ' time, the second fractional frequency signal is 2N+1 frequency division.That is to say, under the control of mode signal mode, first selects to carry out 2N frequency division except N with except the input signal CK of the input in of N+1 bimodulus frequency division module 501 with door 601 output control signals.And first can also select to carry out 2N+1 frequency division except N with except the input signal CK of the input in of N+1 bimodulus frequency division module 501 with door 601 output control signals under the control of mode signal mode.
Particularly, as shown in Figure 6, the bimodulus frequency division module 501 that removes N and remove N+1, when mode signal mode is ' 0 ', completes Fractional-N frequency, completes N+1 frequency division when mode signal mode is ' 1 '.When the input T of the first trigger T trigger 502 connects ' 1 ', on the clock of clock end ck, along arriving once, its output state just overturns once.
Thus, when mode signal mode is ' 0 ', what be connected with the first trigger T trigger 502 first 601 is output as ' 0 ' with door, except N and except the bimodulus frequency division module 501 of N+1 be Fractional-N frequency all the time.For convenient, explain, suppose except N and except the bimodulus frequency division module 501 of N+1 and the initial output valve of the first trigger T trigger 502 be ' 0 ', except N and except first output of the bimodulus frequency division module 501 of N+1 upper when coming, the output OUT of the first trigger T trigger 502 becomes ' 1 ', when completing Fractional-N frequency for the first time except N with except the bimodulus frequency division module 501 of N+1, export second upper along time, the output OUT of the first trigger T trigger 502 becomes ' 0 '; When completing Fractional-N frequency for the second time except N with except the bimodulus frequency division module 501 of N+1, export the 3rd upper along time, the output OUT of the first trigger T trigger 502 becomes ' 1 ', at this moment through twice Fractional-N frequency, allow the output OUT of the first trigger T trigger 502 complete a cycle output, so will carry out 2N frequency division except N with except the input signal CK of the input in of N+1 bimodulus frequency division module 501 like this.
When mode signal mode is ' 1 ', the output of first and the door 601 being connected with the first trigger T trigger 502 is exactly the output OUT of the first trigger T trigger 502.For convenient, explain, suppose except N and except the bimodulus frequency division module 501 of N+1 and the initial output valve of the first trigger T trigger 502 be ' 0 ', except N and except first output of the bimodulus frequency division module 501 of N+1 upper when coming, the output OUT of the first trigger T trigger 502 becomes ' 1 ', is switched to N+1 frequency division; When completing N+1 frequency division for the first time except N with except the bimodulus frequency division module 501 of N+1, export second go up along time, the output OUT of the first trigger T trigger 502 becomes ' 0 ', is at this moment switched to Fractional-N frequency; When completing Fractional-N frequency except N with except the bimodulus frequency division module 501 of N+1, export the 3rd upper along time, the output OUT of the first trigger T trigger 502 becomes ' 1 ', at this moment through a Fractional-N frequency and a N+1 frequency division, allow the output OUT of the first trigger T trigger 502 complete a cycle output, so will carry out 2N+1 frequency division except N with except the input signal CK of the input in of N+1 bimodulus frequency division module 501 like this.
In another embodiment of the present invention, as shown in Figure 7, when gate 503 is the first NAND gate 701, the first frequency division pattern is N+1 frequency division, divide-by-two mode is Fractional-N frequency, so when control model end Mode input first mode signal is for example ' 0 ' time, the second fractional frequency signal is 2N+2 frequency division, when control model end Mode inputs the second mode signal for example ' 1 ' time, the second fractional frequency signal is 2N+1 frequency division.In other words, under mode signal mode controls, the first NAND gate 701 output control signals are selected to carry out 2N+1 frequency division except N with except the input signal CK of the input in of N+1 bimodulus frequency division module 501.And the control signal of the first NAND gate 701 outputs can also be selected to carry out 2N+2 frequency division except N with except the input signal CK of the input in of N+1 bimodulus frequency division module 501 under mode signal mode controls.
Similarly, as shown in Figure 7, the bimodulus frequency division module 501 that removes N and remove N+1, when mode signal mode is ' 0 ', completes Fractional-N frequency, completes N+1 frequency division when mode signal mode is ' 1 '.When the input T of the first trigger T trigger 502 connects ' 1 ', on the clock of clock end ck, along arriving once, its output state just overturns once.
Therefore, when mode signal mode is ' 0 ', the first NAND gate 701 being connected with the first trigger T trigger 502 is output as ' 1 ', except N and except the bimodulus frequency division module 501 of N+1 be N+1 frequency division all the time.For convenient, explain, suppose except N and except the bimodulus frequency division module 501 of N+1 and the initial output valve of the first trigger T trigger 502 be ' 0 ', except N and except first output of the bimodulus frequency division module 501 of N+1 upper when coming, the output OUT of the first trigger T trigger 502 becomes ' 1 ', when completing N+1 frequency division for the first time except N with except the bimodulus frequency division module 501 of N+1, export second upper along time, the output OUT of the first trigger T trigger 502 becomes ' 0 '; When completing N+1 frequency division for the second time except N with except the bimodulus frequency division module 501 of N+1, export the 3rd upper along time, the output OUT of the first trigger T trigger 502 becomes ' 1 ', at this moment through twice N+1 frequency division, allow the output OUT of the first trigger T trigger 502 complete a cycle output, so will carry out 2N+2 frequency division except N with except the input signal CK of the input in of N+1 bimodulus frequency division module 501 like this.
When mode signal mode is ' 1 ', the output of the first NAND gate 701 being connected with the first trigger T trigger 502 is exactly the output OUT of the first trigger T trigger 502.For convenient, explain, suppose except N and except the bimodulus frequency division module 501 of N+1 and the initial output valve of the first trigger T trigger 502 be ' 0 ', except N and except first output of the bimodulus frequency division module 501 of N+1 upper when coming, the output OUT of the first trigger T trigger 502 becomes ' 1 ', is switched to Fractional-N frequency; When completing Fractional-N frequency for the first time except N with except the bimodulus frequency division module 501 of N+1, export second go up along time, the output OUT of the first trigger T trigger 502 becomes ' 0 ', is at this moment switched to N+1 frequency division; When completing N+1 frequency division except N with except the bimodulus frequency division module 501 of N+1, export the 3rd upper along time, the output OUT of the first trigger T trigger 502 becomes ' 1 ', at this moment through a N+1 frequency division and a Fractional-N frequency, allow the output OUT of the first trigger T trigger 502 complete a cycle output, so will carry out 2N+1 frequency division except N with except the input signal CK of the input in of N+1 bimodulus frequency division module 501 like this.
In an example of the present invention, in conjunction with Fig. 1 and Fig. 8, except 4 and except 5 dual-mode frequency divider circuit be except 2 with obtain except expanding on the basis of 3 dual-mode frequency divider circuit, wherein, should and comprise three d type flip flop a, b, c and two NAND gate d, e except 5 dual-mode frequency divider circuit except 4, and one with a door f.That is to say, when N=2, Fig. 8 is the unfolding circuits figure of Fig. 6, and substitutes T trigger by d type flip flop.Similarly, can draw, when mode signal mode is ' 0 ', should and realized input signal CK has been carried out to 4 frequency divisions except 5 dual-mode frequency divider circuit except 4, when mode signal mode is ' 1 ', should and realizes input signal CK had been carried out to 5 frequency divisions except 5 dual-mode frequency divider circuit except 4.
In another example of the present invention, as shown in Figure 9 A, except 8 and except 9 dual-mode frequency divider circuit be in Fig. 8 except 4 with obtain except expanding on the basis of 5 dual-mode frequency divider circuit, compare with Fig. 8, should except 8 and except 9 dual-mode frequency divider circuit many d type flip flop g and one and a h.Similarly, should except 8 and except 9 dual-mode frequency divider circuit can be also when N=4, by Fig. 6, launched to obtain, wherein by d type flip flop, substitute T trigger, so the first trigger 502 can be d type flip flop g, first with can for door h.The rest may be inferred, can draw, when mode signal mode is ' 0 ', should and realized input signal CK has been carried out to 8 frequency divisions except 9 dual-mode frequency divider circuit except 8, when mode signal mode is ' 1 ', should and realizes input signal CK had been carried out to 9 frequency divisions except 9 dual-mode frequency divider circuit except 8.And, should except 8 and except the simplified mode of 9 dual-mode frequency divider circuit as shown in Figure 9 B, wherein, except 4 and except 5 bimodulus frequency division modules 901 be in Fig. 8 except 4 with except the modularization of 5 dual-mode frequency divider circuit, diagram is just more clear like this, is convenient to understand and remember.
In another example of the present invention, as shown in figure 10, except 9, compare with Fig. 9 B with except 10 dual-mode frequency divider circuit, by a NAND gate 1001, substituted and door h.In other words, should except 9 and except 10 dual-mode frequency divider circuit can be also when N=4, by Fig. 7, extend and to obtain, wherein, by the alternative T trigger of d type flip flop, so the first trigger 502 can be d type flip flop g, the first NAND gate 701 can be NAND gate 1001.Similarly, can draw, when mode signal mode is ' 0 ', should and realized input signal CK has been carried out to 10 frequency divisions except 10 dual-mode frequency divider circuit except 9, when mode signal mode is ' 1 ', should and realizes input signal CK had been carried out to 9 frequency divisions except 10 dual-mode frequency divider circuit except 9.
In one embodiment of the invention, as shown in Figure 11 A, described dual-mode frequency divider circuit also comprise the second trigger 1102 and second and door 1101, wherein the first trigger 502 and the second trigger 1102 can be d type flip flop.
Say, the input D of the second trigger 1102 is connected with the second output NQ of the second trigger 1102, the clock end ck of the second trigger 1102 is connected with the first input end 1 of door h with first with the first output Q of the first trigger g respectively, and the second output NQ of the first trigger g is connected with the input D of the first trigger g, for above-mentioned the second fractional frequency signal is carried out to frequency division to generate three frequency division signal.Second is connected with the first input end 1 of door 1101 and the first output Q of the second trigger 1102, also be the output OUT of this dual-mode frequency divider circuit simultaneously, second is connected with control model end Mode with the second input 2 of door 1101, second is connected with the second input 2 of door h with first with the output 3 of door 1101, under controlling, mode signal mode will carry out 4N or 4N+1 except N with except the input signal CK of the input in of N+1 bimodulus frequency division module 501, when control model end Mode input first mode signal, three frequency division signal is 4N frequency division, when control model end Mode inputs the second mode signal, three frequency division signal is 4N+1 frequency division.
That is to say, when mode signal mode is ' 0 ', this dual-mode frequency divider circuit is realized input signal CK has been carried out to 4N frequency division, and when mode signal mode is ' 1 ', this dual-mode frequency divider circuit is realized input signal CK has been carried out to 4N+1 frequency division.
Particularly, as shown in Figure 11 B, when N=4, removing N and removing N+1 bimodulus frequency division module 501 is except 4 with except 5 bimodulus frequency division modules 901, when mode signal mode is ' 0 ', this dual-mode frequency divider circuit is realized input signal CK has been carried out to 16 frequency divisions, and when mode signal mode is ' 1 ', this dual-mode frequency divider circuit is realized input signal CK has been carried out to 17 frequency divisions.
In another embodiment of the present invention, as shown in Figure 12 A, described dual-mode frequency divider circuit also comprises the 3rd trigger 1202 and the second NAND gate 1201, wherein with d type flip flop, has substituted T trigger, and the first trigger 502 and the 3rd trigger 1202 can be d type flip flop.
Say, the input D of the 3rd trigger 1202 is connected with the second output NQ of the 3rd trigger 1202, the clock end ck of the 3rd trigger 1202 is connected with the first input end 1 of door h with first with the first output Q of the first trigger g respectively, and the second output NQ of the first trigger g is connected with the input D of the first trigger g, for the second fractional frequency signal being carried out to frequency division to generate the 4th fractional frequency signal.The first input end 1 of the second NAND gate 1201 is connected with the first output Q of the 3rd trigger 1202, also be the output OUT of this dual-mode frequency divider circuit simultaneously, the second input 2 of the second NAND gate 1201 is connected with control model end Mode, the output 3 of the second NAND gate 1201 is connected with the second input 2 of door h with first, under controlling, mode signal mode will carry out 4N+1 or 4N+2 frequency division except N with except the input signal CK of the input in of N+1 bimodulus frequency division module 501, when control model end Mode input first mode signal, the 4th fractional frequency signal is 4N+2 frequency division, when control model end Mode inputs the second mode signal, the 4th fractional frequency signal is 4N+1 frequency division.
That is to say, when mode signal mode is ' 0 ', this dual-mode frequency divider circuit is realized input signal CK has been carried out to 4N+2 frequency division, and when mode signal mode is ' 1 ', this dual-mode frequency divider circuit is realized input signal CK has been carried out to 4N+1 frequency division.
Particularly, as shown in Figure 12 B, when N=4, removing N and removing N+1 bimodulus frequency division module 501 is except 4 with except 5 bimodulus frequency division modules 901, when mode signal mode is ' 0 ', this dual-mode frequency divider circuit is realized input signal CK has been carried out to 18 frequency divisions, and when mode signal mode is ' 1 ', this dual-mode frequency divider circuit is realized input signal CK has been carried out to 17 frequency divisions.
In yet another embodiment of the present invention, as shown in FIG. 13A, described dual-mode frequency divider circuit also comprise the 4th trigger 1302, the first inverter 1303 and the 3rd with door 1301, wherein with d type flip flop, substituted T trigger, the first trigger 502 and the 4th trigger 1302 can be d type flip flop.
Say, the input D of the 4th trigger 1302 is connected with the second output NQ of the 4th trigger 1302, the clock end ck of the 4th trigger 1302 is connected with the first output Q of the first trigger g and the first input end 1 of the first NAND gate 1001 respectively, and the second output NQ of the first trigger g is connected with the input D of the first trigger g, for above-mentioned the second fractional frequency signal being carried out to frequency division to generate the 5th fractional frequency signal.The output of the first inverter 1303 is connected with the second input 2 of the first NAND gate 1001.The 3rd is connected with the first input end 1 of door 1301 and the first output Q of the 4th trigger 1302, the 3rd is connected with control model end Mode with the second input 2 of door 1301, the 3rd is connected with the input of the first inverter 1303 with the output 3 of door 1301, under the control of mode signal mode, will carry out 4N+2 or 4N+3 frequency division except N with except the input signal CK of the input in of N+1 bimodulus frequency division module 501, when control model end Mode input first mode signal, the 5th fractional frequency signal is 4N+2 frequency division, when control model end Mode inputs the second mode signal, the 5th fractional frequency signal is 4N+3 frequency division.
That is to say, when mode signal mode is ' 0 ', this dual-mode frequency divider circuit is realized input signal CK has been carried out to 4N+2 frequency division, and when mode signal mode is ' 1 ', this dual-mode frequency divider circuit is realized input signal CK has been carried out to 4N+3 frequency division.
Particularly, as shown in Figure 13 B, when N=4, removing N and removing N+1 bimodulus frequency division module 501 is except 4 with except 5 bimodulus frequency division modules 901, when mode signal mode is ' 0 ', this dual-mode frequency divider circuit is realized input signal CK has been carried out to 18 frequency divisions, and when mode signal mode is ' 1 ', this dual-mode frequency divider circuit is realized input signal CK has been carried out to 19 frequency divisions.And, add the first inverter 1303 objects and be allow except 9 and except 1303 inputs of 10 dual-mode frequency divider circuit be 9 frequency divisions for ' 0 ' time, be 10 frequency divisions for ' 1 ' time.
In another embodiment of the present invention, as shown in Figure 14 A, described dual-mode frequency divider circuit also comprises the 5th trigger 1402, the second inverter 1403 and the 3rd NAND gate 1401, wherein with d type flip flop, substituted T trigger, the first trigger 502 and the 5th trigger 1402 can be d type flip flop.
Say, the input D of the 5th trigger 1402 is connected with the second output NQ of the 5th trigger 1402, the clock end ck of the 5th trigger 1402 is connected with the first output Q of the first trigger g and the first input end 1 of the first NAND gate 1001 respectively, and the second output NQ of the first trigger g is connected with the input D of the first trigger g, for above-mentioned the second fractional frequency signal being carried out to frequency division to generate the 6th fractional frequency signal.The output of the second inverter 1403 is connected with the second input 2 of the first NAND gate 1001.The first input end 1 of the 3rd NAND gate 1401 is connected with the first output Q of the 5th trigger 1402, the second input 2 of the 3rd NAND gate 1401 is connected with control model end Mode, the output 3 of the 3rd NAND gate 1401 is connected with the input of the second inverter 1403, under the control of mode signal mode, will carry out 4N+3 or 4N+4 frequency division except N with except the input signal CK of the input in of N+1 bimodulus frequency division module 501, when control model end Mode input first mode signal, the 5th fractional frequency signal is 4N+4 frequency division, when control model end Mode inputs the second mode signal, the 5th fractional frequency signal is 4N+3 frequency division.
That is to say, when mode signal mode is ' 0 ', this dual-mode frequency divider circuit is realized input signal CK has been carried out to 4N+4 frequency division, and when mode signal mode is ' 1 ', this dual-mode frequency divider circuit is realized input signal CK has been carried out to 4N+3 frequency division.
Particularly, as shown in Figure 14B, when N=4, removing N and removing N+1 bimodulus frequency division module 501 is except 4 with except 5 bimodulus frequency division modules 901, when mode signal mode is ' 0 ', this dual-mode frequency divider circuit is realized input signal CK has been carried out to 20 frequency divisions, and when mode signal mode is ' 1 ', this dual-mode frequency divider circuit is realized input signal CK has been carried out to 19 frequency divisions.And, add the second inverter 1303 objects and be also allow except 9 and except 1403 inputs of 10 dual-mode frequency divider circuit be 9 frequency divisions for ' 0 ' time, be 10 frequency divisions for ' 1 ' time.
Be understandable that, embodiment described in Fig. 9 A and Figure 10 is only based on except N with except being extended on the basis of N+1 dual-mode frequency divider circuit except 2N with except the dual-mode frequency divider circuit of 2N+1 and except 2N+1 with except the specific embodiment of the bimodulus frequency dividing circuit of 2N+2, wherein N=4.And embodiment described in Figure 11 B and Figure 12 B is just based on except N with except being extended on the basis of N+1 dual-mode frequency divider circuit except 4N with except the dual-mode frequency divider circuit of 4N+1 and except 4N+1 with except the specific embodiment of the bimodulus frequency dividing circuit of 4N+2, wherein N=4.Finally, the embodiment described in Figure 13 B and Figure 14 B is just based on except N with except being extended on the basis of N+1 dual-mode frequency divider circuit except 4N+2 with except the dual-mode frequency divider circuit of 4N+3 and except 4N+3 with except the specific embodiment of the bimodulus frequency dividing circuit of 4N+4, wherein N=4.Therefore, on the basis of Fig. 6 and Fig. 7, only need to correspondingly add and door inclusive NAND door, just can build the dual-mode frequency divider circuit of frequency division value according to actual needs, the special dual-mode frequency divider circuit of some frequency division values particularly, such as except 11 with except 12 dual-mode frequency divider circuit etc., while only needing N=2, Figure 14 B can realize.
According to the dual-mode frequency divider circuit of the embodiment of the present invention, can will carry out 2N and 2N+1 frequency division and 2N+1 and 2N+2 frequency division except N with except the input signal of the input of N+1 bimodulus frequency division module, be convenient to construct structure, the especially special frequency divider of some frequency division values of actual required dual-mode frequency divider.And convenient memory, flexibility is good.
In the description of this specification, the description of reference term " embodiment ", " some embodiment ", " example ", " concrete example " or " some examples " etc. means to be contained at least one embodiment of the present invention or example in conjunction with specific features, structure, material or the feature of this embodiment or example description.In this manual, the schematic statement of above-mentioned term is not necessarily referred to identical embodiment or example.And the specific features of description, structure, material or feature can be with suitable mode combinations in any one or more embodiment or example.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification to these embodiment, scope of the present invention is by claims and be equal to and limit.
Claims (8)
1. a dual-mode frequency divider circuit, is characterized in that, comprising:
Except N with except N+1 bimodulus frequency division module, describedly except N with except N+1 bimodulus frequency division module, comprise input, control end and output, under the control signal of described control end is controlled, described except N with except N+1 bimodulus frequency division module is for carrying out the input signal by described input Fractional-N frequency or N+1 frequency division to generate the first fractional frequency signal, wherein, N is more than or equal to 2 integer;
The first trigger, the clock end of described the first trigger is connected with the output except N+1 bimodulus frequency division module with the described N that removes, for described the first fractional frequency signal is carried out to frequency division to generate the second fractional frequency signal;
Control model end, for inputting first mode signal and the second mode signal; And
Gate, the first input end of described gate is connected with the first output of described the first trigger, the output of described gate is connected with the control end except N+1 bimodulus frequency division module with the described N that removes, the second input of described gate is connected with described control model end, wherein, described in when described control model end input first mode signal, gate is controlled the described N of removing and is removed N+1 bimodulus frequency division module and is operated in the first frequency division pattern, described in when described control model end is inputted the second mode signal, gate is controlled the described N of removing and is removed N+1 bimodulus frequency division module according to described the second fractional frequency signal and switches between described the first frequency division pattern and divide-by-two mode.
2. dual-mode frequency divider circuit as claimed in claim 1, it is characterized in that, described gate be first with door, described the first frequency division pattern is Fractional-N frequency, described divide-by-two mode is N+1 frequency division, and when described control model end is inputted described first mode signal, described the second fractional frequency signal is 2N frequency division, when described control model end is inputted described the second mode signal, described the second fractional frequency signal is 2N+1 frequency division.
3. dual-mode frequency divider circuit as claimed in claim 1, it is characterized in that, described gate is the first NAND gate, described the first frequency division pattern is N+1 frequency division, described divide-by-two mode is Fractional-N frequency, and when described control model end is inputted described first mode signal, described the second fractional frequency signal is 2N+2 frequency division, when described control model end is inputted described the second mode signal, described the second fractional frequency signal is 2N+1 frequency division.
4. the dual-mode frequency divider circuit as described in claim 1-3 any one, is characterized in that, described the first trigger is T trigger or d type flip flop.
5. dual-mode frequency divider circuit as claimed in claim 2, is characterized in that, also comprises:
The second trigger, the input of described the second trigger is connected with the second output of described the second trigger, the clock end of described the second trigger is connected with the first input end of door with described first with the first output of described the first trigger respectively, and the second output of described the first trigger is connected with the input of described the first trigger, for described the second fractional frequency signal is carried out to frequency division to generate three frequency division signal;
Second with door, described second is connected with the first input end of door and the first output of described the second trigger, described second is connected with described control model end with the second input of door, described second is connected with the second input of door with described first with the output of door, when described control model end is inputted described first mode signal, described three frequency division signal is 4N frequency division, and when described control model end is inputted described the second mode signal, described three frequency division signal is 4N+1 frequency division.
6. dual-mode frequency divider circuit as claimed in claim 2, is characterized in that, also comprises:
The 3rd trigger, the input of described the 3rd trigger is connected with the second output of described the 3rd trigger, the clock end of described the 3rd trigger is connected with the first input end of door with described first with the first output of described the first trigger respectively, and the second output of described the first trigger is connected with the input of described the first trigger, for described the second fractional frequency signal being carried out to frequency division to generate the 4th fractional frequency signal;
The second NAND gate, the first input end of described the second NAND gate is connected with the first output of described the 3rd trigger, the second input of described the second NAND gate is connected with described control model end, the output of described the second NAND gate is connected with the second input of door with described first, when described control model end is inputted described first mode signal, described the 4th fractional frequency signal is 4N+2 frequency division, when described control model end is inputted described the second mode signal, described the 4th fractional frequency signal is 4N+1 frequency division.
7. dual-mode frequency divider circuit as claimed in claim 3, is characterized in that, also comprises:
The 4th trigger, the input of described the 4th trigger is connected with the second output of described the 4th trigger, the clock end of described the 4th trigger is connected with the first input end of described the first NAND gate with the first output of described the first trigger respectively, and the second output of described the first trigger is connected with the input of described the first trigger, for described the second fractional frequency signal being carried out to frequency division to generate the 5th fractional frequency signal;
The first inverter, the output of described the first inverter is connected with the second input of described the first NAND gate;
The 3rd with door, the described the 3rd is connected with the first output of described the 4th trigger with the first input end of door, the described the 3rd is connected with described control model end with the second input of door, the 3rd is connected with the input of described the first inverter with the output of door, when described control model end is inputted described first mode signal, described the 5th fractional frequency signal is 4N+2 frequency division, and when described control model end is inputted described the second mode signal, described the 5th fractional frequency signal is 4N+3 frequency division.
8. dual-mode frequency divider circuit as claimed in claim 3, is characterized in that, also comprises:
The 5th trigger, the input of described the 5th trigger is connected with the second output of described the 5th trigger, the clock end of described the 5th trigger is connected with the first input end of described the first NAND gate with the first output of described the first trigger respectively, and the second output of described the first trigger is connected with the input of described the first trigger, for described the second fractional frequency signal being carried out to frequency division to generate the 6th fractional frequency signal;
The second inverter, the output of described the second inverter is connected with the second input of described the first NAND gate;
The 3rd NAND gate, the first input end of described the 3rd NAND gate is connected with the first output of described the 5th trigger, the second input of described the 3rd NAND gate is connected with described control model end, the output of the 3rd NAND gate is connected with the input of described the second inverter, when described control model end is inputted described first mode signal, described the 5th fractional frequency signal is 4N+4 frequency division, and when described control model end is inputted described the second mode signal, described the 5th fractional frequency signal is 4N+3 frequency division.
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| CN107565965A (en) * | 2017-09-13 | 2018-01-09 | 东南大学 | A kind of 8 frequency dividings at a high speed and the 9 frequency dividing pre- frequency dividing circuits of bimodulus |
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| CN112769431A (en) * | 2019-11-06 | 2021-05-07 | 中芯国际集成电路制造(上海)有限公司 | Dual-mode frequency divider, phase-locked loop module and wireless communication device |
| CN112769431B (en) * | 2019-11-06 | 2024-04-02 | 中芯国际集成电路制造(上海)有限公司 | Dual-mode frequency divider, phase-locked loop module and wireless communication device |
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| CN116781065A (en) * | 2023-08-23 | 2023-09-19 | 芯潮流(珠海)科技有限公司 | High-speed asynchronous dual-mode prescaler, control method thereof and electronic equipment |
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